From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPEH3-0003kp-Jt for qemu-devel@nongnu.org; Fri, 19 Oct 2012 11:14:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TPEGw-0003gn-P1 for qemu-devel@nongnu.org; Fri, 19 Oct 2012 11:14:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:16602) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPEGw-0003gf-Gr for qemu-devel@nongnu.org; Fri, 19 Oct 2012 11:14:02 -0400 Date: Fri, 19 Oct 2012 11:13:53 -0400 From: Jason Baron Message-ID: <20121019151353.GB9682@redhat.com> References: <092c0acd50dc7d66ec0d46277e2fec207c41ffdf.1349749915.git.jbaron@redhat.com> <20121011145324.GI8983@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20121011145324.GI8983@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" , yamahata@valinux.co.jp Cc: agraf@suse.de, aliguori@us.ibm.com, juzhang@redhat.com, jan.kiszka@siemens.com, qemu-devel@nongnu.org, armbru@redhat.com, blauwirbel@gmail.com, alex.williamson@redhat.com, kevin@koconnor.net, avi@redhat.com, mkletzan@redhat.com, pbonzini@redhat.com, lcapitulino@redhat.com, afaerber@suse.de, kraxel@redhat.com On Thu, Oct 11, 2012 at 04:53:24PM +0200, Michael S. Tsirkin wrote: > On Mon, Oct 08, 2012 at 11:30:36PM -0400, Jason Baron wrote: > > From: Jan Kiszka > > > > Both bits are added to the write-1-to-clear mask by default. As the > > smbus device does not allow writes at all, we have to remove it from > > that mask, also to avoid triggering a runtime assertion. > > > > Signed-off-by: Jan Kiszka > > Signed-off-by: Jason Baron > > Yes but a bugger question for me is why are these writeable > while spec says they are W1C? > Could you please add a code comment explaining that? > Spec has these bits as: 'R/WC'. So I think you are right. We should drop the wmask setting. Also, I think the setting of w1cmask is inverted. Shouldn't we be setting the bits in w1cmask, not clearing them? Yamahata, any reason not to drop the setting of wmask here? Thanks, -Jason > > --- > > hw/q35_smbus.c | 4 ++++ > > 1 files changed, 4 insertions(+), 0 deletions(-) > > > > diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c > > index 5efbe6c..dd64aa2 100644 > > --- a/hw/q35_smbus.c > > +++ b/hw/q35_smbus.c > > @@ -97,6 +97,10 @@ static int ich9_smbus_initfn(PCIDevice *d) > > > > pci_set_word(d->wmask + PCI_STATUS, > > PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); > > + pci_set_word(d->w1cmask + PCI_STATUS, > > + pci_get_word(d->w1cmask + PCI_STATUS) & > > + ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY)); > > + > > /* TODO? D31IP.SMIP in chipset configuration space */ > > pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */ > > > > -- > > 1.7.1