From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52857) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPKgm-0003UV-2L for qemu-devel@nongnu.org; Fri, 19 Oct 2012 18:05:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TPKgk-0004ze-Hv for qemu-devel@nongnu.org; Fri, 19 Oct 2012 18:05:08 -0400 Received: from hall.aurel32.net ([88.191.126.93]:41993) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPKgk-0004xD-Bv for qemu-devel@nongnu.org; Fri, 19 Oct 2012 18:05:06 -0400 Date: Sat, 20 Oct 2012 00:05:03 +0200 From: Aurelien Jarno Message-ID: <20121019220503.GA5261@ohm.aurel32.net> References: <1350652019-25946-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1350652019-25946-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH v2 0/2] target-arm: inline abs, 64-bit negate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Fri, Oct 19, 2012 at 02:06:57PM +0100, Peter Maydell wrote: > Two minor patches which inline some operations rather than using helper > functions. The 64 bit negate is a no-brainer since there's a simple > TCG op for it. For abs we implement in terms of movcond: > movi_i32 tmp6,$0x0 > neg_i32 tmp7,tmp5 > movcond_i32 tmp5,tmp5,tmp6,tmp5,tmp7,gt > which the x86-64 backend turns into: > 0x603b53a7: mov %ebp,%ebx > 0x603b53a9: neg %ebx > 0x603b53ab: mov %ebp,%r12d > 0x603b53ae: test %ebp,%ebp > 0x603b53b0: cmovle %ebx,%r12d > > Not sure why it felt the need to use an extra move there, but Difficult to say without saying the whole TB, but likely because both %ebp and %r12d are not dead after the movcond, and are used separately. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net