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Date: Mon, 29 Oct 2012 14:54:55 +0100
From: Aurelien Jarno <aurelien@aurel32.net>
Message-ID: <20121029135455.GA28797@ohm.aurel32.net>
References: <1351486220-26216-1-git-send-email-rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH] target-sparc: Revert setting cpu_dst to
	gen_dest_gpr
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To: Richard Henderson <rth@twiddle.net>
Cc: Blue Swirl <blauwirbel@gmail.com>, qemu-devel@nongnu.org

On Mon, Oct 29, 2012 at 03:50:20PM +1100, Richard Henderson wrote:
> There is some read-after-write error within the OP=2 insns which
> prevents setting cpu_dst to the real output register.  Until this
> is found and fixed, always write to a temporary first.
> 
> Cc: Blue Swirl <blauwirbel@gmail.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  target-sparc/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 4321393..9e46f14 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -2633,7 +2633,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>      case 2:                     /* FPU & Logical Operations */
>          {
>              unsigned int xop = GET_FIELD(insn, 7, 12);
> -            TCGv cpu_dst = gen_dest_gpr(dc, rd);
> +            TCGv cpu_dst = get_temp_tl(dc);
>              TCGv cpu_tmp0;
>  
>              if (xop == 0x3a) {  /* generate trap */

Tested-by: Aurelien Jarno <aurelien@aurel32.net>


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net