* [Qemu-devel] [PATCH v1 01/13] pc/piix_pci: factor out smram/pam logic
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 19:07 ` Anthony Liguori
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 02/13] Back out add of i21154 Jason Baron
` (12 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jbaron@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/i386/Makefile.objs | 1 +
hw/pam.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
hw/pam.h | 97 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/piix_pci.c | 68 ++++++++---------------------------
4 files changed, 200 insertions(+), 53 deletions(-)
create mode 100644 hw/pam.c
create mode 100644 hw/pam.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index d400d1a..693bd18 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
obj-y += debugcon.o multiboot.o
obj-y += pc_piix.o
obj-y += pc_sysfw.o
+obj-y += pam.o
obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
diff --git a/hw/pam.c b/hw/pam.c
new file mode 100644
index 0000000..a95e2cf
--- /dev/null
+++ b/hw/pam.c
@@ -0,0 +1,87 @@
+/*
+ * QEMU i440FX/PIIX3 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * Split out from piix_pci.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "sysemu.h"
+#include "pam.h"
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+ uint8_t smm_enabled)
+{
+ bool smram_enabled;
+
+ smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
+ (smram & SMRAM_D_OPEN));
+ memory_region_set_enabled(smram_region, !smram_enabled);
+}
+
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+ MemoryRegion *smram_region)
+{
+ uint8_t smm_enabled = (smm != 0);
+ if (*host_smm_enabled != smm_enabled) {
+ *host_smm_enabled = smm_enabled;
+ smram_update(smram_region, smram, *host_smm_enabled);
+ }
+}
+
+void init_pam(MemoryRegion *ram_memory, MemoryRegion *system_memory,
+ MemoryRegion *pci_address_space, PAMMemoryRegion *mem,
+ uint32_t start, uint32_t size)
+{
+ int i;
+
+ /* RAM */
+ memory_region_init_alias(&mem->alias[3], "pam-ram", ram_memory,
+ start, size);
+ /* ROM (XXX: not quite correct) */
+ memory_region_init_alias(&mem->alias[1], "pam-rom", ram_memory,
+ start, size);
+ memory_region_set_readonly(&mem->alias[1], true);
+
+ /* XXX: should distinguish read/write cases */
+ memory_region_init_alias(&mem->alias[0], "pam-pci", pci_address_space,
+ start, size);
+ memory_region_init_alias(&mem->alias[2], "pam-pci", pci_address_space,
+ start, size);
+
+ for (i = 0; i < 4; ++i) {
+ memory_region_set_enabled(&mem->alias[i], false);
+ memory_region_add_subregion_overlap(system_memory, start,
+ &mem->alias[i], 1);
+ }
+ mem->current = 0;
+}
+
+void pam_update(PAMMemoryRegion *pam, int idx, uint8_t val)
+{
+ assert(0 <= idx && idx <= 12);
+
+ memory_region_set_enabled(&pam->alias[pam->current], false);
+ pam->current = (val >> ((!(idx & 1)) * 4)) & PAM_ATTR_MASK;
+ memory_region_set_enabled(&pam->alias[pam->current], true);
+}
diff --git a/hw/pam.h b/hw/pam.h
new file mode 100644
index 0000000..2d77ebe
--- /dev/null
+++ b/hw/pam.h
@@ -0,0 +1,97 @@
+#ifndef QEMU_PAM_H
+#define QEMU_PAM_H
+
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * Split out from piix_pci.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * SMRAM memory area and PAM memory area in Legacy address range for PC.
+ * PAM: Programmable Attribute Map registers
+ *
+ * 0xa0000 - 0xbffff compatible SMRAM
+ *
+ * 0xc0000 - 0xc3fff Expansion area memory segments
+ * 0xc4000 - 0xc7fff
+ * 0xc8000 - 0xcbfff
+ * 0xcc000 - 0xcffff
+ * 0xd0000 - 0xd3fff
+ * 0xd4000 - 0xd7fff
+ * 0xd8000 - 0xdbfff
+ * 0xdc000 - 0xdffff
+ * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
+ * 0xe4000 - 0xe7fff
+ * 0xe8000 - 0xebfff
+ * 0xec000 - 0xeffff
+ *
+ * 0xf0000 - 0xfffff System BIOS Area Memory Segments
+ */
+
+#include "qemu-common.h"
+#include "memory.h"
+
+#define SMRAM_C_BASE 0xa0000
+#define SMRAM_C_END 0xc0000
+#define SMRAM_C_SIZE 0x20000
+
+#define PAM_EXPAN_BASE 0xc0000
+#define PAM_EXPAN_SIZE 0x04000
+
+#define PAM_EXBIOS_BASE 0xe0000
+#define PAM_EXBIOS_SIZE 0x04000
+
+#define PAM_BIOS_BASE 0xf0000
+#define PAM_BIOS_END 0xfffff
+/* 64KB: Intel 3 series express chipset family p. 58*/
+#define PAM_BIOS_SIZE 0x10000
+
+/* PAM registers: log nibble and high nibble*/
+#define PAM_ATTR_WE ((uint8_t)2)
+#define PAM_ATTR_RE ((uint8_t)1)
+#define PAM_ATTR_MASK ((uint8_t)3)
+
+/* SMRAM register */
+#define SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
+
+typedef struct PAMMemoryRegion {
+ MemoryRegion alias[4]; /* index = PAM value */
+ unsigned current;
+} PAMMemoryRegion;
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+ uint8_t smm_enabled);
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+ MemoryRegion *smram_region);
+void init_pam(MemoryRegion *ram, MemoryRegion *system, MemoryRegion *pci,
+ PAMMemoryRegion *mem, uint32_t start, uint32_t size);
+void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val);
+
+#endif /* QEMU_PAM_H */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 9af5847..ba1b3de 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -30,6 +30,7 @@
#include "sysbus.h"
#include "range.h"
#include "xen.h"
+#include "pam.h"
/*
* I440FX chipset data sheet.
@@ -68,11 +69,6 @@ typedef struct PIIX3State {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;
-typedef struct PAMMemoryRegion {
- MemoryRegion alias[4]; /* index = PAM value */
- unsigned current;
-} PAMMemoryRegion;
-
struct PCII440FXState {
PCIDevice dev;
MemoryRegion *system_memory;
@@ -105,52 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void init_pam(PCII440FXState *d, PAMMemoryRegion *mem,
- uint32_t start, uint32_t size)
-{
- int i;
-
- /* RAM */
- memory_region_init_alias(&mem->alias[3], "pam-ram", d->ram_memory, start, size);
- /* ROM (XXX: not quite correct) */
- memory_region_init_alias(&mem->alias[1], "pam-rom", d->ram_memory, start, size);
- memory_region_set_readonly(&mem->alias[1], true);
-
- /* XXX: should distinguish read/write cases */
- memory_region_init_alias(&mem->alias[0], "pam-pci", d->pci_address_space,
- start, size);
- memory_region_init_alias(&mem->alias[2], "pam-pci", d->pci_address_space,
- start, size);
-
- for (i = 0; i < 4; ++i) {
- memory_region_set_enabled(&mem->alias[i], false);
- memory_region_add_subregion_overlap(d->system_memory, start, &mem->alias[i], 1);
- }
- mem->current = 0;
-}
-
-static void update_pam(PAMMemoryRegion *pam, unsigned r)
-{
- memory_region_set_enabled(&pam->alias[pam->current], false);
- pam->current = r;
- memory_region_set_enabled(&pam->alias[pam->current], true);
-}
-
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
- int i, r;
- uint32_t smram;
- bool smram_enabled;
+ int i;
memory_region_transaction_begin();
- update_pam(&d->pam_regions[0], (d->dev.config[I440FX_PAM] >> 4) & 3);
- for(i = 0; i < 12; i++) {
- r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
- update_pam(&d->pam_regions[i+1], r);
+ for (i = 0; i < 13; i++) {
+ pam_update(&d->pam_regions[i], i,
+ d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
}
- smram = d->dev.config[I440FX_SMRAM];
- smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
- memory_region_set_enabled(&d->smram_region, !smram_enabled);
+ smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
memory_region_transaction_commit();
}
@@ -158,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
{
PCII440FXState *d = arg;
- val = (val != 0);
- if (d->smm_enabled != val) {
- d->smm_enabled = val;
- i440fx_update_memory_mappings(d);
- }
+ memory_region_transaction_begin();
+ smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
+ &d->smram_region);
+ memory_region_transaction_commit();
}
@@ -300,9 +259,12 @@ static PCIBus *i440fx_common_init(const char *device_name,
memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
&f->smram_region, 1);
memory_region_set_enabled(&f->smram_region, false);
- init_pam(f, &f->pam_regions[0], 0xf0000, 0x10000);
+ init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
+ &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
for (i = 0; i < 12; ++i) {
- init_pam(f, &f->pam_regions[i+1], 0xc0000 + i * 0x4000, 0x4000);
+ init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
+ &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
+ PAM_EXPAN_SIZE);
}
/* Xen supports additional interrupt routes from the PCI devices to
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 01/13] pc/piix_pci: factor out smram/pam logic
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 01/13] pc/piix_pci: factor out smram/pam logic Jason Baron
@ 2012-10-30 19:07 ` Anthony Liguori
2012-10-30 20:26 ` Andreas Färber
0 siblings, 1 reply; 35+ messages in thread
From: Anthony Liguori @ 2012-10-30 19:07 UTC (permalink / raw)
To: Jason Baron, qemu-devel
Cc: juzhang, mst, jan.kiszka, agraf, armbru, blauwirbel, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, kraxel
Jason Baron <jbaron@redhat.com> writes:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Factor out smram/pam logic for later use.
> Which will be used by q35 too.
>
> [jbaron@redhat.com: changes for updated memory API]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
This is really not the right approach to solving this problem.
"pam" is not a device.
Instead, the common bits here are essentially the northbridge logic.
That's what we should model here.
It's pretty simple actually. Just throw this all into a device where
the memory regions are owned by the device. But also make the device
own creation of all RAM (not just the areas controlled by PAM).
Then embed the northbridge into the i440fx and q35.
Regards,
Anthony Liguori
> ---
> hw/i386/Makefile.objs | 1 +
> hw/pam.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
> hw/pam.h | 97 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/piix_pci.c | 68 ++++++++---------------------------
> 4 files changed, 200 insertions(+), 53 deletions(-)
> create mode 100644 hw/pam.c
> create mode 100644 hw/pam.h
>
> diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
> index d400d1a..693bd18 100644
> --- a/hw/i386/Makefile.objs
> +++ b/hw/i386/Makefile.objs
> @@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
> obj-y += debugcon.o multiboot.o
> obj-y += pc_piix.o
> obj-y += pc_sysfw.o
> +obj-y += pam.o
> obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
> obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
> diff --git a/hw/pam.c b/hw/pam.c
> new file mode 100644
> index 0000000..a95e2cf
> --- /dev/null
> +++ b/hw/pam.c
> @@ -0,0 +1,87 @@
> +/*
> + * QEMU i440FX/PIIX3 PCI Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * Split out from piix_pci.c
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "sysemu.h"
> +#include "pam.h"
> +
> +void smram_update(MemoryRegion *smram_region, uint8_t smram,
> + uint8_t smm_enabled)
> +{
> + bool smram_enabled;
> +
> + smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
> + (smram & SMRAM_D_OPEN));
> + memory_region_set_enabled(smram_region, !smram_enabled);
> +}
> +
> +void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
> + MemoryRegion *smram_region)
> +{
> + uint8_t smm_enabled = (smm != 0);
> + if (*host_smm_enabled != smm_enabled) {
> + *host_smm_enabled = smm_enabled;
> + smram_update(smram_region, smram, *host_smm_enabled);
> + }
> +}
> +
> +void init_pam(MemoryRegion *ram_memory, MemoryRegion *system_memory,
> + MemoryRegion *pci_address_space, PAMMemoryRegion *mem,
> + uint32_t start, uint32_t size)
> +{
> + int i;
> +
> + /* RAM */
> + memory_region_init_alias(&mem->alias[3], "pam-ram", ram_memory,
> + start, size);
> + /* ROM (XXX: not quite correct) */
> + memory_region_init_alias(&mem->alias[1], "pam-rom", ram_memory,
> + start, size);
> + memory_region_set_readonly(&mem->alias[1], true);
> +
> + /* XXX: should distinguish read/write cases */
> + memory_region_init_alias(&mem->alias[0], "pam-pci", pci_address_space,
> + start, size);
> + memory_region_init_alias(&mem->alias[2], "pam-pci", pci_address_space,
> + start, size);
> +
> + for (i = 0; i < 4; ++i) {
> + memory_region_set_enabled(&mem->alias[i], false);
> + memory_region_add_subregion_overlap(system_memory, start,
> + &mem->alias[i], 1);
> + }
> + mem->current = 0;
> +}
> +
> +void pam_update(PAMMemoryRegion *pam, int idx, uint8_t val)
> +{
> + assert(0 <= idx && idx <= 12);
> +
> + memory_region_set_enabled(&pam->alias[pam->current], false);
> + pam->current = (val >> ((!(idx & 1)) * 4)) & PAM_ATTR_MASK;
> + memory_region_set_enabled(&pam->alias[pam->current], true);
> +}
> diff --git a/hw/pam.h b/hw/pam.h
> new file mode 100644
> index 0000000..2d77ebe
> --- /dev/null
> +++ b/hw/pam.h
> @@ -0,0 +1,97 @@
> +#ifndef QEMU_PAM_H
> +#define QEMU_PAM_H
> +
> +/*
> + * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * Split out from piix_pci.c
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +/*
> + * SMRAM memory area and PAM memory area in Legacy address range for PC.
> + * PAM: Programmable Attribute Map registers
> + *
> + * 0xa0000 - 0xbffff compatible SMRAM
> + *
> + * 0xc0000 - 0xc3fff Expansion area memory segments
> + * 0xc4000 - 0xc7fff
> + * 0xc8000 - 0xcbfff
> + * 0xcc000 - 0xcffff
> + * 0xd0000 - 0xd3fff
> + * 0xd4000 - 0xd7fff
> + * 0xd8000 - 0xdbfff
> + * 0xdc000 - 0xdffff
> + * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
> + * 0xe4000 - 0xe7fff
> + * 0xe8000 - 0xebfff
> + * 0xec000 - 0xeffff
> + *
> + * 0xf0000 - 0xfffff System BIOS Area Memory Segments
> + */
> +
> +#include "qemu-common.h"
> +#include "memory.h"
> +
> +#define SMRAM_C_BASE 0xa0000
> +#define SMRAM_C_END 0xc0000
> +#define SMRAM_C_SIZE 0x20000
> +
> +#define PAM_EXPAN_BASE 0xc0000
> +#define PAM_EXPAN_SIZE 0x04000
> +
> +#define PAM_EXBIOS_BASE 0xe0000
> +#define PAM_EXBIOS_SIZE 0x04000
> +
> +#define PAM_BIOS_BASE 0xf0000
> +#define PAM_BIOS_END 0xfffff
> +/* 64KB: Intel 3 series express chipset family p. 58*/
> +#define PAM_BIOS_SIZE 0x10000
> +
> +/* PAM registers: log nibble and high nibble*/
> +#define PAM_ATTR_WE ((uint8_t)2)
> +#define PAM_ATTR_RE ((uint8_t)1)
> +#define PAM_ATTR_MASK ((uint8_t)3)
> +
> +/* SMRAM register */
> +#define SMRAM_D_OPEN ((uint8_t)(1 << 6))
> +#define SMRAM_D_CLS ((uint8_t)(1 << 5))
> +#define SMRAM_D_LCK ((uint8_t)(1 << 4))
> +#define SMRAM_G_SMRAME ((uint8_t)(1 << 3))
> +#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
> +#define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
> +
> +typedef struct PAMMemoryRegion {
> + MemoryRegion alias[4]; /* index = PAM value */
> + unsigned current;
> +} PAMMemoryRegion;
> +
> +void smram_update(MemoryRegion *smram_region, uint8_t smram,
> + uint8_t smm_enabled);
> +void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
> + MemoryRegion *smram_region);
> +void init_pam(MemoryRegion *ram, MemoryRegion *system, MemoryRegion *pci,
> + PAMMemoryRegion *mem, uint32_t start, uint32_t size);
> +void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val);
> +
> +#endif /* QEMU_PAM_H */
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 9af5847..ba1b3de 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -30,6 +30,7 @@
> #include "sysbus.h"
> #include "range.h"
> #include "xen.h"
> +#include "pam.h"
>
> /*
> * I440FX chipset data sheet.
> @@ -68,11 +69,6 @@ typedef struct PIIX3State {
> int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> } PIIX3State;
>
> -typedef struct PAMMemoryRegion {
> - MemoryRegion alias[4]; /* index = PAM value */
> - unsigned current;
> -} PAMMemoryRegion;
> -
> struct PCII440FXState {
> PCIDevice dev;
> MemoryRegion *system_memory;
> @@ -105,52 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> return (pci_intx + slot_addend) & 3;
> }
>
> -static void init_pam(PCII440FXState *d, PAMMemoryRegion *mem,
> - uint32_t start, uint32_t size)
> -{
> - int i;
> -
> - /* RAM */
> - memory_region_init_alias(&mem->alias[3], "pam-ram", d->ram_memory, start, size);
> - /* ROM (XXX: not quite correct) */
> - memory_region_init_alias(&mem->alias[1], "pam-rom", d->ram_memory, start, size);
> - memory_region_set_readonly(&mem->alias[1], true);
> -
> - /* XXX: should distinguish read/write cases */
> - memory_region_init_alias(&mem->alias[0], "pam-pci", d->pci_address_space,
> - start, size);
> - memory_region_init_alias(&mem->alias[2], "pam-pci", d->pci_address_space,
> - start, size);
> -
> - for (i = 0; i < 4; ++i) {
> - memory_region_set_enabled(&mem->alias[i], false);
> - memory_region_add_subregion_overlap(d->system_memory, start, &mem->alias[i], 1);
> - }
> - mem->current = 0;
> -}
> -
> -static void update_pam(PAMMemoryRegion *pam, unsigned r)
> -{
> - memory_region_set_enabled(&pam->alias[pam->current], false);
> - pam->current = r;
> - memory_region_set_enabled(&pam->alias[pam->current], true);
> -}
> -
> static void i440fx_update_memory_mappings(PCII440FXState *d)
> {
> - int i, r;
> - uint32_t smram;
> - bool smram_enabled;
> + int i;
>
> memory_region_transaction_begin();
> - update_pam(&d->pam_regions[0], (d->dev.config[I440FX_PAM] >> 4) & 3);
> - for(i = 0; i < 12; i++) {
> - r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
> - update_pam(&d->pam_regions[i+1], r);
> + for (i = 0; i < 13; i++) {
> + pam_update(&d->pam_regions[i], i,
> + d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
> }
> - smram = d->dev.config[I440FX_SMRAM];
> - smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
> - memory_region_set_enabled(&d->smram_region, !smram_enabled);
> + smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
> memory_region_transaction_commit();
> }
>
> @@ -158,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
> {
> PCII440FXState *d = arg;
>
> - val = (val != 0);
> - if (d->smm_enabled != val) {
> - d->smm_enabled = val;
> - i440fx_update_memory_mappings(d);
> - }
> + memory_region_transaction_begin();
> + smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
> + &d->smram_region);
> + memory_region_transaction_commit();
> }
>
>
> @@ -300,9 +259,12 @@ static PCIBus *i440fx_common_init(const char *device_name,
> memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
> &f->smram_region, 1);
> memory_region_set_enabled(&f->smram_region, false);
> - init_pam(f, &f->pam_regions[0], 0xf0000, 0x10000);
> + init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
> + &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
> for (i = 0; i < 12; ++i) {
> - init_pam(f, &f->pam_regions[i+1], 0xc0000 + i * 0x4000, 0x4000);
> + init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
> + &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
> + PAM_EXPAN_SIZE);
> }
>
> /* Xen supports additional interrupt routes from the PCI devices to
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 01/13] pc/piix_pci: factor out smram/pam logic
2012-10-30 19:07 ` Anthony Liguori
@ 2012-10-30 20:26 ` Andreas Färber
0 siblings, 0 replies; 35+ messages in thread
From: Andreas Färber @ 2012-10-30 20:26 UTC (permalink / raw)
To: Anthony Liguori, Wanpeng Li
Cc: juzhang, mst, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, armbru, kraxel
Am 30.10.2012 20:07, schrieb Anthony Liguori:
> Jason Baron <jbaron@redhat.com> writes:
>
>> From: Isaku Yamahata <yamahata@valinux.co.jp>
>>
>> Factor out smram/pam logic for later use.
>> Which will be used by q35 too.
>>
>> [jbaron@redhat.com: changes for updated memory API]
>> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
>> Signed-off-by: Jason Baron <jbaron@redhat.com>
>
> This is really not the right approach to solving this problem.
>
> "pam" is not a device.
>
> Instead, the common bits here are essentially the northbridge logic.
> That's what we should model here.
>
> It's pretty simple actually. Just throw this all into a device where
> the memory regions are owned by the device. But also make the device
> own creation of all RAM (not just the areas controlled by PAM).
>
> Then embed the northbridge into the i440fx and q35.
Anthony/Wanpeng, any update on i440fx? Haven't heard of it since we
finally merged the PCI host bridge stuff for v1.2...
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 02/13] Back out add of i21154
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 01/13] pc/piix_pci: factor out smram/pam logic Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-31 9:54 ` Michael S. Tsirkin
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 03/13] blockdev: Introduce QEMUMachine->default_drive_if Jason Baron
` (11 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
As pointed out by Andreas Färber this is covered by dec_pci.c.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/Makefile.objs | 2 +-
hw/i21154.c | 113 ------------------------------------------------------
hw/i21154.h | 9 ----
3 files changed, 1 insertions(+), 123 deletions(-)
delete mode 100644 hw/i21154.c
delete mode 100644 hw/i21154.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index e951eba..a816e7e 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -9,7 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o
common-obj-$(CONFIG_PCI) += slotid_cap.o
common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
-common-obj-$(CONFIG_PCI) += i82801b11.o i21154.o
+common-obj-$(CONFIG_PCI) += i82801b11.o
common-obj-y += watchdog.o
common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
common-obj-$(CONFIG_ECC) += ecc.o
diff --git a/hw/i21154.c b/hw/i21154.c
deleted file mode 100644
index 93faa59..0000000
--- a/hw/i21154.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-/*
- * QEMU i21154 PCI Bridge Emulation
- *
- * Copyright (c) 2009, 2010, 2011
- * Isaku Yamahata <yamahata at valinux co jp>
- * VA Linux Systems Japan K.K.
- * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-
-#include "i21154.h"
-#include "pci_ids.h"
-#include "pci.h"
-#include "pci_bridge.h"
-#include "pci_internals.h"
-
-/* i21154 pci bridge*/
-
-typedef struct I21154Bridge {
- PCIBridge br;
-} I21154Bridge;
-
-static int i21154_bridge_initfn(PCIDevice *d)
-{
- int rc;
-
- rc = pci_bridge_initfn(d);
- if (rc < 0) {
- return rc;
- }
-
- return 0;
-}
-
-#define I21154_REV 0x05
-#define I21154_PI 0x00
-
-static void i21154_bridge_class_init(ObjectClass *klass, void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->is_bridge = 1;
- k->vendor_id = PCI_VENDOR_ID_DEC;
- k->device_id = PCI_DEVICE_ID_DEC_21154;
- k->revision = I21154_REV;
- k->init = i21154_bridge_initfn;
-}
-
-static const TypeInfo i21154_bridge_info = {
- .name = "i21154-bridge",
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(I21154Bridge),
- .class_init = i21154_bridge_class_init,
-};
-
-PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
- bool multifunction)
-{
- PCIDevice *d;
- PCIBridge *br;
- DeviceState *qdev;
-
- d = pci_create_multifunction(bus, devfn, multifunction, "i21154-bridge");
- if (!d) {
- return NULL;
- }
- br = DO_UPCAST(PCIBridge, dev, d);
- qdev = &br->dev.qdev;
-
- pci_bridge_map_irq(br, bus_name, pci_swizzle_map_irq_fn);
- qdev_init_nofail(qdev);
-
- return br;
-}
-
-static void i21154_register(void)
-{
- type_register_static(&i21154_bridge_info);
-}
-type_init(i21154_register);
diff --git a/hw/i21154.h b/hw/i21154.h
deleted file mode 100644
index 0cf8753..0000000
--- a/hw/i21154.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef QEMU_I21154_H
-#define QEMU_I21154_H
-
-#include "pci.h"
-
-PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
- bool multifunction);
-
-#endif /* QEMU_I21154_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 02/13] Back out add of i21154
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 02/13] Back out add of i21154 Jason Baron
@ 2012-10-31 9:54 ` Michael S. Tsirkin
0 siblings, 0 replies; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 9:54 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 29, 2012 at 10:11:24PM -0400, Jason Baron wrote:
> From: Jason Baron <jbaron@redhat.com>
>
> As pointed out by Andreas Färber this is covered by dec_pci.c.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Revision is different though, and generally dec_pci looks like
it needs some fixups. For now I'll just drop that patch from the tree.
> ---
> hw/Makefile.objs | 2 +-
> hw/i21154.c | 113 ------------------------------------------------------
> hw/i21154.h | 9 ----
> 3 files changed, 1 insertions(+), 123 deletions(-)
> delete mode 100644 hw/i21154.c
> delete mode 100644 hw/i21154.h
>
> diff --git a/hw/Makefile.objs b/hw/Makefile.objs
> index e951eba..a816e7e 100644
> --- a/hw/Makefile.objs
> +++ b/hw/Makefile.objs
> @@ -9,7 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o
> common-obj-$(CONFIG_PCI) += slotid_cap.o
> common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> -common-obj-$(CONFIG_PCI) += i82801b11.o i21154.o
> +common-obj-$(CONFIG_PCI) += i82801b11.o
> common-obj-y += watchdog.o
> common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
> common-obj-$(CONFIG_ECC) += ecc.o
> diff --git a/hw/i21154.c b/hw/i21154.c
> deleted file mode 100644
> index 93faa59..0000000
> --- a/hw/i21154.c
> +++ /dev/null
> @@ -1,113 +0,0 @@
> -/*
> - * Copyright (c) 2006 Fabrice Bellard
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a copy
> - * of this software and associated documentation files (the "Software"), to deal
> - * in the Software without restriction, including without limitation the rights
> - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> - * copies of the Software, and to permit persons to whom the Software is
> - * furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> - * THE SOFTWARE.
> - */
> -/*
> - * QEMU i21154 PCI Bridge Emulation
> - *
> - * Copyright (c) 2009, 2010, 2011
> - * Isaku Yamahata <yamahata at valinux co jp>
> - * VA Linux Systems Japan K.K.
> - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> - *
> - * This library is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU Lesser General Public
> - * License as published by the Free Software Foundation; either
> - * version 2 of the License, or (at your option) any later version.
> - *
> - * This library is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> - * Lesser General Public License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public
> - * License along with this library; if not, see <http://www.gnu.org/licenses/>
> - */
> -
> -#include "i21154.h"
> -#include "pci_ids.h"
> -#include "pci.h"
> -#include "pci_bridge.h"
> -#include "pci_internals.h"
> -
> -/* i21154 pci bridge*/
> -
> -typedef struct I21154Bridge {
> - PCIBridge br;
> -} I21154Bridge;
> -
> -static int i21154_bridge_initfn(PCIDevice *d)
> -{
> - int rc;
> -
> - rc = pci_bridge_initfn(d);
> - if (rc < 0) {
> - return rc;
> - }
> -
> - return 0;
> -}
> -
> -#define I21154_REV 0x05
> -#define I21154_PI 0x00
> -
> -static void i21154_bridge_class_init(ObjectClass *klass, void *data)
> -{
> - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> - k->is_bridge = 1;
> - k->vendor_id = PCI_VENDOR_ID_DEC;
> - k->device_id = PCI_DEVICE_ID_DEC_21154;
> - k->revision = I21154_REV;
> - k->init = i21154_bridge_initfn;
> -}
> -
> -static const TypeInfo i21154_bridge_info = {
> - .name = "i21154-bridge",
> - .parent = TYPE_PCI_DEVICE,
> - .instance_size = sizeof(I21154Bridge),
> - .class_init = i21154_bridge_class_init,
> -};
> -
> -PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> - bool multifunction)
> -{
> - PCIDevice *d;
> - PCIBridge *br;
> - DeviceState *qdev;
> -
> - d = pci_create_multifunction(bus, devfn, multifunction, "i21154-bridge");
> - if (!d) {
> - return NULL;
> - }
> - br = DO_UPCAST(PCIBridge, dev, d);
> - qdev = &br->dev.qdev;
> -
> - pci_bridge_map_irq(br, bus_name, pci_swizzle_map_irq_fn);
> - qdev_init_nofail(qdev);
> -
> - return br;
> -}
> -
> -static void i21154_register(void)
> -{
> - type_register_static(&i21154_bridge_info);
> -}
> -type_init(i21154_register);
> diff --git a/hw/i21154.h b/hw/i21154.h
> deleted file mode 100644
> index 0cf8753..0000000
> --- a/hw/i21154.h
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -#ifndef QEMU_I21154_H
> -#define QEMU_I21154_H
> -
> -#include "pci.h"
> -
> -PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> - bool multifunction);
> -
> -#endif /* QEMU_I21154_H */
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 03/13] blockdev: Introduce QEMUMachine->default_drive_if
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 01/13] pc/piix_pci: factor out smram/pam logic Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 02/13] Back out add of i21154 Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 19:08 ` Anthony Liguori
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 04/13] blockdev: Introduce IF_AHCI Jason Baron
` (10 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
The current QEMUMachine definition has a 'use_scsi' field to indicate if a
machine type should use scsi by default. However, Q35 wants to use ahci by
default. Thus, introdue a new field in the QEMUMachine defintion,
default_drive_if.
Please use 'static inline int get_default_drive_if(int default_drive_if)', when
accesssing the new default_drive_if field. The field should be initialized by the
machine type to the default interface type which it wants to use
(IF_SCSI, IF_AHCI, etc.). If no default_drive_if is specified, we assume IF_IDE.
In the future, we should go through all of the machines types and explicitly
define their desired default interface, thus eliminating the need for
get_default_drive_if() interface.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
blockdev.c | 4 ++--
blockdev.h | 20 ++++++++++++++++++++
hw/boards.h | 2 +-
hw/device-hotplug.c | 2 +-
hw/highbank.c | 2 +-
hw/leon3.c | 1 -
hw/mips_jazz.c | 4 ++--
hw/pc_sysfw.c | 2 +-
hw/puv3.c | 1 -
hw/realview.c | 6 +++---
hw/spapr.c | 2 +-
hw/sun4m.c | 24 ++++++++++++------------
hw/versatilepb.c | 4 ++--
hw/vexpress.c | 4 ++--
hw/xilinx_zynq.c | 2 +-
vl.c | 20 +++++++++++---------
16 files changed, 60 insertions(+), 40 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 99828ad..2977e2f 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)
return true;
}
-DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
+DriveInfo *drive_init(QemuOpts *opts, BlockInterfaceType default_drive_if)
{
const char *buf;
const char *file = NULL;
@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
return NULL;
}
} else {
- type = default_to_scsi ? IF_SCSI : IF_IDE;
+ type = get_default_drive_if(default_drive_if);
}
max_devs = if_max_devs[type];
diff --git a/blockdev.h b/blockdev.h
index 5f27b64..658380d 100644
--- a/blockdev.h
+++ b/blockdev.h
@@ -40,6 +40,26 @@ struct DriveInfo {
int refcount;
};
+/*
+ * Each qemu machine type defines a default_drive_if field for its default
+ * interface type. When accessing the default_drive_if field, please make use
+ * of get_default_drive_if(). If default_drive_if is unspecified, we set it to
+ * IF_IDE.
+ *
+ * Left as a 'todo': We should convert those that are unspecified to their
+ * proper default values, thus eliminating the need for get_default_drive_if().
+ */
+static inline int get_default_drive_if(int default_drive_if)
+{
+ assert(default_drive_if < IF_COUNT);
+ assert(default_drive_if >= IF_NONE);
+
+ if (default_drive_if == 0) {
+ return IF_IDE;
+ }
+ return default_drive_if;
+}
+
DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
int drive_get_max_bus(BlockInterfaceType type);
diff --git a/hw/boards.h b/hw/boards.h
index 813d0e5..cd3f79f 100644
--- a/hw/boards.h
+++ b/hw/boards.h
@@ -24,7 +24,7 @@ typedef struct QEMUMachine {
const char *desc;
QEMUMachineInitFunc *init;
QEMUMachineResetFunc *reset;
- int use_scsi;
+ int default_drive_if;
int max_cpus;
unsigned int no_serial:1,
no_parallel:1,
diff --git a/hw/device-hotplug.c b/hw/device-hotplug.c
index eec0fe3..53ee6c3 100644
--- a/hw/device-hotplug.c
+++ b/hw/device-hotplug.c
@@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)
if (!opts)
return NULL;
- dinfo = drive_init(opts, current_machine->use_scsi);
+ dinfo = drive_init(opts, current_machine->default_drive_if);
if (!dinfo) {
qemu_opts_del(opts);
return NULL;
diff --git a/hw/highbank.c b/hw/highbank.c
index afbb005..03ae3d8 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -326,7 +326,7 @@ static QEMUMachine highbank_machine = {
.name = "highbank",
.desc = "Calxeda Highbank (ECX-1000)",
.init = highbank_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
diff --git a/hw/leon3.c b/hw/leon3.c
index 7742738..ef83dff 100644
--- a/hw/leon3.c
+++ b/hw/leon3.c
@@ -212,7 +212,6 @@ static QEMUMachine leon3_generic_machine = {
.name = "leon3_generic",
.desc = "Leon-3 generic",
.init = leon3_generic_hw_init,
- .use_scsi = 0,
};
static void leon3_machine_init(void)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 0847427..f72358c 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -324,14 +324,14 @@ static QEMUMachine mips_magnum_machine = {
.name = "magnum",
.desc = "MIPS Magnum",
.init = mips_magnum_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine mips_pica61_machine = {
.name = "pica61",
.desc = "Acer Pica 61",
.init = mips_pica61_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static void mips_jazz_machine_init(void)
diff --git a/hw/pc_sysfw.c b/hw/pc_sysfw.c
index 9d7c5f4..b294f91 100644
--- a/hw/pc_sysfw.c
+++ b/hw/pc_sysfw.c
@@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)
return;
}
- drive_init(opts, machine->use_scsi);
+ drive_init(opts, machine->default_drive_if);
}
static void pc_system_flash_init(MemoryRegion *rom_memory,
diff --git a/hw/puv3.c b/hw/puv3.c
index 764799c..3d77349 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -122,7 +122,6 @@ static QEMUMachine puv3_machine = {
.desc = "PKUnity Version-3 based on UniCore32",
.init = puv3_init,
.is_default = 1,
- .use_scsi = 0,
};
static void puv3_machine_init(void)
diff --git a/hw/realview.c b/hw/realview.c
index b5cb08c..129c181 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -394,14 +394,14 @@ static QEMUMachine realview_eb_machine = {
.name = "realview-eb",
.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
.init = realview_eb_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine realview_eb_mpcore_machine = {
.name = "realview-eb-mpcore",
.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
.init = realview_eb_mpcore_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
@@ -415,7 +415,7 @@ static QEMUMachine realview_pbx_a9_machine = {
.name = "realview-pbx-a9",
.desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
.init = realview_pbx_a9_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
diff --git a/hw/spapr.c b/hw/spapr.c
index 8d0ad3c..ee5346b 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -924,7 +924,7 @@ static QEMUMachine spapr_machine = {
.reset = ppc_spapr_reset,
.max_cpus = MAX_CPUS,
.no_parallel = 1,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static void spapr_machine_init(void)
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 02673b2..dc2a7c1 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -1426,7 +1426,7 @@ static QEMUMachine ss5_machine = {
.name = "SS-5",
.desc = "Sun4m platform, SPARCstation 5",
.init = ss5_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.is_default = 1,
};
@@ -1434,7 +1434,7 @@ static QEMUMachine ss10_machine = {
.name = "SS-10",
.desc = "Sun4m platform, SPARCstation 10",
.init = ss10_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
@@ -1442,7 +1442,7 @@ static QEMUMachine ss600mp_machine = {
.name = "SS-600MP",
.desc = "Sun4m platform, SPARCserver 600MP",
.init = ss600mp_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
@@ -1450,7 +1450,7 @@ static QEMUMachine ss20_machine = {
.name = "SS-20",
.desc = "Sun4m platform, SPARCstation 20",
.init = ss20_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
@@ -1458,35 +1458,35 @@ static QEMUMachine voyager_machine = {
.name = "Voyager",
.desc = "Sun4m platform, SPARCstation Voyager",
.init = vger_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine ss_lx_machine = {
.name = "LX",
.desc = "Sun4m platform, SPARCstation LX",
.init = ss_lx_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine ss4_machine = {
.name = "SS-4",
.desc = "Sun4m platform, SPARCstation 4",
.init = ss4_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine scls_machine = {
.name = "SPARCClassic",
.desc = "Sun4m platform, SPARCClassic",
.init = scls_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine sbook_machine = {
.name = "SPARCbook",
.desc = "Sun4m platform, SPARCbook",
.init = sbook_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static const struct sun4d_hwdef sun4d_hwdefs[] = {
@@ -1709,7 +1709,7 @@ static QEMUMachine ss1000_machine = {
.name = "SS-1000",
.desc = "Sun4d platform, SPARCserver 1000",
.init = ss1000_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 8,
};
@@ -1717,7 +1717,7 @@ static QEMUMachine ss2000_machine = {
.name = "SS-2000",
.desc = "Sun4d platform, SPARCcenter 2000",
.init = ss2000_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 20,
};
@@ -1896,7 +1896,7 @@ static QEMUMachine ss2_machine = {
.name = "SS-2",
.desc = "Sun4c platform, SPARCstation 2",
.init = ss2_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static void sun4m_register_types(void)
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index e85f982..86c18aa 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -380,14 +380,14 @@ static QEMUMachine versatilepb_machine = {
.name = "versatilepb",
.desc = "ARM Versatile/PB (ARM926EJ-S)",
.init = vpb_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static QEMUMachine versatileab_machine = {
.name = "versatileab",
.desc = "ARM Versatile/AB (ARM926EJ-S)",
.init = vab_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
};
static void versatile_machine_init(void)
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 3f7cb66..8fb9905 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -497,7 +497,7 @@ static QEMUMachine vexpress_a9_machine = {
.name = "vexpress-a9",
.desc = "ARM Versatile Express for Cortex-A9",
.init = vexpress_a9_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
@@ -505,7 +505,7 @@ static QEMUMachine vexpress_a15_machine = {
.name = "vexpress-a15",
.desc = "ARM Versatile Express for Cortex-A15",
.init = vexpress_a15_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 4,
};
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index c55dafb..a4f2c1b 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -181,7 +181,7 @@ static QEMUMachine zynq_machine = {
.name = "xilinx-zynq-a9",
.desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
.init = zynq_init,
- .use_scsi = 1,
+ .default_drive_if = IF_SCSI,
.max_cpus = 1,
.no_sdcard = 1
};
diff --git a/vl.c b/vl.c
index 6dd767c..824d8ae 100644
--- a/vl.c
+++ b/vl.c
@@ -812,9 +812,9 @@ bool usb_enabled(bool default_usb)
static int drive_init_func(QemuOpts *opts, void *opaque)
{
- int *use_scsi = opaque;
+ int *default_drive_if = opaque;
- return drive_init(opts, *use_scsi) == NULL;
+ return drive_init(opts, *default_drive_if) == NULL;
}
static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
@@ -825,14 +825,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
return 0;
}
-static void default_drive(int enable, int snapshot, int use_scsi,
+static void default_drive(int enable, int snapshot, int default_drive_if,
BlockInterfaceType type, int index,
const char *optstr)
{
QemuOpts *opts;
if (type == IF_DEFAULT) {
- type = use_scsi ? IF_SCSI : IF_IDE;
+ type = get_default_drive_if(default_drive_if);
}
if (!enable || drive_get_by_index(type, index)) {
@@ -843,7 +843,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,
if (snapshot) {
drive_enable_snapshot(opts, NULL);
}
- if (!drive_init(opts, use_scsi)) {
+ if (!drive_init(opts, default_drive_if)) {
exit(1);
}
}
@@ -3565,14 +3565,16 @@ int main(int argc, char **argv, char **envp)
/* open the virtual block devices */
if (snapshot)
qemu_opts_foreach(qemu_find_opts("drive"), drive_enable_snapshot, NULL, 0);
- if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func, &machine->use_scsi, 1) != 0)
+ if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func,
+ &machine->default_drive_if, 1) != 0) {
exit(1);
+ }
- default_drive(default_cdrom, snapshot, machine->use_scsi,
+ default_drive(default_cdrom, snapshot, machine->default_drive_if,
IF_DEFAULT, 2, CDROM_OPTS);
- default_drive(default_floppy, snapshot, machine->use_scsi,
+ default_drive(default_floppy, snapshot, machine->default_drive_if,
IF_FLOPPY, 0, FD_OPTS);
- default_drive(default_sdcard, snapshot, machine->use_scsi,
+ default_drive(default_sdcard, snapshot, machine->default_drive_if,
IF_SD, 0, SD_OPTS);
register_savevm_live(NULL, "ram", 0, 4, &savevm_ram_handlers, NULL);
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 03/13] blockdev: Introduce QEMUMachine->default_drive_if
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 03/13] blockdev: Introduce QEMUMachine->default_drive_if Jason Baron
@ 2012-10-30 19:08 ` Anthony Liguori
0 siblings, 0 replies; 35+ messages in thread
From: Anthony Liguori @ 2012-10-30 19:08 UTC (permalink / raw)
To: Jason Baron, qemu-devel
Cc: Kevin Wolf, juzhang, mst, jan.kiszka, agraf, armbru, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
Jason Baron <jbaron@redhat.com> writes:
> From: Jason Baron <jbaron@redhat.com>
>
> The current QEMUMachine definition has a 'use_scsi' field to indicate if a
> machine type should use scsi by default. However, Q35 wants to use ahci by
> default. Thus, introdue a new field in the QEMUMachine defintion,
> default_drive_if.
>
> Please use 'static inline int get_default_drive_if(int default_drive_if)', when
> accesssing the new default_drive_if field. The field should be initialized by the
> machine type to the default interface type which it wants to use
> (IF_SCSI, IF_AHCI, etc.). If no default_drive_if is specified, we assume IF_IDE.
> In the future, we should go through all of the machines types and explicitly
> define their desired default interface, thus eliminating the need for
> get_default_drive_if() interface.
>
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
I think having a storage machine option is a bit nicer here but I'll
defer to Kevin/Markus.
Regards,
Anthony Liguori
> ---
> blockdev.c | 4 ++--
> blockdev.h | 20 ++++++++++++++++++++
> hw/boards.h | 2 +-
> hw/device-hotplug.c | 2 +-
> hw/highbank.c | 2 +-
> hw/leon3.c | 1 -
> hw/mips_jazz.c | 4 ++--
> hw/pc_sysfw.c | 2 +-
> hw/puv3.c | 1 -
> hw/realview.c | 6 +++---
> hw/spapr.c | 2 +-
> hw/sun4m.c | 24 ++++++++++++------------
> hw/versatilepb.c | 4 ++--
> hw/vexpress.c | 4 ++--
> hw/xilinx_zynq.c | 2 +-
> vl.c | 20 +++++++++++---------
> 16 files changed, 60 insertions(+), 40 deletions(-)
>
> diff --git a/blockdev.c b/blockdev.c
> index 99828ad..2977e2f 100644
> --- a/blockdev.c
> +++ b/blockdev.c
> @@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)
> return true;
> }
>
> -DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
> +DriveInfo *drive_init(QemuOpts *opts, BlockInterfaceType default_drive_if)
> {
> const char *buf;
> const char *file = NULL;
> @@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
> return NULL;
> }
> } else {
> - type = default_to_scsi ? IF_SCSI : IF_IDE;
> + type = get_default_drive_if(default_drive_if);
> }
>
> max_devs = if_max_devs[type];
> diff --git a/blockdev.h b/blockdev.h
> index 5f27b64..658380d 100644
> --- a/blockdev.h
> +++ b/blockdev.h
> @@ -40,6 +40,26 @@ struct DriveInfo {
> int refcount;
> };
>
> +/*
> + * Each qemu machine type defines a default_drive_if field for its default
> + * interface type. When accessing the default_drive_if field, please make use
> + * of get_default_drive_if(). If default_drive_if is unspecified, we set it to
> + * IF_IDE.
> + *
> + * Left as a 'todo': We should convert those that are unspecified to their
> + * proper default values, thus eliminating the need for get_default_drive_if().
> + */
> +static inline int get_default_drive_if(int default_drive_if)
> +{
> + assert(default_drive_if < IF_COUNT);
> + assert(default_drive_if >= IF_NONE);
> +
> + if (default_drive_if == 0) {
> + return IF_IDE;
> + }
> + return default_drive_if;
> +}
> +
> DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
> DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
> int drive_get_max_bus(BlockInterfaceType type);
> diff --git a/hw/boards.h b/hw/boards.h
> index 813d0e5..cd3f79f 100644
> --- a/hw/boards.h
> +++ b/hw/boards.h
> @@ -24,7 +24,7 @@ typedef struct QEMUMachine {
> const char *desc;
> QEMUMachineInitFunc *init;
> QEMUMachineResetFunc *reset;
> - int use_scsi;
> + int default_drive_if;
> int max_cpus;
> unsigned int no_serial:1,
> no_parallel:1,
> diff --git a/hw/device-hotplug.c b/hw/device-hotplug.c
> index eec0fe3..53ee6c3 100644
> --- a/hw/device-hotplug.c
> +++ b/hw/device-hotplug.c
> @@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)
> if (!opts)
> return NULL;
>
> - dinfo = drive_init(opts, current_machine->use_scsi);
> + dinfo = drive_init(opts, current_machine->default_drive_if);
> if (!dinfo) {
> qemu_opts_del(opts);
> return NULL;
> diff --git a/hw/highbank.c b/hw/highbank.c
> index afbb005..03ae3d8 100644
> --- a/hw/highbank.c
> +++ b/hw/highbank.c
> @@ -326,7 +326,7 @@ static QEMUMachine highbank_machine = {
> .name = "highbank",
> .desc = "Calxeda Highbank (ECX-1000)",
> .init = highbank_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> diff --git a/hw/leon3.c b/hw/leon3.c
> index 7742738..ef83dff 100644
> --- a/hw/leon3.c
> +++ b/hw/leon3.c
> @@ -212,7 +212,6 @@ static QEMUMachine leon3_generic_machine = {
> .name = "leon3_generic",
> .desc = "Leon-3 generic",
> .init = leon3_generic_hw_init,
> - .use_scsi = 0,
> };
>
> static void leon3_machine_init(void)
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 0847427..f72358c 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -324,14 +324,14 @@ static QEMUMachine mips_magnum_machine = {
> .name = "magnum",
> .desc = "MIPS Magnum",
> .init = mips_magnum_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine mips_pica61_machine = {
> .name = "pica61",
> .desc = "Acer Pica 61",
> .init = mips_pica61_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static void mips_jazz_machine_init(void)
> diff --git a/hw/pc_sysfw.c b/hw/pc_sysfw.c
> index 9d7c5f4..b294f91 100644
> --- a/hw/pc_sysfw.c
> +++ b/hw/pc_sysfw.c
> @@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)
> return;
> }
>
> - drive_init(opts, machine->use_scsi);
> + drive_init(opts, machine->default_drive_if);
> }
>
> static void pc_system_flash_init(MemoryRegion *rom_memory,
> diff --git a/hw/puv3.c b/hw/puv3.c
> index 764799c..3d77349 100644
> --- a/hw/puv3.c
> +++ b/hw/puv3.c
> @@ -122,7 +122,6 @@ static QEMUMachine puv3_machine = {
> .desc = "PKUnity Version-3 based on UniCore32",
> .init = puv3_init,
> .is_default = 1,
> - .use_scsi = 0,
> };
>
> static void puv3_machine_init(void)
> diff --git a/hw/realview.c b/hw/realview.c
> index b5cb08c..129c181 100644
> --- a/hw/realview.c
> +++ b/hw/realview.c
> @@ -394,14 +394,14 @@ static QEMUMachine realview_eb_machine = {
> .name = "realview-eb",
> .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
> .init = realview_eb_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine realview_eb_mpcore_machine = {
> .name = "realview-eb-mpcore",
> .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
> .init = realview_eb_mpcore_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -415,7 +415,7 @@ static QEMUMachine realview_pbx_a9_machine = {
> .name = "realview-pbx-a9",
> .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
> .init = realview_pbx_a9_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> diff --git a/hw/spapr.c b/hw/spapr.c
> index 8d0ad3c..ee5346b 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -924,7 +924,7 @@ static QEMUMachine spapr_machine = {
> .reset = ppc_spapr_reset,
> .max_cpus = MAX_CPUS,
> .no_parallel = 1,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static void spapr_machine_init(void)
> diff --git a/hw/sun4m.c b/hw/sun4m.c
> index 02673b2..dc2a7c1 100644
> --- a/hw/sun4m.c
> +++ b/hw/sun4m.c
> @@ -1426,7 +1426,7 @@ static QEMUMachine ss5_machine = {
> .name = "SS-5",
> .desc = "Sun4m platform, SPARCstation 5",
> .init = ss5_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .is_default = 1,
> };
>
> @@ -1434,7 +1434,7 @@ static QEMUMachine ss10_machine = {
> .name = "SS-10",
> .desc = "Sun4m platform, SPARCstation 10",
> .init = ss10_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -1442,7 +1442,7 @@ static QEMUMachine ss600mp_machine = {
> .name = "SS-600MP",
> .desc = "Sun4m platform, SPARCserver 600MP",
> .init = ss600mp_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -1450,7 +1450,7 @@ static QEMUMachine ss20_machine = {
> .name = "SS-20",
> .desc = "Sun4m platform, SPARCstation 20",
> .init = ss20_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -1458,35 +1458,35 @@ static QEMUMachine voyager_machine = {
> .name = "Voyager",
> .desc = "Sun4m platform, SPARCstation Voyager",
> .init = vger_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine ss_lx_machine = {
> .name = "LX",
> .desc = "Sun4m platform, SPARCstation LX",
> .init = ss_lx_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine ss4_machine = {
> .name = "SS-4",
> .desc = "Sun4m platform, SPARCstation 4",
> .init = ss4_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine scls_machine = {
> .name = "SPARCClassic",
> .desc = "Sun4m platform, SPARCClassic",
> .init = scls_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine sbook_machine = {
> .name = "SPARCbook",
> .desc = "Sun4m platform, SPARCbook",
> .init = sbook_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static const struct sun4d_hwdef sun4d_hwdefs[] = {
> @@ -1709,7 +1709,7 @@ static QEMUMachine ss1000_machine = {
> .name = "SS-1000",
> .desc = "Sun4d platform, SPARCserver 1000",
> .init = ss1000_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 8,
> };
>
> @@ -1717,7 +1717,7 @@ static QEMUMachine ss2000_machine = {
> .name = "SS-2000",
> .desc = "Sun4d platform, SPARCcenter 2000",
> .init = ss2000_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 20,
> };
>
> @@ -1896,7 +1896,7 @@ static QEMUMachine ss2_machine = {
> .name = "SS-2",
> .desc = "Sun4c platform, SPARCstation 2",
> .init = ss2_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static void sun4m_register_types(void)
> diff --git a/hw/versatilepb.c b/hw/versatilepb.c
> index e85f982..86c18aa 100644
> --- a/hw/versatilepb.c
> +++ b/hw/versatilepb.c
> @@ -380,14 +380,14 @@ static QEMUMachine versatilepb_machine = {
> .name = "versatilepb",
> .desc = "ARM Versatile/PB (ARM926EJ-S)",
> .init = vpb_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static QEMUMachine versatileab_machine = {
> .name = "versatileab",
> .desc = "ARM Versatile/AB (ARM926EJ-S)",
> .init = vab_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> };
>
> static void versatile_machine_init(void)
> diff --git a/hw/vexpress.c b/hw/vexpress.c
> index 3f7cb66..8fb9905 100644
> --- a/hw/vexpress.c
> +++ b/hw/vexpress.c
> @@ -497,7 +497,7 @@ static QEMUMachine vexpress_a9_machine = {
> .name = "vexpress-a9",
> .desc = "ARM Versatile Express for Cortex-A9",
> .init = vexpress_a9_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -505,7 +505,7 @@ static QEMUMachine vexpress_a15_machine = {
> .name = "vexpress-a15",
> .desc = "ARM Versatile Express for Cortex-A15",
> .init = vexpress_a15_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
> index c55dafb..a4f2c1b 100644
> --- a/hw/xilinx_zynq.c
> +++ b/hw/xilinx_zynq.c
> @@ -181,7 +181,7 @@ static QEMUMachine zynq_machine = {
> .name = "xilinx-zynq-a9",
> .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
> .init = zynq_init,
> - .use_scsi = 1,
> + .default_drive_if = IF_SCSI,
> .max_cpus = 1,
> .no_sdcard = 1
> };
> diff --git a/vl.c b/vl.c
> index 6dd767c..824d8ae 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -812,9 +812,9 @@ bool usb_enabled(bool default_usb)
>
> static int drive_init_func(QemuOpts *opts, void *opaque)
> {
> - int *use_scsi = opaque;
> + int *default_drive_if = opaque;
>
> - return drive_init(opts, *use_scsi) == NULL;
> + return drive_init(opts, *default_drive_if) == NULL;
> }
>
> static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
> @@ -825,14 +825,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
> return 0;
> }
>
> -static void default_drive(int enable, int snapshot, int use_scsi,
> +static void default_drive(int enable, int snapshot, int default_drive_if,
> BlockInterfaceType type, int index,
> const char *optstr)
> {
> QemuOpts *opts;
>
> if (type == IF_DEFAULT) {
> - type = use_scsi ? IF_SCSI : IF_IDE;
> + type = get_default_drive_if(default_drive_if);
> }
>
> if (!enable || drive_get_by_index(type, index)) {
> @@ -843,7 +843,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,
> if (snapshot) {
> drive_enable_snapshot(opts, NULL);
> }
> - if (!drive_init(opts, use_scsi)) {
> + if (!drive_init(opts, default_drive_if)) {
> exit(1);
> }
> }
> @@ -3565,14 +3565,16 @@ int main(int argc, char **argv, char **envp)
> /* open the virtual block devices */
> if (snapshot)
> qemu_opts_foreach(qemu_find_opts("drive"), drive_enable_snapshot, NULL, 0);
> - if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func, &machine->use_scsi, 1) != 0)
> + if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func,
> + &machine->default_drive_if, 1) != 0) {
> exit(1);
> + }
>
> - default_drive(default_cdrom, snapshot, machine->use_scsi,
> + default_drive(default_cdrom, snapshot, machine->default_drive_if,
> IF_DEFAULT, 2, CDROM_OPTS);
> - default_drive(default_floppy, snapshot, machine->use_scsi,
> + default_drive(default_floppy, snapshot, machine->default_drive_if,
> IF_FLOPPY, 0, FD_OPTS);
> - default_drive(default_sdcard, snapshot, machine->use_scsi,
> + default_drive(default_sdcard, snapshot, machine->default_drive_if,
> IF_SD, 0, SD_OPTS);
>
> register_savevm_live(NULL, "ram", 0, 4, &savevm_ram_handlers, NULL);
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 04/13] blockdev: Introduce IF_AHCI
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (2 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 03/13] blockdev: Introduce QEMUMachine->default_drive_if Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization Jason Baron
` (9 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to
differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is important, since we don't want
to have the meaning of if=ide changing once q35 is introduced. Thus, its
important for this to be applied before we introduce q35.
This patch also adds:
1)
void ahci_drive_get(DriveInfo **hd, int bus, int nports);
To populate hd with with the drives on bus 'bus', with up to 'nports'.
2)
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table, int
table_size);
Which provides a convient way of attaching ahci drives to an
ahci controller.
3)
drive_get_max_unit(BlockInterfaceType type);
Allows q35 to error if too many units are specified.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
blockdev.c | 19 ++++++++++++++++++-
blockdev.h | 2 ++
hw/ide.h | 1 +
hw/ide/core.c | 9 +++++++++
hw/ide/pci.c | 19 +++++++++++++++++++
hw/ide/pci.h | 1 +
6 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 2977e2f..e37d93d 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = {
[IF_SD] = "sd",
[IF_VIRTIO] = "virtio",
[IF_XEN] = "xen",
+ [IF_AHCI] = "ahci",
};
static const int if_max_devs[IF_COUNT] = {
@@ -158,6 +159,21 @@ int drive_get_max_bus(BlockInterfaceType type)
return max_bus;
}
+int drive_get_max_unit(BlockInterfaceType type)
+{
+ int max_unit;
+ DriveInfo *dinfo;
+
+ max_unit = -1;
+ QTAILQ_FOREACH(dinfo, &drives, next) {
+ if (dinfo->type == type &&
+ dinfo->unit > max_unit) {
+ max_unit = dinfo->unit;
+ }
+ }
+ return max_unit;
+}
+
/* Get a block device. This should only be used for single-drive devices
(e.g. SD/Floppy/MTD). Multi-disk devices (scsi/ide) should use the
appropriate bus. */
@@ -518,7 +534,7 @@ DriveInfo *drive_init(QemuOpts *opts, BlockInterfaceType default_drive_if)
} else {
/* no id supplied -> create one */
dinfo->id = g_malloc0(32);
- if (type == IF_IDE || type == IF_SCSI)
+ if (type == IF_IDE || type == IF_SCSI || type == IF_AHCI)
mediastr = (media == MEDIA_CDROM) ? "-cd" : "-hd";
if (max_devs)
snprintf(dinfo->id, 32, "%s%i%s%i",
@@ -550,6 +566,7 @@ DriveInfo *drive_init(QemuOpts *opts, BlockInterfaceType default_drive_if)
switch(type) {
case IF_IDE:
+ case IF_AHCI:
case IF_SCSI:
case IF_XEN:
case IF_NONE:
diff --git a/blockdev.h b/blockdev.h
index 658380d..0c7985d 100644
--- a/blockdev.h
+++ b/blockdev.h
@@ -21,6 +21,7 @@ typedef enum {
IF_DEFAULT = -1, /* for use with drive_add() only */
IF_NONE,
IF_IDE, IF_SCSI, IF_FLOPPY, IF_PFLASH, IF_MTD, IF_SD, IF_VIRTIO, IF_XEN,
+ IF_AHCI,
IF_COUNT
} BlockInterfaceType;
@@ -63,6 +64,7 @@ static inline int get_default_drive_if(int default_drive_if)
DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
int drive_get_max_bus(BlockInterfaceType type);
+int drive_get_max_unit(BlockInterfaceType type);
DriveInfo *drive_get_next(BlockInterfaceType type);
void drive_get_ref(DriveInfo *dinfo);
void drive_put_ref(DriveInfo *dinfo);
diff --git a/hw/ide.h b/hw/ide.h
index add742c..6c43a57 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -35,5 +35,6 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
/* ide/core.c */
void ide_drive_get(DriveInfo **hd, int max_bus);
+void ahci_drive_get(DriveInfo **hd, int bus, int nports);
#endif /* HW_IDE_H */
diff --git a/hw/ide/core.c b/hw/ide/core.c
index d683a8c..4a56517 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2354,3 +2354,12 @@ void ide_drive_get(DriveInfo **hd, int max_bus)
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
}
}
+
+void ahci_drive_get(DriveInfo **hd, int bus, int nports)
+{
+ int i;
+
+ for (i = 0; i < nports; i++) {
+ hd[i] = drive_get(IF_AHCI, bus, i);
+ }
+}
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index bcdd70e..9218989 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -28,8 +28,10 @@
#include <hw/isa.h>
#include "block.h"
#include "dma.h"
+#include "blockdev.h"
#include <hw/ide/pci.h>
+#include <hw/ide/ahci.h>
#define BMDMA_PAGE_SIZE 4096
@@ -504,6 +506,23 @@ void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
}
}
+void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table, int table_size)
+{
+ struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
+ int i;
+ DriveInfo *drive;
+
+ for (i = 0; i < table_size; i++) {
+ if (hd_table[i] == NULL) {
+ continue;
+ }
+ drive = hd_table[i];
+ assert(drive->type == IF_AHCI);
+ ide_create_drive(&dev->ahci.dev[i].port, 0,
+ hd_table[i]);
+ }
+}
+
static const struct IDEDMAOps bmdma_ops = {
.start_dma = bmdma_start_dma,
.start_transfer = bmdma_start_transfer,
diff --git a/hw/ide/pci.h b/hw/ide/pci.h
index a694e54..aa23f44 100644
--- a/hw/ide/pci.h
+++ b/hw/ide/pci.h
@@ -58,6 +58,7 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
extern MemoryRegionOps bmdma_addr_ioport_ops;
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table);
+void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table, int table_size);
extern const VMStateDescription vmstate_ide_pci;
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (3 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 04/13] blockdev: Introduce IF_AHCI Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 19:09 ` Anthony Liguori
2012-10-31 9:57 ` Michael S. Tsirkin
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 06/13] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
` (8 subsequent siblings)
13 siblings, 2 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 15 +++++++++++++++
hw/pc.h | 1 +
hw/pc_piix.c | 9 +--------
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index a02b397..cb7fa68 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1104,6 +1104,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
*floppy = fdctrl_init_isa(isa_bus, fd);
}
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
+{
+ int i;
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
+ pc_init_ne2k_isa(isa_bus, nd);
+ } else {
+ pci_nic_init_nofail(nd, "e1000", NULL);
+ }
+ }
+}
+
void pc_pci_device_init(PCIBus *pci_bus)
{
int max_bus;
diff --git a/hw/pc.h b/hw/pc.h
index e7993ca..d6639a6 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -98,6 +98,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device,
ISADevice *floppy, BusState *ide0, BusState *ide1,
ISADevice *s);
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 85529b2..acb1e92 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -234,14 +234,7 @@ static void pc_init1(MemoryRegion *system_memory,
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
- for(i = 0; i < nb_nics; i++) {
- NICInfo *nd = &nd_table[i];
-
- if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
- pc_init_ne2k_isa(isa_bus, nd);
- else
- pci_nic_init_nofail(nd, "e1000", NULL);
- }
+ pc_nic_init(isa_bus, pci_bus);
ide_drive_get(hd, MAX_IDE_BUS);
if (pci_enabled) {
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization Jason Baron
@ 2012-10-30 19:09 ` Anthony Liguori
2012-10-31 9:57 ` Michael S. Tsirkin
1 sibling, 0 replies; 35+ messages in thread
From: Anthony Liguori @ 2012-10-30 19:09 UTC (permalink / raw)
To: Jason Baron, qemu-devel
Cc: juzhang, mst, jan.kiszka, agraf, armbru, blauwirbel, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, kraxel
Jason Baron <jbaron@redhat.com> writes:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Factor out pc nic initialization.
> This simplifies the pc initialization and will reduce the code
> duplication of q35 pc initialization.
>
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Regards,
Anthony Liguori
> ---
> hw/pc.c | 15 +++++++++++++++
> hw/pc.h | 1 +
> hw/pc_piix.c | 9 +--------
> 3 files changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index a02b397..cb7fa68 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1104,6 +1104,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
> *floppy = fdctrl_init_isa(isa_bus, fd);
> }
>
> +void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
> +{
> + int i;
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> +
> + if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
> + pc_init_ne2k_isa(isa_bus, nd);
> + } else {
> + pci_nic_init_nofail(nd, "e1000", NULL);
> + }
> + }
> +}
> +
> void pc_pci_device_init(PCIBus *pci_bus)
> {
> int max_bus;
> diff --git a/hw/pc.h b/hw/pc.h
> index e7993ca..d6639a6 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -98,6 +98,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
> const char *boot_device,
> ISADevice *floppy, BusState *ide0, BusState *ide1,
> ISADevice *s);
> +void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
> void pc_pci_device_init(PCIBus *pci_bus);
>
> typedef void (*cpu_set_smm_t)(int smm, void *arg);
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index 85529b2..acb1e92 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -234,14 +234,7 @@ static void pc_init1(MemoryRegion *system_memory,
> /* init basic PC hardware */
> pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
>
> - for(i = 0; i < nb_nics; i++) {
> - NICInfo *nd = &nd_table[i];
> -
> - if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
> - pc_init_ne2k_isa(isa_bus, nd);
> - else
> - pci_nic_init_nofail(nd, "e1000", NULL);
> - }
> + pc_nic_init(isa_bus, pci_bus);
>
> ide_drive_get(hd, MAX_IDE_BUS);
> if (pci_enabled) {
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization Jason Baron
2012-10-30 19:09 ` Anthony Liguori
@ 2012-10-31 9:57 ` Michael S. Tsirkin
1 sibling, 0 replies; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 9:57 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 29, 2012 at 10:11:26PM -0400, Jason Baron wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Factor out pc nic initialization.
> This simplifies the pc initialization and will reduce the code
> duplication of q35 pc initialization.
>
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Thanks, applied.
> ---
> hw/pc.c | 15 +++++++++++++++
> hw/pc.h | 1 +
> hw/pc_piix.c | 9 +--------
> 3 files changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index a02b397..cb7fa68 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1104,6 +1104,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
> *floppy = fdctrl_init_isa(isa_bus, fd);
> }
>
> +void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
> +{
> + int i;
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> +
> + if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
> + pc_init_ne2k_isa(isa_bus, nd);
> + } else {
> + pci_nic_init_nofail(nd, "e1000", NULL);
> + }
> + }
> +}
> +
> void pc_pci_device_init(PCIBus *pci_bus)
> {
> int max_bus;
> diff --git a/hw/pc.h b/hw/pc.h
> index e7993ca..d6639a6 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -98,6 +98,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
> const char *boot_device,
> ISADevice *floppy, BusState *ide0, BusState *ide1,
> ISADevice *s);
> +void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
> void pc_pci_device_init(PCIBus *pci_bus);
>
> typedef void (*cpu_set_smm_t)(int smm, void *arg);
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index 85529b2..acb1e92 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -234,14 +234,7 @@ static void pc_init1(MemoryRegion *system_memory,
> /* init basic PC hardware */
> pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
>
> - for(i = 0; i < nb_nics; i++) {
> - NICInfo *nd = &nd_table[i];
> -
> - if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
> - pc_init_ne2k_isa(isa_bus, nd);
> - else
> - pci_nic_init_nofail(nd, "e1000", NULL);
> - }
> + pc_nic_init(isa_bus, pci_bus);
>
> ide_drive_get(hd, MAX_IDE_BUS);
> if (pci_enabled) {
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 06/13] pc: Move ioapic_init() from pc_piix.c to pc.c
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (4 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 05/13] pc, pc_piix: split out pc nic initialization Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-31 10:02 ` Michael S. Tsirkin
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator Jason Baron
` (7 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 24 ++++++++++++++++++++++++
hw/pc.h | 2 ++
hw/pc_piix.c | 25 +------------------------
3 files changed, 27 insertions(+), 24 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index cb7fa68..af1a076 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1129,3 +1129,27 @@ void pc_pci_device_init(PCIBus *pci_bus)
pci_create_simple(pci_bus, -1, "lsi53c895a");
}
}
+
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
+{
+ DeviceState *dev;
+ SysBusDevice *d;
+ unsigned int i;
+
+ if (kvm_irqchip_in_kernel()) {
+ dev = qdev_create(NULL, "kvm-ioapic");
+ } else {
+ dev = qdev_create(NULL, "ioapic");
+ }
+ if (parent_name) {
+ object_property_add_child(object_resolve_path(parent_name, NULL),
+ "ioapic", OBJECT(dev), NULL);
+ }
+ qdev_init_nofail(dev);
+ d = sysbus_from_qdev(dev);
+ sysbus_mmio_map(d, 0, 0xfec00000);
+
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+ gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
+ }
+}
diff --git a/hw/pc.h b/hw/pc.h
index d6639a6..2237e86 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -104,6 +104,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
+
/* acpi.c */
extern int acpi_enabled;
extern char *acpi_tables;
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index acb1e92..7bcac87 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -95,29 +95,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
}
}
-static void ioapic_init(GSIState *gsi_state)
-{
- DeviceState *dev;
- SysBusDevice *d;
- unsigned int i;
-
- if (kvm_irqchip_in_kernel()) {
- dev = qdev_create(NULL, "kvm-ioapic");
- } else {
- dev = qdev_create(NULL, "ioapic");
- }
- /* FIXME: this should be under the piix3. */
- object_property_add_child(object_resolve_path("i440fx", NULL),
- "ioapic", OBJECT(dev), NULL);
- qdev_init_nofail(dev);
- d = sysbus_from_qdev(dev);
- sysbus_mmio_map(d, 0, 0xfec00000);
-
- for (i = 0; i < IOAPIC_NUM_PINS; i++) {
- gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
- }
-}
-
/* PC hardware initialisation */
static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *system_io,
@@ -221,7 +198,7 @@ static void pc_init1(MemoryRegion *system_memory,
gsi_state->i8259_irq[i] = i8259[i];
}
if (pci_enabled) {
- ioapic_init(gsi_state);
+ ioapic_init_gsi(gsi_state, "i440fx");
}
pc_register_ferr_irq(gsi[13]);
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 06/13] pc: Move ioapic_init() from pc_piix.c to pc.c
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 06/13] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
@ 2012-10-31 10:02 ` Michael S. Tsirkin
0 siblings, 0 replies; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 10:02 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 29, 2012 at 10:11:26PM -0400, Jason Baron wrote:
> From: Jason Baron <jbaron@redhat.com>
>
> Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
> Rename ioapic_init -> ioapic_init_gsi.
>
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
I wonder whether this should be reworked using composition too?
> ---
> hw/pc.c | 24 ++++++++++++++++++++++++
> hw/pc.h | 2 ++
> hw/pc_piix.c | 25 +------------------------
> 3 files changed, 27 insertions(+), 24 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index cb7fa68..af1a076 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1129,3 +1129,27 @@ void pc_pci_device_init(PCIBus *pci_bus)
> pci_create_simple(pci_bus, -1, "lsi53c895a");
> }
> }
> +
> +void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
> +{
> + DeviceState *dev;
> + SysBusDevice *d;
> + unsigned int i;
> +
> + if (kvm_irqchip_in_kernel()) {
> + dev = qdev_create(NULL, "kvm-ioapic");
> + } else {
> + dev = qdev_create(NULL, "ioapic");
> + }
> + if (parent_name) {
> + object_property_add_child(object_resolve_path(parent_name, NULL),
> + "ioapic", OBJECT(dev), NULL);
> + }
> + qdev_init_nofail(dev);
> + d = sysbus_from_qdev(dev);
> + sysbus_mmio_map(d, 0, 0xfec00000);
> +
> + for (i = 0; i < IOAPIC_NUM_PINS; i++) {
> + gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> + }
> +}
> diff --git a/hw/pc.h b/hw/pc.h
> index d6639a6..2237e86 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -104,6 +104,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
> typedef void (*cpu_set_smm_t)(int smm, void *arg);
> void cpu_smm_register(cpu_set_smm_t callback, void *arg);
>
> +void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
> +
> /* acpi.c */
> extern int acpi_enabled;
> extern char *acpi_tables;
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index acb1e92..7bcac87 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -95,29 +95,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
> }
> }
>
> -static void ioapic_init(GSIState *gsi_state)
> -{
> - DeviceState *dev;
> - SysBusDevice *d;
> - unsigned int i;
> -
> - if (kvm_irqchip_in_kernel()) {
> - dev = qdev_create(NULL, "kvm-ioapic");
> - } else {
> - dev = qdev_create(NULL, "ioapic");
> - }
> - /* FIXME: this should be under the piix3. */
> - object_property_add_child(object_resolve_path("i440fx", NULL),
> - "ioapic", OBJECT(dev), NULL);
> - qdev_init_nofail(dev);
> - d = sysbus_from_qdev(dev);
> - sysbus_mmio_map(d, 0, 0xfec00000);
> -
> - for (i = 0; i < IOAPIC_NUM_PINS; i++) {
> - gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> - }
> -}
> -
> /* PC hardware initialisation */
> static void pc_init1(MemoryRegion *system_memory,
> MemoryRegion *system_io,
> @@ -221,7 +198,7 @@ static void pc_init1(MemoryRegion *system_memory,
> gsi_state->i8259_irq[i] = i8259[i];
> }
> if (pci_enabled) {
> - ioapic_init(gsi_state);
> + ioapic_init_gsi(gsi_state, "i440fx");
> }
>
> pc_register_ferr_irq(gsi[13]);
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (5 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 06/13] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 19:18 ` Anthony Liguori
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 08/13] q35: Suppress SMM BIOS initialization under KVM Jason Baron
` (6 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
pc q35 based chipset emulator to support pci express natively. Based on
Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias
of 'q35'. At this point, there are no compatibility guarantees. When the
chipset stabilizes more, we will begin to version the machine names.
Major features which still need to be added:
-Migration support (mostly around ahci)
-ACPI hotplug support (pcie hotplug support is working)
-Passthrough support
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/i386/Makefile.objs | 2 +-
hw/pc.h | 2 +
hw/pc_piix.c | 4 +-
hw/pc_q35.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/pci_ids.h | 2 +
hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++
hw/q35.h | 161 ++++++++++++++++++++++++
7 files changed, 809 insertions(+), 3 deletions(-)
create mode 100644 hw/pc_q35.c
create mode 100644 hw/q35.c
create mode 100644 hw/q35.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 693bd18..469b127 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o
obj-y += pc_piix.o
obj-y += pc_sysfw.o
obj-y += pam.o
-obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
+obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o
obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
diff --git a/hw/pc.h b/hw/pc.h
index 2237e86..e1bf2fc 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -42,6 +42,8 @@ int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon);
void irq_info(Monitor *mon);
+void kvm_piix3_gsi_handler(void *opaque, int n, int level);
+void kvm_piix3_setup_irq_routing(bool pci_enabled);
/* Global System Interrupts */
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 7bcac87..26565a1 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -54,7 +54,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
-static void kvm_piix3_setup_irq_routing(bool pci_enabled)
+void kvm_piix3_setup_irq_routing(bool pci_enabled)
{
#ifdef CONFIG_KVM
KVMState *s = kvm_state;
@@ -83,7 +83,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)
#endif /* CONFIG_KVM */
}
-static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
+void kvm_piix3_gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
new file mode 100644
index 0000000..cf0d361
--- /dev/null
+++ b/hw/pc_q35.c
@@ -0,0 +1,326 @@
+/*
+ * Q35 chipset based pc system emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ * Copyright (c) 2009, 2010
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * This is based on pc.c, but heavily modified.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "arch_init.h"
+#include "pc.h"
+#include "fdc.h"
+#include "pci.h"
+#include "pci_bridge.h"
+#include "ioh3420.h"
+#include "xio3130_upstream.h"
+#include "xio3130_downstream.h"
+#include "block.h"
+#include "blockdev.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
+#include "monitor.h"
+#include "fw_cfg.h"
+#include "hpet_emul.h"
+#include "watchdog.h"
+#include "smbios.h"
+#include "ide.h"
+#include "mc146818rtc.h"
+#include "xen.h"
+#include "kvm.h"
+
+#include "q35.h"
+#include "exec-memory.h"
+#include "ich9.h"
+#include <hw/ide/pci.h>
+#include <hw/ide/ahci.h>
+
+/* ICH9 AHCI has 6 ports */
+#define MAX_SATA_PORTS 6
+
+static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state,
+ DeviceState **gmch_host_p,
+ PCIBus **host_bus_p,
+ PCIDevice **lpc_p, ISABus **isa_bus,
+ MemoryRegion *system_memory,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io,
+ MemoryRegion *ram_memory,
+ ram_addr_t below_4g_mem_size,
+ ram_addr_t above_4g_mem_size)
+{
+ int i;
+ hwaddr pci_hole64_size;
+ DeviceState *gmch_host;
+ PCIBus *host_bus;
+
+ PCIDevice *gmch_state;
+ PCIDevice *lpc;
+ GMCHPCIState *gmps;
+ ICH9LPCState *ich9_lpc;
+
+ /* create pci host bus */
+ host_bus = gmch_host_init(&gmch_host, pci_address_space, address_space_io);
+ gmch_state = gmch_init(gmch_host, host_bus);
+ gmps = GMCH_PCI_DEVICE(gmch_state);
+
+ /* create ISA bus */
+ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
+ ICH9_LPC_FUNC), true,
+ TYPE_ICH9_LPC_DEVICE);
+ ich9_lpc = ICH9_LPC_DEVICE(lpc);
+ ich9_lpc->pic = gsi;
+ ich9_lpc->ioapic = gsi_state->ioapic_irq;
+ pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
+ ICH9_LPC_NB_PIRQS);
+
+ gmps->ram_memory = ram_memory;
+ gmps->pci_address_space = pci_address_space;
+ gmps->system_memory = system_memory;
+ /* pci */
+ memory_region_init_alias(&gmps->pci_hole, "pci-hole",
+ gmps->pci_address_space,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size);
+ memory_region_add_subregion(gmps->system_memory, below_4g_mem_size,
+ &gmps->pci_hole);
+ pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
+ ((uint64_t)1 << 62));
+ memory_region_init_alias(&gmps->pci_hole_64bit, "pci-hole64",
+ gmps->pci_address_space,
+ 0x100000000ULL + above_4g_mem_size,
+ pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(gmps->system_memory,
+ 0x100000000ULL + above_4g_mem_size,
+ &gmps->pci_hole_64bit);
+ }
+
+ /* smram */
+ memory_region_init_alias(&gmps->smram_region, "smram-region",
+ pci_address_space, 0xa0000, 0x20000);
+ memory_region_add_subregion_overlap(system_memory, 0xa0000,
+ &gmps->smram_region, 1);
+ memory_region_set_enabled(&gmps->smram_region, false);
+ init_pam(gmps->ram_memory, gmps->system_memory, gmps->pci_address_space,
+ &gmps->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ for (i = 0; i < 12; ++i) {
+ init_pam(gmps->ram_memory, gmps->system_memory, gmps->pci_address_space,
+ &gmps->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
+ PAM_EXPAN_SIZE);
+ }
+
+ *gmch_host_p = gmch_host;
+ *host_bus_p = host_bus;
+ *lpc_p = lpc;
+ *isa_bus = ich9_lpc->isa_bus;
+}
+
+
+/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
+ * BIOS will read it and start S3 resume at POST Entry */
+static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
+{
+ ISADevice *s = opaque;
+
+ if (level) {
+ rtc_set_memory(s, 0xF, 0xFE);
+ }
+}
+
+static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
+ DeviceState *gmch_host, PCIBus *host_bus,
+ PCIDevice *lpc)
+{
+ qemu_irq *cmos_s3;
+ PCIDevice *ahci;
+ DriveInfo **hd;
+ struct AHCIPCIState *ahci_state;
+ int ports, max_unit, max_bus;
+
+ /* connect pm stuff to lpc */
+ cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
+ ich9_lpc_pm_init(lpc, *cmos_s3);
+
+ /* ahci and SATA device, for q35 1 ahci controller is built-in */
+ ahci = pci_create_simple_multifunction(host_bus,
+ PCI_DEVFN(ICH9_SATA1_DEV,
+ ICH9_SATA1_FUNC),
+ true, "ich9-ahci");
+ ahci_state = DO_UPCAST(struct AHCIPCIState, card, ahci);
+ ports = ahci_state->ahci.ports;
+ max_unit = drive_get_max_unit(IF_AHCI);
+ if (max_unit >= ports) {
+ fprintf(stderr, "%d ports are available on the host ahci controller.\n"
+ "Ignoring extra assignments.\n", ports);
+ }
+ max_bus = drive_get_max_bus(IF_AHCI);
+ if (max_bus > 0) {
+ fprintf(stderr, "1 bus is available on the host ahci controller.\n"
+ "Ignoring extra assignments.\n");
+ }
+ hd = g_malloc(ports * sizeof(DriveInfo *));
+ ahci_drive_get(hd, 0, ports);
+ pci_ahci_create_devs(ahci, hd, ports);
+ idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
+ idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
+
+ if (usb_enabled(false)) {
+ /* Should we create 6 UHCI according to ich9 spec? */
+ pci_create_simple_multifunction(
+ host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
+ true, "ich9-usb-uhci1");
+ /* XXX: EHCI */
+ }
+
+ /* TODO: Populate SPD eeprom data. */
+ smbus_eeprom_init(ich9_smb_init(host_bus,
+ PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
+ 0xb100),
+ 8, NULL, 0);
+}
+
+/* PC hardware initialisation */
+static void pc_q35_init(QEMUMachineInitArgs *args)
+{
+ ram_addr_t ram_size = args->ram_size;
+ const char *cpu_model = args->cpu_model;
+ const char *kernel_filename = args->kernel_filename;
+ const char *kernel_cmdline = args->kernel_cmdline;
+ const char *initrd_filename = args->initrd_filename;
+ const char *boot_device = args->boot_device;
+ ram_addr_t below_4g_mem_size, above_4g_mem_size;
+ DeviceState *gmch_host;
+ PCIBus *host_bus;
+ PCIDevice *lpc;
+ BusState *idebus[MAX_SATA_PORTS];
+ ISADevice *rtc_state;
+ ISADevice *floppy;
+ MemoryRegion *pci_memory;
+ MemoryRegion *rom_memory;
+ MemoryRegion *ram_memory;
+ GSIState *gsi_state;
+ ISABus *isa_bus;
+ int pci_enabled = 1;
+ qemu_irq *cpu_irq;
+ qemu_irq *gsi;
+ qemu_irq *i8259;
+ int i;
+
+ pc_cpus_init(cpu_model);
+
+ if (ram_size >= 0xb0000000) {
+ above_4g_mem_size = ram_size - 0xb0000000;
+ below_4g_mem_size = 0xb0000000;
+ } else {
+ above_4g_mem_size = 0;
+ below_4g_mem_size = ram_size;
+ }
+
+ /* pci enabled */
+ if (pci_enabled) {
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+ rom_memory = pci_memory;
+ } else {
+ pci_memory = NULL;
+ rom_memory = get_system_memory();
+ }
+
+ /* allocate ram and load rom/bios */
+ if (!xen_enabled()) {
+ pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
+ initrd_filename, below_4g_mem_size, above_4g_mem_size,
+ rom_memory, &ram_memory);
+ }
+
+ /* irq lines */
+ gsi_state = g_malloc0(sizeof(*gsi_state));
+ if (kvm_irqchip_in_kernel()) {
+ kvm_piix3_setup_irq_routing(pci_enabled);
+ gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
+ GSI_NUM_PINS);
+ } else {
+ gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ }
+
+ pc_q35_init_early(gsi, gsi_state,
+ &gmch_host, &host_bus, &lpc, &isa_bus,
+ get_system_memory(), pci_memory, get_system_io(),
+ ram_memory, below_4g_mem_size, above_4g_mem_size);
+ isa_bus_irqs(isa_bus, gsi);
+
+ if (kvm_irqchip_in_kernel()) {
+ i8259 = kvm_i8259_init(isa_bus);
+ } else if (xen_enabled()) {
+ i8259 = xen_interrupt_controller_init();
+ } else {
+ cpu_irq = pc_allocate_cpu_irq();
+ i8259 = i8259_init(isa_bus, cpu_irq[0]);
+ }
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ gsi_state->i8259_irq[i] = i8259[i];
+ }
+ if (pci_enabled) {
+ ioapic_init_gsi(gsi_state, NULL);
+ }
+
+ pc_register_ferr_irq(gsi[13]);
+
+ /* init basic PC hardware */
+ pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
+
+ pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, lpc);
+
+ pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
+ floppy, idebus[0], idebus[1], rtc_state);
+
+ /* the rest devices to which pci devfn is automatically assigned */
+ pc_vga_init(isa_bus, host_bus);
+ audio_init(isa_bus, host_bus);
+ pc_nic_init(isa_bus, host_bus);
+ if (pci_enabled) {
+ pc_pci_device_init(host_bus);
+ }
+}
+
+static QEMUMachine pc_q35_machine = {
+ .name = "q35-next",
+ .alias = "q35",
+ .desc = "Q35 chipset PC",
+ .init = pc_q35_init,
+ .max_cpus = 255,
+ .default_drive_if = IF_AHCI,
+};
+
+static void pc_q35_machine_init(void)
+{
+ qemu_register_machine(&pc_q35_machine);
+}
+
+machine_init(pc_q35_machine_init);
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 17ae42e..ef24181 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -137,6 +137,8 @@
#define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c
#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
+
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
diff --git a/hw/q35.c b/hw/q35.c
new file mode 100644
index 0000000..1fd8802
--- /dev/null
+++ b/hw/q35.c
@@ -0,0 +1,315 @@
+/*
+ * QEMU GMCH/ICH9 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2009, 2010, 2011
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * This is based on piix_pci.c, but heavily modified.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+#include "pci_internals.h"
+#include "exec-memory.h"
+#include "isa.h"
+#include "qemu-common.h"
+#include "ich9.h"
+
+
+
+/****************************************************************************
+ * GMCH PCI host
+ */
+
+static int gmch_pcihost_initfn(SysBusDevice *dev)
+{
+ PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(&dev->qdev);
+
+ memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
+ "pci-conf-idx", 4);
+ sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
+ sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_ADDR, 4);
+
+ memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
+ "pci-conf-data", 4);
+ sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
+ sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_DATA, 4);
+
+ if (pcie_host_init(&s->host) < 0) {
+ abort();
+ }
+
+ return 0;
+}
+
+static Property gmch_props[] = {
+ DEFINE_PROP_UINT64("MCFG", GMCHPCIHost, host.base_addr,
+ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void gmch_pcihost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = gmch_pcihost_initfn;
+ dc->props = gmch_props;
+ dc->no_user = 1;
+}
+
+static const TypeInfo gmch_pcihost_info = {
+ .name = TYPE_GMCH_HOST_DEVICE,
+ .parent = TYPE_PCIE_HOST_BRIDGE,
+ .instance_size = sizeof(GMCHPCIHost),
+ .class_init = gmch_pcihost_class_init,
+};
+
+/* host bridge */
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io)
+{
+ DeviceState *dev;
+ GMCHPCIHost *s;
+ PCIBus *b;
+
+ dev = qdev_create(NULL, TYPE_GMCH_HOST_DEVICE);
+ s = GMCH_HOST_DEVICE(dev);
+ b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", pci_address_space,
+ address_space_io, 0);
+ s->host.pci.bus = b;
+ qdev_init_nofail(dev);
+ *gmch_hostp = dev;
+ return b;
+}
+
+
+/****************************************************************************
+ * GMCH D0:F0
+ */
+
+/* PCIE MMCFG */
+static void gmch_update_pciexbar(GMCHPCIState *gs)
+{
+ PCIDevice *pci_dev = &gs->d;
+ BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+ DeviceState *qdev = bus->parent;
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(qdev);
+
+ uint64_t pciexbar;
+ int enable;
+ uint64_t addr;
+ uint64_t addr_mask;
+ uint32_t length;
+
+ pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
+ enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
+
+ addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
+ switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
+ length = 256 * 1024 * 1024;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
+ length = 128 * 1024 * 1024;
+ addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
+ GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
+ length = 64 * 1024 * 1024;
+ addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
+ default:
+ enable = 0;
+ length = 0;
+ abort();
+ break;
+ }
+ addr = pciexbar & addr_mask;
+
+ pcie_host_mmcfg_update(&s->host, enable, addr, length);
+}
+
+/* PAM */
+static void gmch_update_pam(GMCHPCIState *gs)
+{
+ int i;
+
+ memory_region_transaction_begin();
+ for (i = 0; i < 13; i++) {
+ pam_update(&gs->pam_regions[i], i,
+ gs->d.config[GMCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
+ }
+ memory_region_transaction_commit();
+}
+
+/* SMRAM */
+static void gmch_update_smram(GMCHPCIState *gs)
+{
+ memory_region_transaction_begin();
+ smram_update(&gs->smram_region, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+ gs->smm_enabled);
+ memory_region_transaction_commit();
+}
+
+static void gmch_set_smm(int smm, void *arg)
+{
+ GMCHPCIState *gs = arg;
+
+ memory_region_transaction_begin();
+ smram_set_smm(&gs->smm_enabled, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+ &gs->smram_region);
+ memory_region_transaction_commit();
+}
+
+static void gmch_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
+
+ /* XXX: implement SMRAM.D_LOCK */
+ pci_default_write_config(d, address, val, len);
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
+ GMCH_HOST_BRIDGE_PAM_SIZE)) {
+ gmch_update_pam(gs);
+ }
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
+ GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
+ gmch_update_pciexbar(gs);
+ }
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
+ GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
+ gmch_update_smram(gs);
+ }
+}
+
+static void gmch_update(GMCHPCIState *gs)
+{
+ gmch_update_pciexbar(gs);
+ gmch_update_pam(gs);
+ gmch_update_smram(gs);
+}
+
+static int gmch_post_load(void *opaque, int version_id)
+{
+ GMCHPCIState *gs = opaque;
+ gmch_update(gs);
+ return 0;
+}
+
+static const VMStateDescription vmstate_gmch = {
+ .name = "gmch",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = gmch_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_PCI_DEVICE(d, GMCHPCIState),
+ VMSTATE_UINT8(smm_enabled, GMCHPCIState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void gmch_reset(DeviceState *qdev)
+{
+ PCIDevice *d = PCI_DEVICE(qdev);
+ GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
+
+ pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
+ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+
+ d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
+
+ gmch_update(gs);
+}
+
+static int pci_gmch_initfn(PCIDevice *d)
+{
+ GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
+
+ cpu_smm_register(&gmch_set_smm, gs);
+
+ return 0;
+}
+
+static void pci_gmch_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ k->init = pci_gmch_initfn;
+ k->config_write = gmch_write_config;
+ dc->reset = gmch_reset;
+ dc->desc = "Host bridge";
+ dc->vmsd = &vmstate_gmch;
+ dc->no_user = 1;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
+ k->revision = GMCH_HOST_BRIDGE_REVISION_DEFUALT;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+}
+
+static const TypeInfo pci_gmch_info = {
+ .name = TYPE_GMCH_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(GMCHPCIState),
+ .class_init = pci_gmch_class_init,
+};
+
+/* host bridge */
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
+{
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(gmch_host);
+ PCIDevice *d;
+
+ d = pci_create_simple_multifunction(b, 0, false, TYPE_GMCH_PCI_DEVICE);
+ s->dev = d;
+
+ return d;
+}
+
+static void q35_register(void)
+{
+ type_register_static(&pci_gmch_info);
+ type_register_static(&gmch_pcihost_info);
+}
+
+type_init(q35_register);
diff --git a/hw/q35.h b/hw/q35.h
new file mode 100644
index 0000000..0b66da7
--- /dev/null
+++ b/hw/q35.h
@@ -0,0 +1,161 @@
+/*
+ * q35.h
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_Q35_H
+#define HW_Q35_H
+
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+#include "pci_internals.h"
+
+
+#define TYPE_GMCH_HOST_DEVICE "gmch-pcihost"
+#define GMCH_HOST_DEVICE(obj) \
+ OBJECT_CHECK(GMCHPCIHost, (obj), TYPE_GMCH_HOST_DEVICE)
+
+#define TYPE_GMCH_PCI_DEVICE "gmch"
+#define GMCH_PCI_DEVICE(obj) \
+ OBJECT_CHECK(GMCHPCIState, (obj), TYPE_GMCH_PCI_DEVICE)
+
+typedef struct GMCHPCIHost {
+ PCIExpressHost host;
+ PCIDevice *dev;
+} GMCHPCIHost;
+
+typedef struct GMCHPCIState {
+ PCIDevice d;
+ /*
+ * GMCH_PCIHost *gmch_host;
+ * In order to get GMCH_PCIHost
+ * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+ */
+ MemoryRegion *ram_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *system_memory;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ uint8_t smm_enabled;
+} GMCHPCIState;
+
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io);
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
+
+#define Q35_MASK(bit, ms_bit, ls_bit) \
+((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
+
+/*
+ * gmch part
+ */
+
+/* PCI configuration */
+#define GMCH_HOST_BRIDGE "GMCH"
+
+#define GMCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
+#define GMCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
+
+/* D0:F0 configuration space */
+#define GMCH_HOST_BRIDGE_REVISION_DEFUALT 0x0
+
+#define GMCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xe0000000
+#define GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 25) /* bit 35:28 */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
+
+#define GMCH_HOST_BRIDGE_PAM_NB 7
+#define GMCH_HOST_BRIDGE_PAM_SIZE 7
+#define GMCH_HOST_BRIDGE_PAM0 0x90
+#define GMCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
+#define GMCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
+#define GMCH_HOST_BRIDGE_PAM1 0x91
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
+#define GMCH_HOST_BRIDGE_PAM2 0x92
+#define GMCH_HOST_BRIDGE_PAM3 0x93
+#define GMCH_HOST_BRIDGE_PAM4 0x94
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
+#define GMCH_HOST_BRIDGE_PAM5 0x95
+#define GMCH_HOST_BRIDGE_PAM6 0x96
+#define GMCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
+#define GMCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
+#define GMCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
+#define GMCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
+#define GMCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
+
+#define GMCH_HOST_BRDIGE_SMRAM 0x9d
+#define GMCH_HOST_BRDIGE_SMRAM_SIZE 1
+#define GMCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
+#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
+
+#define GMCH_HOST_BRIDGE_ESMRAMC 0x9e
+#define GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
+
+/* D1:F0 PCIE* port*/
+#define GMCH_PCIE_DEV 1
+#define GMCH_PCIE_FUNC 0
+
+#endif /* HW_Q35_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator Jason Baron
@ 2012-10-30 19:18 ` Anthony Liguori
2012-10-31 10:04 ` Michael S. Tsirkin
0 siblings, 1 reply; 35+ messages in thread
From: Anthony Liguori @ 2012-10-30 19:18 UTC (permalink / raw)
To: Jason Baron, qemu-devel
Cc: juzhang, mst, jan.kiszka, agraf, armbru, blauwirbel, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, kraxel
Jason Baron <jbaron@redhat.com> writes:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> pc q35 based chipset emulator to support pci express natively. Based on
> Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias
> of 'q35'. At this point, there are no compatibility guarantees. When the
> chipset stabilizes more, we will begin to version the machine names.
>
> Major features which still need to be added:
>
> -Migration support (mostly around ahci)
> -ACPI hotplug support (pcie hotplug support is working)
> -Passthrough support
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/i386/Makefile.objs | 2 +-
> hw/pc.h | 2 +
> hw/pc_piix.c | 4 +-
> hw/pc_q35.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pci_ids.h | 2 +
> hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++
> hw/q35.h | 161 ++++++++++++++++++++++++
> 7 files changed, 809 insertions(+), 3 deletions(-)
> create mode 100644 hw/pc_q35.c
> create mode 100644 hw/q35.c
> create mode 100644 hw/q35.h
>
> diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
> index 693bd18..469b127 100644
> --- a/hw/i386/Makefile.objs
> +++ b/hw/i386/Makefile.objs
> @@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o
> obj-y += pc_piix.o
> obj-y += pc_sysfw.o
> obj-y += pam.o
> -obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
> +obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o
This shouldn't be here. It should be in hw/Makefile.objs.
This is not target specific code.
> obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
> diff --git a/hw/pc.h b/hw/pc.h
> index 2237e86..e1bf2fc 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -42,6 +42,8 @@ int pic_read_irq(DeviceState *d);
> int pic_get_output(DeviceState *d);
> void pic_info(Monitor *mon);
> void irq_info(Monitor *mon);
> +void kvm_piix3_gsi_handler(void *opaque, int n, int level);
> +void kvm_piix3_setup_irq_routing(bool pci_enabled);
kvm specific code declarations shouldn't be in pc.h.
BTW, if you've got q35 calling something called "kvm_piix3..." something
is wrong. There's no piix3 in the q35.
> /* Global System Interrupts */
>
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index 7bcac87..26565a1 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -54,7 +54,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
> static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
> static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
>
> -static void kvm_piix3_setup_irq_routing(bool pci_enabled)
> +void kvm_piix3_setup_irq_routing(bool pci_enabled)
> {
> #ifdef CONFIG_KVM
> KVMState *s = kvm_state;
> @@ -83,7 +83,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)
> #endif /* CONFIG_KVM */
> }
>
> -static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
> +void kvm_piix3_gsi_handler(void *opaque, int n, int level)
> {
> GSIState *s = opaque;
>
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> new file mode 100644
> index 0000000..cf0d361
> --- /dev/null
> +++ b/hw/pc_q35.c
> @@ -0,0 +1,326 @@
> +/*
> + * Q35 chipset based pc system emulator
> + *
> + * Copyright (c) 2003-2004 Fabrice Bellard
> + * Copyright (c) 2009, 2010
> + * Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * This is based on pc.c, but heavily modified.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "hw.h"
> +#include "arch_init.h"
> +#include "pc.h"
> +#include "fdc.h"
> +#include "pci.h"
> +#include "pci_bridge.h"
> +#include "ioh3420.h"
> +#include "xio3130_upstream.h"
> +#include "xio3130_downstream.h"
There's way too many includes here. Don't just copy/paste includes.
> +#include "block.h"
> +#include "blockdev.h"
> +#include "sysemu.h"
> +#include "audio/audio.h"
> +#include "net.h"
> +#include "smbus.h"
> +#include "boards.h"
> +#include "monitor.h"
> +#include "fw_cfg.h"
> +#include "hpet_emul.h"
> +#include "watchdog.h"
> +#include "smbios.h"
> +#include "ide.h"
> +#include "mc146818rtc.h"
> +#include "xen.h"
> +#include "kvm.h"
> +
> +#include "q35.h"
> +#include "exec-memory.h"
> +#include "ich9.h"
> +#include <hw/ide/pci.h>
> +#include <hw/ide/ahci.h>
Should be double quotes..
> +
> +/* ICH9 AHCI has 6 ports */
> +#define MAX_SATA_PORTS 6
> +
> +static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state,
> + DeviceState **gmch_host_p,
> + PCIBus **host_bus_p,
> + PCIDevice **lpc_p, ISABus **isa_bus,
> + MemoryRegion *system_memory,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *address_space_io,
> + MemoryRegion *ram_memory,
> + ram_addr_t below_4g_mem_size,
> + ram_addr_t above_4g_mem_size)
> +{
> + int i;
> + hwaddr pci_hole64_size;
> + DeviceState *gmch_host;
> + PCIBus *host_bus;
> +
> + PCIDevice *gmch_state;
> + PCIDevice *lpc;
> + GMCHPCIState *gmps;
> + ICH9LPCState *ich9_lpc;
> +
> + /* create pci host bus */
> + host_bus = gmch_host_init(&gmch_host, pci_address_space, address_space_io);
> + gmch_state = gmch_init(gmch_host, host_bus);
> + gmps = GMCH_PCI_DEVICE(gmch_state);
> +
> + /* create ISA bus */
> + lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
> + ICH9_LPC_FUNC), true,
> + TYPE_ICH9_LPC_DEVICE);
Should be done through composition.
Q35 ought to be modelled as a device from the start properly.
> + ich9_lpc = ICH9_LPC_DEVICE(lpc);
> + ich9_lpc->pic = gsi;
> + ich9_lpc->ioapic = gsi_state->ioapic_irq;
> + pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
> + ICH9_LPC_NB_PIRQS);
> +
> + gmps->ram_memory = ram_memory;
> + gmps->pci_address_space = pci_address_space;
> + gmps->system_memory = system_memory;
> + /* pci */
> + memory_region_init_alias(&gmps->pci_hole, "pci-hole",
> + gmps->pci_address_space,
> + below_4g_mem_size,
> + 0x100000000ULL - below_4g_mem_size);
> + memory_region_add_subregion(gmps->system_memory, below_4g_mem_size,
> + &gmps->pci_hole);
> + pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
> + ((uint64_t)1 << 62));
> + memory_region_init_alias(&gmps->pci_hole_64bit, "pci-hole64",
> + gmps->pci_address_space,
> + 0x100000000ULL + above_4g_mem_size,
> + pci_hole64_size);
> + if (pci_hole64_size) {
> + memory_region_add_subregion(gmps->system_memory,
> + 0x100000000ULL + above_4g_mem_size,
> + &gmps->pci_hole_64bit);
> + }
> +
> + /* smram */
> + memory_region_init_alias(&gmps->smram_region, "smram-region",
> + pci_address_space, 0xa0000, 0x20000);
> + memory_region_add_subregion_overlap(system_memory, 0xa0000,
> + &gmps->smram_region, 1);
> + memory_region_set_enabled(&gmps->smram_region, false);
> + init_pam(gmps->ram_memory, gmps->system_memory, gmps->pci_address_space,
> + &gmps->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
> + for (i = 0; i < 12; ++i) {
> + init_pam(gmps->ram_memory, gmps->system_memory, gmps->pci_address_space,
> + &gmps->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
> + PAM_EXPAN_SIZE);
> + }
> +
> + *gmch_host_p = gmch_host;
> + *host_bus_p = host_bus;
> + *lpc_p = lpc;
> + *isa_bus = ich9_lpc->isa_bus;
> +}
> +
> +
> +/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
> + * BIOS will read it and start S3 resume at POST Entry */
> +static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
> +{
> + ISADevice *s = opaque;
> +
> + if (level) {
> + rtc_set_memory(s, 0xF, 0xFE);
> + }
> +}
> +
> +static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
> + DeviceState *gmch_host, PCIBus *host_bus,
> + PCIDevice *lpc)
> +{
> + qemu_irq *cmos_s3;
> + PCIDevice *ahci;
> + DriveInfo **hd;
> + struct AHCIPCIState *ahci_state;
> + int ports, max_unit, max_bus;
> +
> + /* connect pm stuff to lpc */
> + cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
> + ich9_lpc_pm_init(lpc, *cmos_s3);
> +
> + /* ahci and SATA device, for q35 1 ahci controller is built-in */
> + ahci = pci_create_simple_multifunction(host_bus,
> + PCI_DEVFN(ICH9_SATA1_DEV,
> + ICH9_SATA1_FUNC),
> + true, "ich9-ahci");
> + ahci_state = DO_UPCAST(struct AHCIPCIState, card, ahci);
> + ports = ahci_state->ahci.ports;
> + max_unit = drive_get_max_unit(IF_AHCI);
> + if (max_unit >= ports) {
> + fprintf(stderr, "%d ports are available on the host ahci controller.\n"
> + "Ignoring extra assignments.\n", ports);
> + }
> + max_bus = drive_get_max_bus(IF_AHCI);
> + if (max_bus > 0) {
> + fprintf(stderr, "1 bus is available on the host ahci controller.\n"
> + "Ignoring extra assignments.\n");
> + }
> + hd = g_malloc(ports * sizeof(DriveInfo *));
> + ahci_drive_get(hd, 0, ports);
> + pci_ahci_create_devs(ahci, hd, ports);
> + idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
> + idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
> +
> + if (usb_enabled(false)) {
> + /* Should we create 6 UHCI according to ich9 spec? */
> + pci_create_simple_multifunction(
> + host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
> + true, "ich9-usb-uhci1");
> + /* XXX: EHCI */
> + }
> +
> + /* TODO: Populate SPD eeprom data. */
> + smbus_eeprom_init(ich9_smb_init(host_bus,
> + PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
> + 0xb100),
> + 8, NULL, 0);
> +}
> +
> +/* PC hardware initialisation */
> +static void pc_q35_init(QEMUMachineInitArgs *args)
> +{
> + ram_addr_t ram_size = args->ram_size;
> + const char *cpu_model = args->cpu_model;
> + const char *kernel_filename = args->kernel_filename;
> + const char *kernel_cmdline = args->kernel_cmdline;
> + const char *initrd_filename = args->initrd_filename;
> + const char *boot_device = args->boot_device;
> + ram_addr_t below_4g_mem_size, above_4g_mem_size;
> + DeviceState *gmch_host;
> + PCIBus *host_bus;
> + PCIDevice *lpc;
> + BusState *idebus[MAX_SATA_PORTS];
> + ISADevice *rtc_state;
> + ISADevice *floppy;
> + MemoryRegion *pci_memory;
> + MemoryRegion *rom_memory;
> + MemoryRegion *ram_memory;
> + GSIState *gsi_state;
> + ISABus *isa_bus;
> + int pci_enabled = 1;
> + qemu_irq *cpu_irq;
> + qemu_irq *gsi;
> + qemu_irq *i8259;
All this should live in a device structure.
> + int i;
> +
> + pc_cpus_init(cpu_model);
> +
> + if (ram_size >= 0xb0000000) {
> + above_4g_mem_size = ram_size - 0xb0000000;
> + below_4g_mem_size = 0xb0000000;
> + } else {
> + above_4g_mem_size = 0;
> + below_4g_mem_size = ram_size;
> + }
> +
> + /* pci enabled */
> + if (pci_enabled) {
> + pci_memory = g_new(MemoryRegion, 1);
> + memory_region_init(pci_memory, "pci", INT64_MAX);
> + rom_memory = pci_memory;
> + } else {
> + pci_memory = NULL;
> + rom_memory = get_system_memory();
> + }
> +
> + /* allocate ram and load rom/bios */
> + if (!xen_enabled()) {
> + pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
> + initrd_filename, below_4g_mem_size, above_4g_mem_size,
> + rom_memory, &ram_memory);
> + }
> +
> + /* irq lines */
> + gsi_state = g_malloc0(sizeof(*gsi_state));
> + if (kvm_irqchip_in_kernel()) {
> + kvm_piix3_setup_irq_routing(pci_enabled);
> + gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
> + GSI_NUM_PINS);
> + } else {
> + gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
> + }
> +
> + pc_q35_init_early(gsi, gsi_state,
> + &gmch_host, &host_bus, &lpc, &isa_bus,
> + get_system_memory(), pci_memory, get_system_io(),
> + ram_memory, below_4g_mem_size, above_4g_mem_size);
> + isa_bus_irqs(isa_bus, gsi);
> +
> + if (kvm_irqchip_in_kernel()) {
> + i8259 = kvm_i8259_init(isa_bus);
> + } else if (xen_enabled()) {
> + i8259 = xen_interrupt_controller_init();
> + } else {
> + cpu_irq = pc_allocate_cpu_irq();
> + i8259 = i8259_init(isa_bus, cpu_irq[0]);
> + }
> +
> + for (i = 0; i < ISA_NUM_IRQS; i++) {
> + gsi_state->i8259_irq[i] = i8259[i];
> + }
> + if (pci_enabled) {
> + ioapic_init_gsi(gsi_state, NULL);
> + }
> +
> + pc_register_ferr_irq(gsi[13]);
> +
> + /* init basic PC hardware */
> + pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
> +
> + pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, lpc);
> +
> + pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
> + floppy, idebus[0], idebus[1], rtc_state);
> +
> + /* the rest devices to which pci devfn is automatically assigned */
> + pc_vga_init(isa_bus, host_bus);
> + audio_init(isa_bus, host_bus);
> + pc_nic_init(isa_bus, host_bus);
> + if (pci_enabled) {
> + pc_pci_device_init(host_bus);
> + }
> +}
> +
> +static QEMUMachine pc_q35_machine = {
> + .name = "q35-next",
> + .alias = "q35",
> + .desc = "Q35 chipset PC",
> + .init = pc_q35_init,
> + .max_cpus = 255,
> + .default_drive_if = IF_AHCI,
> +};
> +
> +static void pc_q35_machine_init(void)
> +{
> + qemu_register_machine(&pc_q35_machine);
> +}
> +
> +machine_init(pc_q35_machine_init);
> diff --git a/hw/pci_ids.h b/hw/pci_ids.h
> index 17ae42e..ef24181 100644
> --- a/hw/pci_ids.h
> +++ b/hw/pci_ids.h
> @@ -137,6 +137,8 @@
> #define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c
> #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
>
> +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
> +
> #define PCI_VENDOR_ID_XEN 0x5853
> #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
>
> diff --git a/hw/q35.c b/hw/q35.c
> new file mode 100644
> index 0000000..1fd8802
> --- /dev/null
> +++ b/hw/q35.c
> @@ -0,0 +1,315 @@
> +/*
> + * QEMU GMCH/ICH9 PCI Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2009, 2010, 2011
> + * Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * This is based on piix_pci.c, but heavily modified.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "hw.h"
> +#include "range.h"
> +#include "isa.h"
> +#include "sysbus.h"
> +#include "pc.h"
> +#include "apm.h"
> +#include "apic.h"
> +#include "pci.h"
> +#include "pcie_host.h"
> +#include "pci_bridge.h"
> +#include "q35.h"
> +#include "acpi.h"
> +#include "acpi_ich9.h"
> +#include "pam.h"
> +#include "pci_internals.h"
> +#include "exec-memory.h"
> +#include "isa.h"
> +#include "qemu-common.h"
> +#include "ich9.h"
> +
> +
> +
> +/****************************************************************************
> + * GMCH PCI host
> + */
> +
> +static int gmch_pcihost_initfn(SysBusDevice *dev)
> +{
> + PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
> + GMCHPCIHost *s = GMCH_HOST_DEVICE(&dev->qdev);
> +
> + memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
> + "pci-conf-idx", 4);
> + sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
> + sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_ADDR, 4);
> +
> + memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
> + "pci-conf-data", 4);
> + sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
> + sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_DATA, 4);
> +
> + if (pcie_host_init(&s->host) < 0) {
> + abort();
Just return -1, it has the same affect but nicer errors.
> + }
> +
> + return 0;
> +}
> +
> +static Property gmch_props[] = {
> + DEFINE_PROP_UINT64("MCFG", GMCHPCIHost, host.base_addr,
> + GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void gmch_pcihost_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> + k->init = gmch_pcihost_initfn;
> + dc->props = gmch_props;
> + dc->no_user = 1;
no_user is meaningless...
> +}
> +
> +static const TypeInfo gmch_pcihost_info = {
> + .name = TYPE_GMCH_HOST_DEVICE,
> + .parent = TYPE_PCIE_HOST_BRIDGE,
> + .instance_size = sizeof(GMCHPCIHost),
> + .class_init = gmch_pcihost_class_init,
> +};
> +
> +/* host bridge */
> +PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *address_space_io)
> +{
> + DeviceState *dev;
> + GMCHPCIHost *s;
> + PCIBus *b;
> +
> + dev = qdev_create(NULL, TYPE_GMCH_HOST_DEVICE);
> + s = GMCH_HOST_DEVICE(dev);
> + b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", pci_address_space,
> + address_space_io, 0);
> + s->host.pci.bus = b;
> + qdev_init_nofail(dev);
> + *gmch_hostp = dev;
> + return b;
> +}
> +
> +
> +/****************************************************************************
> + * GMCH D0:F0
> + */
> +
> +/* PCIE MMCFG */
> +static void gmch_update_pciexbar(GMCHPCIState *gs)
> +{
> + PCIDevice *pci_dev = &gs->d;
> + BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
> + DeviceState *qdev = bus->parent;
> + GMCHPCIHost *s = GMCH_HOST_DEVICE(qdev);
> +
> + uint64_t pciexbar;
> + int enable;
> + uint64_t addr;
> + uint64_t addr_mask;
> + uint32_t length;
> +
> + pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
> + enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
> +
> + addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
> + switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
> + length = 256 * 1024 * 1024;
> + break;
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
> + length = 128 * 1024 * 1024;
> + addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
> + GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
> + break;
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
> + length = 64 * 1024 * 1024;
> + addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
> + break;
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
> + default:
> + enable = 0;
> + length = 0;
> + abort();
> + break;
> + }
> + addr = pciexbar & addr_mask;
> +
> + pcie_host_mmcfg_update(&s->host, enable, addr, length);
> +}
> +
> +/* PAM */
> +static void gmch_update_pam(GMCHPCIState *gs)
> +{
> + int i;
> +
> + memory_region_transaction_begin();
> + for (i = 0; i < 13; i++) {
> + pam_update(&gs->pam_regions[i], i,
> + gs->d.config[GMCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
> + }
> + memory_region_transaction_commit();
> +}
> +
> +/* SMRAM */
> +static void gmch_update_smram(GMCHPCIState *gs)
> +{
> + memory_region_transaction_begin();
> + smram_update(&gs->smram_region, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
> + gs->smm_enabled);
> + memory_region_transaction_commit();
> +}
> +
> +static void gmch_set_smm(int smm, void *arg)
> +{
> + GMCHPCIState *gs = arg;
> +
> + memory_region_transaction_begin();
> + smram_set_smm(&gs->smm_enabled, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
> + &gs->smram_region);
> + memory_region_transaction_commit();
> +}
> +
> +static void gmch_write_config(PCIDevice *d,
> + uint32_t address, uint32_t val, int len)
> +{
> + GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
> +
> + /* XXX: implement SMRAM.D_LOCK */
> + pci_default_write_config(d, address, val, len);
> +
> + if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
> + GMCH_HOST_BRIDGE_PAM_SIZE)) {
> + gmch_update_pam(gs);
> + }
> +
> + if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
> + GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
> + gmch_update_pciexbar(gs);
> + }
> +
> + if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
> + GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
> + gmch_update_smram(gs);
> + }
> +}
> +
> +static void gmch_update(GMCHPCIState *gs)
> +{
> + gmch_update_pciexbar(gs);
> + gmch_update_pam(gs);
> + gmch_update_smram(gs);
> +}
> +
> +static int gmch_post_load(void *opaque, int version_id)
> +{
> + GMCHPCIState *gs = opaque;
> + gmch_update(gs);
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_gmch = {
> + .name = "gmch",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .post_load = gmch_post_load,
> + .fields = (VMStateField []) {
> + VMSTATE_PCI_DEVICE(d, GMCHPCIState),
> + VMSTATE_UINT8(smm_enabled, GMCHPCIState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void gmch_reset(DeviceState *qdev)
> +{
> + PCIDevice *d = PCI_DEVICE(qdev);
> + GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
> +
> + pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
> + GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
> +
> + d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
> +
> + gmch_update(gs);
> +}
> +
> +static int pci_gmch_initfn(PCIDevice *d)
> +{
> + GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
> +
> + cpu_smm_register(&gmch_set_smm, gs);
> +
> + return 0;
> +}
> +
> +static void pci_gmch_class_init(ObjectClass *klass, void *data)
> +{
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + k->init = pci_gmch_initfn;
> + k->config_write = gmch_write_config;
> + dc->reset = gmch_reset;
> + dc->desc = "Host bridge";
> + dc->vmsd = &vmstate_gmch;
> + dc->no_user = 1;
> + k->vendor_id = PCI_VENDOR_ID_INTEL;
> + k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
> + k->revision = GMCH_HOST_BRIDGE_REVISION_DEFUALT;
> + k->class_id = PCI_CLASS_BRIDGE_HOST;
> +}
> +
> +static const TypeInfo pci_gmch_info = {
> + .name = TYPE_GMCH_PCI_DEVICE,
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(GMCHPCIState),
> + .class_init = pci_gmch_class_init,
> +};
So I think you could pretty easily make GMCH inherit from a generic
Northbridge to get the code sharing I was talking about before.
> +
> +/* host bridge */
> +PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
> +{
> + GMCHPCIHost *s = GMCH_HOST_DEVICE(gmch_host);
> + PCIDevice *d;
> +
> + d = pci_create_simple_multifunction(b, 0, false, TYPE_GMCH_PCI_DEVICE);
> + s->dev = d;
> +
> + return d;
> +}
> +
> +static void q35_register(void)
> +{
> + type_register_static(&pci_gmch_info);
> + type_register_static(&gmch_pcihost_info);
> +}
> +
> +type_init(q35_register);
> diff --git a/hw/q35.h b/hw/q35.h
> new file mode 100644
> index 0000000..0b66da7
> --- /dev/null
> +++ b/hw/q35.h
> @@ -0,0 +1,161 @@
> +/*
> + * q35.h
> + *
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +
> +#ifndef HW_Q35_H
> +#define HW_Q35_H
> +
> +#include "hw.h"
> +#include "range.h"
> +#include "isa.h"
> +#include "sysbus.h"
> +#include "pc.h"
> +#include "apm.h"
> +#include "apic.h"
> +#include "pci.h"
> +#include "pcie_host.h"
> +#include "pci_bridge.h"
> +#include "q35.h"
> +#include "acpi.h"
> +#include "acpi_ich9.h"
> +#include "pam.h"
> +#include "pci_internals.h"
> +
> +
> +#define TYPE_GMCH_HOST_DEVICE "gmch-pcihost"
> +#define GMCH_HOST_DEVICE(obj) \
> + OBJECT_CHECK(GMCHPCIHost, (obj), TYPE_GMCH_HOST_DEVICE)
> +
> +#define TYPE_GMCH_PCI_DEVICE "gmch"
> +#define GMCH_PCI_DEVICE(obj) \
> + OBJECT_CHECK(GMCHPCIState, (obj), TYPE_GMCH_PCI_DEVICE)
> +
> +typedef struct GMCHPCIHost {
> + PCIExpressHost host;
> + PCIDevice *dev;
> +} GMCHPCIHost;
> +
> +typedef struct GMCHPCIState {
> + PCIDevice d;
> + /*
> + * GMCH_PCIHost *gmch_host;
> + * In order to get GMCH_PCIHost
> + * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
> + */
> + MemoryRegion *ram_memory;
> + MemoryRegion *pci_address_space;
> + MemoryRegion *system_memory;
> + PAMMemoryRegion pam_regions[13];
> + MemoryRegion smram_region;
> + MemoryRegion pci_hole;
> + MemoryRegion pci_hole_64bit;
> + uint8_t smm_enabled;
> +} GMCHPCIState;
> +
> +PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *address_space_io);
> +PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
> +
> +#define Q35_MASK(bit, ms_bit, ls_bit) \
> +((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit)
> - 1)))
This is pretty wacky!
> +
> +/*
> + * gmch part
> + */
> +
> +/* PCI configuration */
> +#define GMCH_HOST_BRIDGE "GMCH"
> +
> +#define GMCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
> +#define GMCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
> +
> +/* D0:F0 configuration space */
> +#define GMCH_HOST_BRIDGE_REVISION_DEFUALT 0x0
> +
> +#define GMCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xe0000000
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 25) /* bit 35:28 */
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
The way these defines are setup are strange... Why isn't everythign
using Q35_MASK?
Regards,
Anthony Liguori
> +
> +#define GMCH_HOST_BRIDGE_PAM_NB 7
> +#define GMCH_HOST_BRIDGE_PAM_SIZE 7
> +#define GMCH_HOST_BRIDGE_PAM0 0x90
> +#define GMCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
> +#define GMCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
> +#define GMCH_HOST_BRIDGE_PAM1 0x91
> +#define GMCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
> +#define GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
> +#define GMCH_HOST_BRIDGE_PAM2 0x92
> +#define GMCH_HOST_BRIDGE_PAM3 0x93
> +#define GMCH_HOST_BRIDGE_PAM4 0x94
> +#define GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
> +#define GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
> +#define GMCH_HOST_BRIDGE_PAM5 0x95
> +#define GMCH_HOST_BRIDGE_PAM6 0x96
> +#define GMCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
> +#define GMCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
> +#define GMCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
> +#define GMCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
> +#define GMCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
> +#define GMCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
> +#define GMCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
> +#define GMCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
> +#define GMCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
> +
> +#define GMCH_HOST_BRDIGE_SMRAM 0x9d
> +#define GMCH_HOST_BRDIGE_SMRAM_SIZE 1
> +#define GMCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
> +#define GMCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
> +#define GMCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
> +#define GMCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
> +#define GMCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
> +#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
> +#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
> +#define GMCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
> +#define GMCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
> +#define GMCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
> +#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
> +
> +#define GMCH_HOST_BRIDGE_ESMRAMC 0x9e
> +#define GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
> +
> +/* D1:F0 PCIE* port*/
> +#define GMCH_PCIE_DEV 1
> +#define GMCH_PCIE_FUNC 0
> +
> +#endif /* HW_Q35_H */
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator
2012-10-30 19:18 ` Anthony Liguori
@ 2012-10-31 10:04 ` Michael S. Tsirkin
2012-10-31 12:53 ` Anthony Liguori
0 siblings, 1 reply; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 10:04 UTC (permalink / raw)
To: Anthony Liguori
Cc: agraf, juzhang, jan.kiszka, Jason Baron, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Tue, Oct 30, 2012 at 02:18:02PM -0500, Anthony Liguori wrote:
> Jason Baron <jbaron@redhat.com> writes:
>
> > From: Isaku Yamahata <yamahata@valinux.co.jp>
> >
> > pc q35 based chipset emulator to support pci express natively. Based on
> > Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias
> > of 'q35'. At this point, there are no compatibility guarantees. When the
> > chipset stabilizes more, we will begin to version the machine names.
> >
> > Major features which still need to be added:
> >
> > -Migration support (mostly around ahci)
> > -ACPI hotplug support (pcie hotplug support is working)
> > -Passthrough support
> >
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > ---
> > hw/i386/Makefile.objs | 2 +-
> > hw/pc.h | 2 +
> > hw/pc_piix.c | 4 +-
> > hw/pc_q35.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++++
> > hw/pci_ids.h | 2 +
> > hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++
> > hw/q35.h | 161 ++++++++++++++++++++++++
> > 7 files changed, 809 insertions(+), 3 deletions(-)
> > create mode 100644 hw/pc_q35.c
> > create mode 100644 hw/q35.c
> > create mode 100644 hw/q35.h
> >
> > diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
> > index 693bd18..469b127 100644
> > --- a/hw/i386/Makefile.objs
> > +++ b/hw/i386/Makefile.objs
> > @@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o
> > obj-y += pc_piix.o
> > obj-y += pc_sysfw.o
> > obj-y += pam.o
> > -obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
> > +obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o
>
> This shouldn't be here. It should be in hw/Makefile.objs.
>
> This is not target specific code.
What about acpi_ich9.o lpc_ich9.o smbus_ich9.o? Should it move to Makefile.objs too?
How is this different from pc_piix?
--
MST
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator
2012-10-31 10:04 ` Michael S. Tsirkin
@ 2012-10-31 12:53 ` Anthony Liguori
0 siblings, 0 replies; 35+ messages in thread
From: Anthony Liguori @ 2012-10-31 12:53 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: agraf, juzhang, jan.kiszka, Jason Baron, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
"Michael S. Tsirkin" <mst@redhat.com> writes:
> On Tue, Oct 30, 2012 at 02:18:02PM -0500, Anthony Liguori wrote:
>> Jason Baron <jbaron@redhat.com> writes:
>>
>> > From: Isaku Yamahata <yamahata@valinux.co.jp>
>> >
>> > pc q35 based chipset emulator to support pci express natively. Based on
>> > Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias
>> > of 'q35'. At this point, there are no compatibility guarantees. When the
>> > chipset stabilizes more, we will begin to version the machine names.
>> >
>> > Major features which still need to be added:
>> >
>> > -Migration support (mostly around ahci)
>> > -ACPI hotplug support (pcie hotplug support is working)
>> > -Passthrough support
>> >
>> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
>> > Signed-off-by: Jason Baron <jbaron@redhat.com>
>> > ---
>> > hw/i386/Makefile.objs | 2 +-
>> > hw/pc.h | 2 +
>> > hw/pc_piix.c | 4 +-
>> > hw/pc_q35.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++++
>> > hw/pci_ids.h | 2 +
>> > hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++
>> > hw/q35.h | 161 ++++++++++++++++++++++++
>> > 7 files changed, 809 insertions(+), 3 deletions(-)
>> > create mode 100644 hw/pc_q35.c
>> > create mode 100644 hw/q35.c
>> > create mode 100644 hw/q35.h
>> >
>> > diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
>> > index 693bd18..469b127 100644
>> > --- a/hw/i386/Makefile.objs
>> > +++ b/hw/i386/Makefile.objs
>> > @@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o
>> > obj-y += pc_piix.o
>> > obj-y += pc_sysfw.o
>> > obj-y += pam.o
>> > -obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
>> > +obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o
>>
>> This shouldn't be here. It should be in hw/Makefile.objs.
>>
>> This is not target specific code.
>
> What about acpi_ich9.o lpc_ich9.o smbus_ich9.o? Should it move to Makefile.objs too?
>
> How is this different from pc_piix?
Yes, everything should be in Makefile.objs unless it depends on
CPUState.
Regards,
Anthony Liguori
>
> --
> MST
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 08/13] q35: Suppress SMM BIOS initialization under KVM
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (6 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 07/13] q35: Introduce q35 pc based chipset emulator Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 09/13] q35: Add kvmclock support Jason Baron
` (5 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index c45921c..61034d3 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -28,6 +28,7 @@
#include "qemu-timer.h"
#include "sysemu.h"
#include "acpi.h"
+#include "kvm.h"
#include "ich9.h"
@@ -292,6 +293,12 @@ static void pm_reset(void *opaque)
acpi_pm_tmr_reset(&pm->acpi_regs);
acpi_gpe_reset(&pm->acpi_regs);
+ if (kvm_enabled()) {
+ /* Mark SMM as already inited to prevent SMM from running. KVM does not
+ * support SMM mode. */
+ pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
+ }
+
pm_update_sci(pm);
}
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* [Qemu-devel] [PATCH v1 09/13] q35: Add kvmclock support
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (7 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 08/13] q35: Suppress SMM BIOS initialization under KVM Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 11/13] q35: automatically load the q35 dsdt table Jason Baron
` (4 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc_q35.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index cf0d361..1f31486 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -52,6 +52,7 @@
#include "mc146818rtc.h"
#include "xen.h"
#include "kvm.h"
+#include "kvm/clock.h"
#include "q35.h"
#include "exec-memory.h"
@@ -233,6 +234,8 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
pc_cpus_init(cpu_model);
+ kvmclock_create();
+
if (ram_size >= 0xb0000000) {
above_4g_mem_size = ram_size - 0xb0000000;
below_4g_mem_size = 0xb0000000;
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* [Qemu-devel] [PATCH v1 11/13] q35: automatically load the q35 dsdt table
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (8 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 09/13] q35: Add kvmclock support Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 10/13] Add a fallback bios file search, if -L fails Jason Baron
` (3 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 19 +++++++++++++++++++
hw/pc.h | 2 ++
hw/pc_q35.c | 7 +++++++
3 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index af1a076..743d771 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1153,3 +1153,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
}
}
+
+int find_and_load_dsdt(const char *dsdt_name)
+{
+ char *filename;
+ char buf[1024];
+
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
+ if (!filename) {
+ return -1;
+ }
+ snprintf(buf, sizeof(buf), "file=%s", filename);
+ g_free(filename);
+ if (acpi_table_add(buf) < 0) {
+ fprintf(stderr, "Wrong acpi table provided\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/hw/pc.h b/hw/pc.h
index e1bf2fc..1a3db90 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -187,5 +187,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
#define E820_UNUSABLE 5
int e820_add_entry(uint64_t, uint64_t, uint32_t);
+int find_and_load_dsdt(const char *dsdt_name);
+
#endif
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 1f31486..a9a7f6c 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -232,6 +232,13 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
qemu_irq *i8259;
int i;
+ /* let's first see if we can find the proper dsdt */
+ if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
+ fprintf(stderr, "Couldn't find q35 dsdt table!\n"
+ "Try updating your bios.\n");
+ exit(1);
+ }
+
pc_cpus_init(cpu_model);
kvmclock_create();
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* [Qemu-devel] [PATCH v1 10/13] Add a fallback bios file search, if -L fails.
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (9 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 11/13] q35: automatically load the q35 dsdt table Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb Jason Baron
` (2 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
vl.c | 36 +++++++++++++++++++++++++-----------
1 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/vl.c b/vl.c
index 824d8ae..59e8d2f 100644
--- a/vl.c
+++ b/vl.c
@@ -177,6 +177,7 @@ int main(int argc, char **argv)
#define MAX_VIRTIO_CONSOLES 1
static const char *data_dir;
+static const char *data_dir_fallback;
const char *bios_name = NULL;
enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
DisplayType display_type = DT_DEFAULT;
@@ -1904,16 +1905,16 @@ static int balloon_parse(const char *arg)
return -1;
}
-char *qemu_find_file(int type, const char *name)
+static char *qemu_find_file_in_dir(int type, const char *name, const char *dir)
{
int len;
const char *subdir;
char *buf;
- /* Try the name as a straight path first */
- if (access(name, R_OK) == 0) {
- return g_strdup(name);
+ if (!dir) {
+ return NULL;
}
+
switch (type) {
case QEMU_FILE_TYPE_BIOS:
subdir = "";
@@ -1924,9 +1925,9 @@ char *qemu_find_file(int type, const char *name)
default:
abort();
}
- len = strlen(data_dir) + strlen(name) + strlen(subdir) + 2;
+ len = strlen(dir) + strlen(name) + strlen(subdir) + 2;
buf = g_malloc0(len);
- snprintf(buf, len, "%s/%s%s", data_dir, subdir, name);
+ snprintf(buf, len, "%s/%s%s", dir, subdir, name);
if (access(buf, R_OK)) {
g_free(buf);
return NULL;
@@ -1934,6 +1935,21 @@ char *qemu_find_file(int type, const char *name)
return buf;
}
+char *qemu_find_file(int type, const char *name)
+{
+ char *filename;
+
+ /* Try the name as a straight path first */
+ if (access(name, R_OK) == 0) {
+ return g_strdup(name);
+ }
+ filename = qemu_find_file_in_dir(type, name, data_dir);
+ if (!filename) {
+ filename = qemu_find_file_in_dir(type, name, data_dir_fallback);
+ }
+ return filename;
+}
+
static int device_help_func(QemuOpts *opts, void *opaque)
{
return qdev_device_help(opts);
@@ -3377,12 +3393,10 @@ int main(int argc, char **argv, char **envp)
/* If no data_dir is specified then try to find it relative to the
executable path. */
- if (!data_dir) {
- data_dir = os_find_datadir(argv[0]);
- }
+ data_dir_fallback = os_find_datadir(argv[0]);
/* If all else fails use the install path specified when building. */
- if (!data_dir) {
- data_dir = CONFIG_QEMU_DATADIR;
+ if (!data_dir_fallback) {
+ data_dir_fallback = CONFIG_QEMU_DATADIR;
}
/*
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (10 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 10/13] Add a fallback bios file search, if -L fails Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-30 6:34 ` Gerd Hoffmann
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses Jason Baron
2012-10-30 19:20 ` [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Anthony Liguori
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, gsomlo, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
This fills out the usb slots on q35, when -usb is passed.
We now have (lspci output):
00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 03)
00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 03)
00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 03)
00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 03)
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/ich9.h | 5 ++++-
hw/pc_q35.c | 26 ++++++++++++++++++++++----
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/ich9.h b/hw/ich9.h
index 10c6d47..c4d04a7 100644
--- a/hw/ich9.h
+++ b/hw/ich9.h
@@ -86,8 +86,11 @@ typedef struct ICH9LPCState {
/* D29:F0 USB UHCI Controller #1 */
-#define ICH9_USB_UHCI1_DEV 29
+#define ICH9_USB_DEV 29
#define ICH9_USB_UHCI1_FUNC 0
+#define ICH9_USB_UHCI2_FUNC 1
+#define ICH9_USB_UHCI3_FUNC 2
+#define ICH9_USB_EHCI1_FUNC 7
/* D30:F0 DMI-to-PCI brdige */
#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index a9a7f6c..714aeaf 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -191,11 +191,29 @@ static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
if (usb_enabled(false)) {
+ int i;
+ PCIDevice *usb;
+ DeviceState *usb_qdev;
+ char uhci_devname[] = "ich9-usb-uhciX";
+
/* Should we create 6 UHCI according to ich9 spec? */
- pci_create_simple_multifunction(
- host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
- true, "ich9-usb-uhci1");
- /* XXX: EHCI */
+ usb = pci_create_multifunction(
+ host_bus, PCI_DEVFN(ICH9_USB_DEV, ICH9_USB_EHCI1_FUNC),
+ true, "ich9-usb-ehci1");
+ usb_qdev = &usb->qdev;
+ usb_qdev->id = g_strdup("ich9-usb-bus");
+ qdev_init_nofail(usb_qdev);
+
+ for (i = 0; i < 3; i++) {
+ uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;
+ usb = pci_create_multifunction(
+ host_bus, PCI_DEVFN(ICH9_USB_DEV, ICH9_USB_UHCI1_FUNC + i),
+ true, uhci_devname);
+ usb_qdev = &usb->qdev;
+ qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");
+ qdev_prop_set_uint32(usb_qdev, "firstport", i * 2);
+ qdev_init_nofail(usb_qdev);
+ }
}
/* TODO: Populate SPD eeprom data. */
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb Jason Baron
@ 2012-10-30 6:34 ` Gerd Hoffmann
2012-10-30 15:19 ` Jason Baron
0 siblings, 1 reply; 35+ messages in thread
From: Gerd Hoffmann @ 2012-10-30 6:34 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, gsomlo, mkletzan, pbonzini,
lcapitulino, afaerber, armbru
Hi,
> + uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;
snprintf(devname, sizeof(devname), "...%d", i) is more readable.
> + qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");
Any reason why you rename the usb bus?
cheers,
Gerd
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb
2012-10-30 6:34 ` Gerd Hoffmann
@ 2012-10-30 15:19 ` Jason Baron
2012-10-30 16:19 ` Gerd Hoffmann
0 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 15:19 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, gsomlo, mkletzan, pbonzini,
lcapitulino, afaerber, armbru
On Tue, Oct 30, 2012 at 07:34:26AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > + uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;
>
> snprintf(devname, sizeof(devname), "...%d", i) is more readable.
ok.
>
> > + qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");
>
> Any reason why you rename the usb bus?
>
I wasn't sure if the user created usb devices on the command-line via
-device if that would break naming here. Thus, I added a 'private' name.
If the naming is stable, that works. It would be 'usb-bus.0', in that
case?
Thanks,
-Jason
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb
2012-10-30 15:19 ` Jason Baron
@ 2012-10-30 16:19 ` Gerd Hoffmann
2012-10-30 18:00 ` Jason Baron
0 siblings, 1 reply; 35+ messages in thread
From: Gerd Hoffmann @ 2012-10-30 16:19 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, gsomlo, mkletzan, pbonzini,
lcapitulino, afaerber, armbru
On 10/30/12 16:19, Jason Baron wrote:
> On Tue, Oct 30, 2012 at 07:34:26AM +0100, Gerd Hoffmann wrote:
>> Hi,
>>
>>> + uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;
>>
>> snprintf(devname, sizeof(devname), "...%d", i) is more readable.
>
> ok.
>
>>
>>> + qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");
>>
>> Any reason why you rename the usb bus?
>>
>
> I wasn't sure if the user created usb devices on the command-line via
> -device if that would break naming here. Thus, I added a 'private' name.
> If the naming is stable, that works. It would be 'usb-bus.0', in that
> case?
"usb.0" would be the default name, but you don't need to know it, you
can just look up what qdev created. See here:
http://www.kraxel.org/cgit/qemu/commit/?h=rebase/usb-next&id=70b9867011c4793787c5acee3d2005a6bc951f59
[ This is part of the "usb patch queue" patch series posted today,
depending on how the qom discussions go and how fast it goes in
you might just call the function the patch provides. Or do
something simliar in pc_q35.c and I'll drop the patch. ]
-usb for -M pc creates a "usb.0" bus too, so I don't expect trouble.
cheers,
Gerd
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb
2012-10-30 16:19 ` Gerd Hoffmann
@ 2012-10-30 18:00 ` Jason Baron
0 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-30 18:00 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, juzhang, kevin, avi, gsomlo, mkletzan,
pbonzini, lcapitulino, afaerber, armbru
On Tue, Oct 30, 2012 at 05:19:01PM +0100, Gerd Hoffmann wrote:
> On 10/30/12 16:19, Jason Baron wrote:
> > On Tue, Oct 30, 2012 at 07:34:26AM +0100, Gerd Hoffmann wrote:
> >> Hi,
> >>
> >>> + uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;
> >>
> >> snprintf(devname, sizeof(devname), "...%d", i) is more readable.
> >
> > ok.
> >
> >>
> >>> + qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");
> >>
> >> Any reason why you rename the usb bus?
> >>
> >
> > I wasn't sure if the user created usb devices on the command-line via
> > -device if that would break naming here. Thus, I added a 'private' name.
> > If the naming is stable, that works. It would be 'usb-bus.0', in that
> > case?
>
> "usb.0" would be the default name, but you don't need to know it, you
> can just look up what qdev created. See here:
>
> http://www.kraxel.org/cgit/qemu/commit/?h=rebase/usb-next&id=70b9867011c4793787c5acee3d2005a6bc951f59
yes, much better :)
>
> [ This is part of the "usb patch queue" patch series posted today,
> depending on how the qom discussions go and how fast it goes in
> you might just call the function the patch provides. Or do
> something simliar in pc_q35.c and I'll drop the patch. ]
>
> -usb for -M pc creates a "usb.0" bus too, so I don't expect trouble.
>
I think your patch, is a generally useful helper function. Thus, I plan to
incorporate something similar to your patch, but less general in pc_q35.c. So
usb can get testing, and when your patch lands I will drop the extra usb
bits in pc_q35.c.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (11 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 12/13] q35: fill in usb pci slots with -usb Jason Baron
@ 2012-10-30 2:11 ` Jason Baron
2012-10-31 8:59 ` Michael S. Tsirkin
2012-10-30 19:20 ` [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Anthony Liguori
13 siblings, 1 reply; 35+ messages in thread
From: Jason Baron @ 2012-10-30 2:11 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Cleanup the q35/ich9 license headers.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 13 +++++++------
hw/lpc_ich9.c | 32 ++++++++------------------------
hw/smbus_ich9.c | 14 ++++++++------
3 files changed, 23 insertions(+), 36 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 61034d3..25c9d36 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -2,6 +2,11 @@
* ACPI implementation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * This is based on acpi.c.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -14,13 +19,9 @@
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-/*
- * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
- * VA Linux Systems Japan K.K.
- * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
- * This is based on acpi.c.
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
*/
#include "hw.h"
#include "pc.h"
diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c
index 4116c50..90129db 100644
--- a/hw/lpc_ich9.c
+++ b/hw/lpc_ich9.c
@@ -1,5 +1,13 @@
/*
+ * QEMU ICH9 Emulation
+ *
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2009, 2010, 2011
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * This is based on piix_pci.c, but heavily modified.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -19,30 +27,6 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-/*
- * QEMU ICH9 Emulation
- *
- * Copyright (c) 2009, 2010, 2011
- * Isaku Yamahata <yamahata at valinux co jp>
- * VA Linux Systems Japan K.K.
- * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
- *
- * This is based on piix_pci.c, but heavily modified.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-
#include "qemu-common.h"
#include "hw.h"
#include "range.h"
diff --git a/hw/smbus_ich9.c b/hw/smbus_ich9.c
index 6940583..6d31e24 100644
--- a/hw/smbus_ich9.c
+++ b/hw/smbus_ich9.c
@@ -2,6 +2,11 @@
* ACPI implementation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * This is based on acpi.c, but heavily rewritten.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -14,13 +19,10 @@
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-/*
- * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
- * VA Linux Systems Japan K.K.
- * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
- * This is based on acpi.c, but heavily rewritten.
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ *
*/
#include "hw.h"
#include "pc.h"
--
1.7.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses Jason Baron
@ 2012-10-31 8:59 ` Michael S. Tsirkin
2012-10-31 9:34 ` Isaku Yamahata
0 siblings, 1 reply; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 8:59 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 29, 2012 at 10:11:31PM -0400, Jason Baron wrote:
> From: Jason Baron <jbaron@redhat.com>
>
> Cleanup the q35/ich9 license headers.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Isaku Yamahata, could you confirm this one please?
> ---
> hw/acpi_ich9.c | 13 +++++++------
> hw/lpc_ich9.c | 32 ++++++++------------------------
> hw/smbus_ich9.c | 14 ++++++++------
> 3 files changed, 23 insertions(+), 36 deletions(-)
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> index 61034d3..25c9d36 100644
> --- a/hw/acpi_ich9.c
> +++ b/hw/acpi_ich9.c
> @@ -2,6 +2,11 @@
> * ACPI implementation
> *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * This is based on acpi.c.
> *
> * This library is free software; you can redistribute it and/or
> * modify it under the terms of the GNU Lesser General Public
> @@ -14,13 +19,9 @@
> *
> * You should have received a copy of the GNU Lesser General Public
> * License along with this library; if not, see <http://www.gnu.org/licenses/>
> - */
> -/*
> - * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> - * VA Linux Systems Japan K.K.
> - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> *
> - * This is based on acpi.c.
> + * Contributions after 2012-01-13 are licensed under the terms of the
> + * GNU GPL, version 2 or (at your option) any later version.
> */
> #include "hw.h"
> #include "pc.h"
> diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c
> index 4116c50..90129db 100644
> --- a/hw/lpc_ich9.c
> +++ b/hw/lpc_ich9.c
> @@ -1,5 +1,13 @@
> /*
> + * QEMU ICH9 Emulation
> + *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2009, 2010, 2011
> + * Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * This is based on piix_pci.c, but heavily modified.
> *
> * Permission is hereby granted, free of charge, to any person obtaining a copy
> * of this software and associated documentation files (the "Software"), to deal
> @@ -19,30 +27,6 @@
> * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> * THE SOFTWARE.
> */
> -/*
> - * QEMU ICH9 Emulation
> - *
> - * Copyright (c) 2009, 2010, 2011
> - * Isaku Yamahata <yamahata at valinux co jp>
> - * VA Linux Systems Japan K.K.
> - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> - *
> - * This is based on piix_pci.c, but heavily modified.
> - *
> - * This library is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU Lesser General Public
> - * License as published by the Free Software Foundation; either
> - * version 2 of the License, or (at your option) any later version.
> - *
> - * This library is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> - * Lesser General Public License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public
> - * License along with this library; if not, see <http://www.gnu.org/licenses/>
> - */
> -
> #include "qemu-common.h"
> #include "hw.h"
> #include "range.h"
> diff --git a/hw/smbus_ich9.c b/hw/smbus_ich9.c
> index 6940583..6d31e24 100644
> --- a/hw/smbus_ich9.c
> +++ b/hw/smbus_ich9.c
> @@ -2,6 +2,11 @@
> * ACPI implementation
> *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * This is based on acpi.c, but heavily rewritten.
> *
> * This library is free software; you can redistribute it and/or
> * modify it under the terms of the GNU Lesser General Public
> @@ -14,13 +19,10 @@
> *
> * You should have received a copy of the GNU Lesser General Public
> * License along with this library; if not, see <http://www.gnu.org/licenses/>
> - */
> -/*
> - * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> - * VA Linux Systems Japan K.K.
> - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> *
> - * This is based on acpi.c, but heavily rewritten.
> + * Contributions after 2012-01-13 are licensed under the terms of the
> + * GNU GPL, version 2 or (at your option) any later version.
> + *
> */
> #include "hw.h"
> #include "pc.h"
> --
> 1.7.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses
2012-10-31 8:59 ` Michael S. Tsirkin
@ 2012-10-31 9:34 ` Isaku Yamahata
2012-10-31 9:57 ` Michael S. Tsirkin
0 siblings, 1 reply; 35+ messages in thread
From: Isaku Yamahata @ 2012-10-31 9:34 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, armbru, kraxel
Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
On Wed, Oct 31, 2012 at 10:59:18AM +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 29, 2012 at 10:11:31PM -0400, Jason Baron wrote:
> > From: Jason Baron <jbaron@redhat.com>
> >
> > Cleanup the q35/ich9 license headers.
> >
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
>
> Isaku Yamahata, could you confirm this one please?
>
> > ---
> > hw/acpi_ich9.c | 13 +++++++------
> > hw/lpc_ich9.c | 32 ++++++++------------------------
> > hw/smbus_ich9.c | 14 ++++++++------
> > 3 files changed, 23 insertions(+), 36 deletions(-)
> >
> > diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> > index 61034d3..25c9d36 100644
> > --- a/hw/acpi_ich9.c
> > +++ b/hw/acpi_ich9.c
> > @@ -2,6 +2,11 @@
> > * ACPI implementation
> > *
> > * Copyright (c) 2006 Fabrice Bellard
> > + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > + * VA Linux Systems Japan K.K.
> > + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > + *
> > + * This is based on acpi.c.
> > *
> > * This library is free software; you can redistribute it and/or
> > * modify it under the terms of the GNU Lesser General Public
> > @@ -14,13 +19,9 @@
> > *
> > * You should have received a copy of the GNU Lesser General Public
> > * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > - */
> > -/*
> > - * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > - * VA Linux Systems Japan K.K.
> > - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > *
> > - * This is based on acpi.c.
> > + * Contributions after 2012-01-13 are licensed under the terms of the
> > + * GNU GPL, version 2 or (at your option) any later version.
> > */
> > #include "hw.h"
> > #include "pc.h"
> > diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c
> > index 4116c50..90129db 100644
> > --- a/hw/lpc_ich9.c
> > +++ b/hw/lpc_ich9.c
> > @@ -1,5 +1,13 @@
> > /*
> > + * QEMU ICH9 Emulation
> > + *
> > * Copyright (c) 2006 Fabrice Bellard
> > + * Copyright (c) 2009, 2010, 2011
> > + * Isaku Yamahata <yamahata at valinux co jp>
> > + * VA Linux Systems Japan K.K.
> > + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > + *
> > + * This is based on piix_pci.c, but heavily modified.
> > *
> > * Permission is hereby granted, free of charge, to any person obtaining a copy
> > * of this software and associated documentation files (the "Software"), to deal
> > @@ -19,30 +27,6 @@
> > * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> > * THE SOFTWARE.
> > */
> > -/*
> > - * QEMU ICH9 Emulation
> > - *
> > - * Copyright (c) 2009, 2010, 2011
> > - * Isaku Yamahata <yamahata at valinux co jp>
> > - * VA Linux Systems Japan K.K.
> > - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > - *
> > - * This is based on piix_pci.c, but heavily modified.
> > - *
> > - * This library is free software; you can redistribute it and/or
> > - * modify it under the terms of the GNU Lesser General Public
> > - * License as published by the Free Software Foundation; either
> > - * version 2 of the License, or (at your option) any later version.
> > - *
> > - * This library is distributed in the hope that it will be useful,
> > - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > - * Lesser General Public License for more details.
> > - *
> > - * You should have received a copy of the GNU Lesser General Public
> > - * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > - */
> > -
> > #include "qemu-common.h"
> > #include "hw.h"
> > #include "range.h"
> > diff --git a/hw/smbus_ich9.c b/hw/smbus_ich9.c
> > index 6940583..6d31e24 100644
> > --- a/hw/smbus_ich9.c
> > +++ b/hw/smbus_ich9.c
> > @@ -2,6 +2,11 @@
> > * ACPI implementation
> > *
> > * Copyright (c) 2006 Fabrice Bellard
> > + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > + * VA Linux Systems Japan K.K.
> > + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > + *
> > + * This is based on acpi.c, but heavily rewritten.
> > *
> > * This library is free software; you can redistribute it and/or
> > * modify it under the terms of the GNU Lesser General Public
> > @@ -14,13 +19,10 @@
> > *
> > * You should have received a copy of the GNU Lesser General Public
> > * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > - */
> > -/*
> > - * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > - * VA Linux Systems Japan K.K.
> > - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > *
> > - * This is based on acpi.c, but heavily rewritten.
> > + * Contributions after 2012-01-13 are licensed under the terms of the
> > + * GNU GPL, version 2 or (at your option) any later version.
> > + *
> > */
> > #include "hw.h"
> > #include "pc.h"
> > --
> > 1.7.1
>
--
yamahata
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses
2012-10-31 9:34 ` Isaku Yamahata
@ 2012-10-31 9:57 ` Michael S. Tsirkin
0 siblings, 0 replies; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 9:57 UTC (permalink / raw)
To: Isaku Yamahata
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, armbru, kraxel
Applied, thanks.
On Wed, Oct 31, 2012 at 06:34:36PM +0900, Isaku Yamahata wrote:
> Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
>
> On Wed, Oct 31, 2012 at 10:59:18AM +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 29, 2012 at 10:11:31PM -0400, Jason Baron wrote:
> > > From: Jason Baron <jbaron@redhat.com>
> > >
> > > Cleanup the q35/ich9 license headers.
> > >
> > > Signed-off-by: Jason Baron <jbaron@redhat.com>
> >
> > Isaku Yamahata, could you confirm this one please?
> >
> > > ---
> > > hw/acpi_ich9.c | 13 +++++++------
> > > hw/lpc_ich9.c | 32 ++++++++------------------------
> > > hw/smbus_ich9.c | 14 ++++++++------
> > > 3 files changed, 23 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> > > index 61034d3..25c9d36 100644
> > > --- a/hw/acpi_ich9.c
> > > +++ b/hw/acpi_ich9.c
> > > @@ -2,6 +2,11 @@
> > > * ACPI implementation
> > > *
> > > * Copyright (c) 2006 Fabrice Bellard
> > > + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > > + * VA Linux Systems Japan K.K.
> > > + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > > + *
> > > + * This is based on acpi.c.
> > > *
> > > * This library is free software; you can redistribute it and/or
> > > * modify it under the terms of the GNU Lesser General Public
> > > @@ -14,13 +19,9 @@
> > > *
> > > * You should have received a copy of the GNU Lesser General Public
> > > * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > > - */
> > > -/*
> > > - * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > > - * VA Linux Systems Japan K.K.
> > > - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > > *
> > > - * This is based on acpi.c.
> > > + * Contributions after 2012-01-13 are licensed under the terms of the
> > > + * GNU GPL, version 2 or (at your option) any later version.
> > > */
> > > #include "hw.h"
> > > #include "pc.h"
> > > diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c
> > > index 4116c50..90129db 100644
> > > --- a/hw/lpc_ich9.c
> > > +++ b/hw/lpc_ich9.c
> > > @@ -1,5 +1,13 @@
> > > /*
> > > + * QEMU ICH9 Emulation
> > > + *
> > > * Copyright (c) 2006 Fabrice Bellard
> > > + * Copyright (c) 2009, 2010, 2011
> > > + * Isaku Yamahata <yamahata at valinux co jp>
> > > + * VA Linux Systems Japan K.K.
> > > + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > > + *
> > > + * This is based on piix_pci.c, but heavily modified.
> > > *
> > > * Permission is hereby granted, free of charge, to any person obtaining a copy
> > > * of this software and associated documentation files (the "Software"), to deal
> > > @@ -19,30 +27,6 @@
> > > * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> > > * THE SOFTWARE.
> > > */
> > > -/*
> > > - * QEMU ICH9 Emulation
> > > - *
> > > - * Copyright (c) 2009, 2010, 2011
> > > - * Isaku Yamahata <yamahata at valinux co jp>
> > > - * VA Linux Systems Japan K.K.
> > > - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > > - *
> > > - * This is based on piix_pci.c, but heavily modified.
> > > - *
> > > - * This library is free software; you can redistribute it and/or
> > > - * modify it under the terms of the GNU Lesser General Public
> > > - * License as published by the Free Software Foundation; either
> > > - * version 2 of the License, or (at your option) any later version.
> > > - *
> > > - * This library is distributed in the hope that it will be useful,
> > > - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > - * Lesser General Public License for more details.
> > > - *
> > > - * You should have received a copy of the GNU Lesser General Public
> > > - * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > > - */
> > > -
> > > #include "qemu-common.h"
> > > #include "hw.h"
> > > #include "range.h"
> > > diff --git a/hw/smbus_ich9.c b/hw/smbus_ich9.c
> > > index 6940583..6d31e24 100644
> > > --- a/hw/smbus_ich9.c
> > > +++ b/hw/smbus_ich9.c
> > > @@ -2,6 +2,11 @@
> > > * ACPI implementation
> > > *
> > > * Copyright (c) 2006 Fabrice Bellard
> > > + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > > + * VA Linux Systems Japan K.K.
> > > + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > > + *
> > > + * This is based on acpi.c, but heavily rewritten.
> > > *
> > > * This library is free software; you can redistribute it and/or
> > > * modify it under the terms of the GNU Lesser General Public
> > > @@ -14,13 +19,10 @@
> > > *
> > > * You should have received a copy of the GNU Lesser General Public
> > > * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > > - */
> > > -/*
> > > - * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > > - * VA Linux Systems Japan K.K.
> > > - * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> > > *
> > > - * This is based on acpi.c, but heavily rewritten.
> > > + * Contributions after 2012-01-13 are licensed under the terms of the
> > > + * GNU GPL, version 2 or (at your option) any later version.
> > > + *
> > > */
> > > #include "hw.h"
> > > #include "pc.h"
> > > --
> > > 1.7.1
> >
>
> --
> yamahata
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree
2012-10-30 2:11 [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Jason Baron
` (12 preceding siblings ...)
2012-10-30 2:11 ` [Qemu-devel] [PATCH v1 13/13] Fixup q35/ich9 Licenses Jason Baron
@ 2012-10-30 19:20 ` Anthony Liguori
2012-10-31 8:42 ` Michael S. Tsirkin
13 siblings, 1 reply; 35+ messages in thread
From: Anthony Liguori @ 2012-10-30 19:20 UTC (permalink / raw)
To: Jason Baron, qemu-devel
Cc: juzhang, mst, jan.kiszka, agraf, armbru, blauwirbel, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, kraxel
Jason Baron <jbaron@redhat.com> writes:
> Hi,
>
> Re-base of my previous q35 patches on top of Michael Tsirkin's pci
> tree.
I don't want this to come in through the pci tree. This is not just
another PCI device and the ramifications are pretty big since this will
become the main machine model.
> Qemu bits for q35 support, I'm posting the seabios changes separately. The
> patches require '-M q35' and -L 'seabios dir with q35 changes' on the
> qemu command line. Hopefully, we can make it the default for x86 at some future
> point when we feel comfortable with it. I'm hoping these patches can be
> included for the 1.3 soft freeze.
Q35 is sufficiently important that I think we should push for it in 1.3
regardless of freeze dates. The code is pretty close to being ready.
So let's not worry too much about merge dates and focusing on getting
the code up to the right level.
> The current patches have been tested with basic install testing and memory testing
> on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors
> by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches
> have also been reported to work with a small dsdt change on OSX 10.6 as well.
>
> I've also dropped ACPI hotplug support completely - I simply haven't gotten a
> chance to clean this up yet. Hopefully, it is ok for this to come in a bit
> later.
>
> Git trees:
>
> git://github.com/jibaron/q35-qemu.git
> git://github.com/jibaron/q35-seabios.git
>
> Major Todo Items:
>
> -add ahci migration back (need to cover more fields, but basically works)
> -add ACPI hotplug support (pcie hotplug is currently working)
Since this is coming in as experimental for 1.3, I'm not overly
concerned about missing functionality. I'm more concerned with code
structure and device modeling so let's focus on getting this right for
1.3.
Overall, the series looks pretty nice. Thanks for all of your work
here!
Regards,
Anthony Liguori
>
>
> Isaku Yamahata (3):
> pc/piix_pci: factor out smram/pam logic
> pc, pc_piix: split out pc nic initialization
> q35: Introduce q35 pc based chipset emulator
>
> Jan Kiszka (2):
> q35: Suppress SMM BIOS initialization under KVM
> q35: Add kvmclock support
>
> Jason Baron (8):
> Back out add of i21154
> blockdev: Introduce QEMUMachine->default_drive_if
> blockdev: Introduce IF_AHCI
> pc: Move ioapic_init() from pc_piix.c to pc.c
> Add a fallback bios file search, if -L fails.
> q35: automatically load the q35 dsdt table
> q35: fill in usb pci slots with -usb
> Fixup q35/ich9 Licenses
>
> blockdev.c | 23 +++-
> blockdev.h | 22 +++
> hw/Makefile.objs | 2 +-
> hw/acpi_ich9.c | 20 ++-
> hw/boards.h | 2 +-
> hw/device-hotplug.c | 2 +-
> hw/highbank.c | 2 +-
> hw/i21154.c | 113 ----------------
> hw/i21154.h | 9 --
> hw/i386/Makefile.objs | 3 +-
> hw/ich9.h | 5 +-
> hw/ide.h | 1 +
> hw/ide/core.c | 9 ++
> hw/ide/pci.c | 19 +++
> hw/ide/pci.h | 1 +
> hw/leon3.c | 1 -
> hw/lpc_ich9.c | 32 +----
> hw/mips_jazz.c | 4 +-
> hw/pam.c | 87 ++++++++++++
> hw/pam.h | 97 ++++++++++++++
> hw/pc.c | 58 ++++++++
> hw/pc.h | 7 +
> hw/pc_piix.c | 38 +-----
> hw/pc_q35.c | 354 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pc_sysfw.c | 2 +-
> hw/pci_ids.h | 2 +
> hw/piix_pci.c | 68 ++--------
> hw/puv3.c | 1 -
> hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++
> hw/q35.h | 161 ++++++++++++++++++++++
> hw/realview.c | 6 +-
> hw/smbus_ich9.c | 14 +-
> hw/spapr.c | 2 +-
> hw/sun4m.c | 24 ++--
> hw/versatilepb.c | 4 +-
> hw/vexpress.c | 4 +-
> hw/xilinx_zynq.c | 2 +-
> vl.c | 56 +++++---
> 38 files changed, 1272 insertions(+), 300 deletions(-)
> delete mode 100644 hw/i21154.c
> delete mode 100644 hw/i21154.h
> create mode 100644 hw/pam.c
> create mode 100644 hw/pam.h
> create mode 100644 hw/pc_q35.c
> create mode 100644 hw/q35.c
> create mode 100644 hw/q35.h
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree
2012-10-30 19:20 ` [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree Anthony Liguori
@ 2012-10-31 8:42 ` Michael S. Tsirkin
2012-10-31 12:55 ` Anthony Liguori
0 siblings, 1 reply; 35+ messages in thread
From: Michael S. Tsirkin @ 2012-10-31 8:42 UTC (permalink / raw)
To: Anthony Liguori
Cc: agraf, juzhang, jan.kiszka, Jason Baron, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Tue, Oct 30, 2012 at 02:20:35PM -0500, Anthony Liguori wrote:
> Jason Baron <jbaron@redhat.com> writes:
>
> > Hi,
> >
> > Re-base of my previous q35 patches on top of Michael Tsirkin's pci
> > tree.
>
> I don't want this to come in through the pci tree.
OK so you want to merge directly?
> This is not just
> another PCI device and the ramifications are pretty big since this will
> become the main machine model.
OTOH it's not going to be the main machine model in 1.3 so maybe they
are not that big, yet.
> > Qemu bits for q35 support, I'm posting the seabios changes separately. The
> > patches require '-M q35' and -L 'seabios dir with q35 changes' on the
> > qemu command line. Hopefully, we can make it the default for x86 at some future
> > point when we feel comfortable with it. I'm hoping these patches can be
> > included for the 1.3 soft freeze.
>
> Q35 is sufficiently important that I think we should push for it in 1.3
> regardless of freeze dates. The code is pretty close to being ready.
> So let's not worry too much about merge dates and focusing on getting
> the code up to the right level.
>
> > The current patches have been tested with basic install testing and memory testing
> > on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors
> > by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches
> > have also been reported to work with a small dsdt change on OSX 10.6 as well.
> >
> > I've also dropped ACPI hotplug support completely - I simply haven't gotten a
> > chance to clean this up yet. Hopefully, it is ok for this to come in a bit
> > later.
> >
> > Git trees:
> >
> > git://github.com/jibaron/q35-qemu.git
> > git://github.com/jibaron/q35-seabios.git
> >
> > Major Todo Items:
> >
> > -add ahci migration back (need to cover more fields, but basically works)
> > -add ACPI hotplug support (pcie hotplug is currently working)
>
> Since this is coming in as experimental for 1.3, I'm not overly
> concerned about missing functionality. I'm more concerned with code
> structure and device modeling so let's focus on getting this right for
> 1.3.
>
> Overall, the series looks pretty nice. Thanks for all of your work
> here!
>
> Regards,
>
> Anthony Liguori
>
> >
> >
> > Isaku Yamahata (3):
> > pc/piix_pci: factor out smram/pam logic
> > pc, pc_piix: split out pc nic initialization
> > q35: Introduce q35 pc based chipset emulator
> >
> > Jan Kiszka (2):
> > q35: Suppress SMM BIOS initialization under KVM
> > q35: Add kvmclock support
> >
> > Jason Baron (8):
> > Back out add of i21154
> > blockdev: Introduce QEMUMachine->default_drive_if
> > blockdev: Introduce IF_AHCI
> > pc: Move ioapic_init() from pc_piix.c to pc.c
> > Add a fallback bios file search, if -L fails.
> > q35: automatically load the q35 dsdt table
> > q35: fill in usb pci slots with -usb
> > Fixup q35/ich9 Licenses
> >
> > blockdev.c | 23 +++-
> > blockdev.h | 22 +++
> > hw/Makefile.objs | 2 +-
> > hw/acpi_ich9.c | 20 ++-
> > hw/boards.h | 2 +-
> > hw/device-hotplug.c | 2 +-
> > hw/highbank.c | 2 +-
> > hw/i21154.c | 113 ----------------
> > hw/i21154.h | 9 --
> > hw/i386/Makefile.objs | 3 +-
> > hw/ich9.h | 5 +-
> > hw/ide.h | 1 +
> > hw/ide/core.c | 9 ++
> > hw/ide/pci.c | 19 +++
> > hw/ide/pci.h | 1 +
> > hw/leon3.c | 1 -
> > hw/lpc_ich9.c | 32 +----
> > hw/mips_jazz.c | 4 +-
> > hw/pam.c | 87 ++++++++++++
> > hw/pam.h | 97 ++++++++++++++
> > hw/pc.c | 58 ++++++++
> > hw/pc.h | 7 +
> > hw/pc_piix.c | 38 +-----
> > hw/pc_q35.c | 354 +++++++++++++++++++++++++++++++++++++++++++++++++
> > hw/pc_sysfw.c | 2 +-
> > hw/pci_ids.h | 2 +
> > hw/piix_pci.c | 68 ++--------
> > hw/puv3.c | 1 -
> > hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++
> > hw/q35.h | 161 ++++++++++++++++++++++
> > hw/realview.c | 6 +-
> > hw/smbus_ich9.c | 14 +-
> > hw/spapr.c | 2 +-
> > hw/sun4m.c | 24 ++--
> > hw/versatilepb.c | 4 +-
> > hw/vexpress.c | 4 +-
> > hw/xilinx_zynq.c | 2 +-
> > vl.c | 56 +++++---
> > 38 files changed, 1272 insertions(+), 300 deletions(-)
> > delete mode 100644 hw/i21154.c
> > delete mode 100644 hw/i21154.h
> > create mode 100644 hw/pam.c
> > create mode 100644 hw/pam.h
> > create mode 100644 hw/pc_q35.c
> > create mode 100644 hw/q35.c
> > create mode 100644 hw/q35.h
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree
2012-10-31 8:42 ` Michael S. Tsirkin
@ 2012-10-31 12:55 ` Anthony Liguori
2012-10-31 14:42 ` Jason Baron
0 siblings, 1 reply; 35+ messages in thread
From: Anthony Liguori @ 2012-10-31 12:55 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: agraf, juzhang, jan.kiszka, Jason Baron, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
"Michael S. Tsirkin" <mst@redhat.com> writes:
> On Tue, Oct 30, 2012 at 02:20:35PM -0500, Anthony Liguori wrote:
>> Jason Baron <jbaron@redhat.com> writes:
>>
>> > Hi,
>> >
>> > Re-base of my previous q35 patches on top of Michael Tsirkin's pci
>> > tree.
>>
>> I don't want this to come in through the pci tree.
>
> OK so you want to merge directly?
Yes.
>
>> This is not just
>> another PCI device and the ramifications are pretty big since this will
>> become the main machine model.
>
> OTOH it's not going to be the main machine model in 1.3 so maybe they
> are not that big, yet.
I think it's important to avoid introducing a lot of unmodelled code
regardless of whether it's the main machine model or not.
There's plenty of time to fix it for 1.3 though so it shouldn't be a big deal.
Regards,
Anthony Liguori
>
>> > Qemu bits for q35 support, I'm posting the seabios changes separately. The
>> > patches require '-M q35' and -L 'seabios dir with q35 changes' on the
>> > qemu command line. Hopefully, we can make it the default for x86 at some future
>> > point when we feel comfortable with it. I'm hoping these patches can be
>> > included for the 1.3 soft freeze.
>>
>> Q35 is sufficiently important that I think we should push for it in 1.3
>> regardless of freeze dates. The code is pretty close to being ready.
>> So let's not worry too much about merge dates and focusing on getting
>> the code up to the right level.
>>
>> > The current patches have been tested with basic install testing and memory testing
>> > on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors
>> > by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches
>> > have also been reported to work with a small dsdt change on OSX 10.6 as well.
>> >
>> > I've also dropped ACPI hotplug support completely - I simply haven't gotten a
>> > chance to clean this up yet. Hopefully, it is ok for this to come in a bit
>> > later.
>> >
>> > Git trees:
>> >
>> > git://github.com/jibaron/q35-qemu.git
>> > git://github.com/jibaron/q35-seabios.git
>> >
>> > Major Todo Items:
>> >
>> > -add ahci migration back (need to cover more fields, but basically works)
>> > -add ACPI hotplug support (pcie hotplug is currently working)
>>
>> Since this is coming in as experimental for 1.3, I'm not overly
>> concerned about missing functionality. I'm more concerned with code
>> structure and device modeling so let's focus on getting this right for
>> 1.3.
>>
>> Overall, the series looks pretty nice. Thanks for all of your work
>> here!
>>
>> Regards,
>>
>> Anthony Liguori
>>
>> >
>> >
>> > Isaku Yamahata (3):
>> > pc/piix_pci: factor out smram/pam logic
>> > pc, pc_piix: split out pc nic initialization
>> > q35: Introduce q35 pc based chipset emulator
>> >
>> > Jan Kiszka (2):
>> > q35: Suppress SMM BIOS initialization under KVM
>> > q35: Add kvmclock support
>> >
>> > Jason Baron (8):
>> > Back out add of i21154
>> > blockdev: Introduce QEMUMachine->default_drive_if
>> > blockdev: Introduce IF_AHCI
>> > pc: Move ioapic_init() from pc_piix.c to pc.c
>> > Add a fallback bios file search, if -L fails.
>> > q35: automatically load the q35 dsdt table
>> > q35: fill in usb pci slots with -usb
>> > Fixup q35/ich9 Licenses
>> >
>> > blockdev.c | 23 +++-
>> > blockdev.h | 22 +++
>> > hw/Makefile.objs | 2 +-
>> > hw/acpi_ich9.c | 20 ++-
>> > hw/boards.h | 2 +-
>> > hw/device-hotplug.c | 2 +-
>> > hw/highbank.c | 2 +-
>> > hw/i21154.c | 113 ----------------
>> > hw/i21154.h | 9 --
>> > hw/i386/Makefile.objs | 3 +-
>> > hw/ich9.h | 5 +-
>> > hw/ide.h | 1 +
>> > hw/ide/core.c | 9 ++
>> > hw/ide/pci.c | 19 +++
>> > hw/ide/pci.h | 1 +
>> > hw/leon3.c | 1 -
>> > hw/lpc_ich9.c | 32 +----
>> > hw/mips_jazz.c | 4 +-
>> > hw/pam.c | 87 ++++++++++++
>> > hw/pam.h | 97 ++++++++++++++
>> > hw/pc.c | 58 ++++++++
>> > hw/pc.h | 7 +
>> > hw/pc_piix.c | 38 +-----
>> > hw/pc_q35.c | 354 +++++++++++++++++++++++++++++++++++++++++++++++++
>> > hw/pc_sysfw.c | 2 +-
>> > hw/pci_ids.h | 2 +
>> > hw/piix_pci.c | 68 ++--------
>> > hw/puv3.c | 1 -
>> > hw/q35.c | 315 +++++++++++++++++++++++++++++++++++++++++++
>> > hw/q35.h | 161 ++++++++++++++++++++++
>> > hw/realview.c | 6 +-
>> > hw/smbus_ich9.c | 14 +-
>> > hw/spapr.c | 2 +-
>> > hw/sun4m.c | 24 ++--
>> > hw/versatilepb.c | 4 +-
>> > hw/vexpress.c | 4 +-
>> > hw/xilinx_zynq.c | 2 +-
>> > vl.c | 56 +++++---
>> > 38 files changed, 1272 insertions(+), 300 deletions(-)
>> > delete mode 100644 hw/i21154.c
>> > delete mode 100644 hw/i21154.h
>> > create mode 100644 hw/pam.c
>> > create mode 100644 hw/pam.h
>> > create mode 100644 hw/pc_q35.c
>> > create mode 100644 hw/q35.c
>> > create mode 100644 hw/q35.h
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v1 00/13] q35 patches for pci tree
2012-10-31 12:55 ` Anthony Liguori
@ 2012-10-31 14:42 ` Jason Baron
0 siblings, 0 replies; 35+ messages in thread
From: Jason Baron @ 2012-10-31 14:42 UTC (permalink / raw)
To: Anthony Liguori
Cc: agraf, juzhang, Michael S. Tsirkin, jan.kiszka, armbru,
qemu-devel, blauwirbel, yamahata, alex.williamson, kevin, avi,
mkletzan, pbonzini, lcapitulino, afaerber, kraxel
On Wed, Oct 31, 2012 at 07:55:13AM -0500, Anthony Liguori wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
>
> > On Tue, Oct 30, 2012 at 02:20:35PM -0500, Anthony Liguori wrote:
> >> Jason Baron <jbaron@redhat.com> writes:
> >>
> >> > Hi,
> >> >
> >> > Re-base of my previous q35 patches on top of Michael Tsirkin's pci
> >> > tree.
> >>
> >> I don't want this to come in through the pci tree.
> >
> > OK so you want to merge directly?
>
> Yes.
>
> >
> >> This is not just
> >> another PCI device and the ramifications are pretty big since this will
> >> become the main machine model.
> >
> > OTOH it's not going to be the main machine model in 1.3 so maybe they
> > are not that big, yet.
>
> I think it's important to avoid introducing a lot of unmodelled code
> regardless of whether it's the main machine model or not.
>
> There's plenty of time to fix it for 1.3 though so it shouldn't be a big deal.
>
> Regards,
>
> Anthony Liguori
>
> >
I was looking at some of past pc refactoring patches, and they are
fairly involved:
Subject: [Qemu-devel] [PATCH 0/6] refactor PC machine, i440fx and piix3 to take advantage of QOM
http://lists.gnu.org/archive/html/qemu-devel/2012-03/msg04711.html
I'm not sure that level of modeling/refactoring can be safely be done in
1.3. I'm hoping you had something less invasive in mind.
It might be helpful to look at the core 'q35' data structures:
'Northbridge':
q35.h:
typedef struct GMCHPCIHost {
PCIExpressHost host;
PCIDevice *dev; //points to the GMCHPCIState
} GMCHPCIHost;
q35.h:
typedef struct GMCHPCIState {
PCIDevice d;
/*
* GMCH_PCIHost *gmch_host;
* In order to get GMCH_PCIHost
* PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
*/
MemoryRegion *ram_memory;
MemoryRegion *pci_address_space;
MemoryRegion *system_memory;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
MemoryRegion pci_hole;
MemoryRegion pci_hole_64bit;
uint8_t smm_enabled;
} GMCHPCIState;
So the memory controller is really the GMCHPCIState structure. We could
create a generic 'MemoryController' class and embed it in GMCHPCIState,
and then embed GMCHPCIState into GMCHPCIHost. Adding the PAM routines
to the 'MemoryController'.
Then when we initialize GMCHPCIHost, we can also initialize GMCHPCIState
and the 'MemoryController'. Next, set the user passed parameters and then
finishing initializing all 3 structures?
'SouthBride':
ich9.h:
typedef struct ICH9LPCState {
/* ICH9 LPC PCI to ISA bridge */
PCIDevice d;
/* (pci device, intx) -> pirq
* In real chipset case, the unused slots are never used
* as ICH9 supports only D25-D32 irq routing.
* On the other hand in qemu case, any slot/function can be
* populated
* via command line option.
* So fallback interrupt routing for any devices in any slots is
* necessary.
*/
uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
APMState apm;
ICH9LPCPMRegs pm;
uint32_t sci_level; /* track sci level */
/* 10.1 Chipset Configuration registers(Memory Space)
which is pointed by RCBA */
uint8_t chip_config[ICH9_CC_SIZE];
/* isa bus */
ISABus *isa_bus;
MemoryRegion rbca_mem;
qemu_irq *pic;
qemu_irq *ioapic;
} ICH9LPCState;
hw/smbus_ich9.c:
typedef struct ICH9SMBState {
PCIDevice dev;
PMSMBus smb;
MemoryRegion mem_bar;
} ICH9SMBState;
hw/ide/ahci.h:
typedef struct AHCIPCIState {
PCIDevice card;
AHCIState ahci;
} AHCIPCIState;
Here too, we probably could create a generic 'ICH9' device and embed the
LPC, SMB, and ahci controller in it. Initialize all the devices, set
the desired parameters, and finalize their creation.
That would still be a lot of code churn. Maybe you can be more specific
about what you're looking for?
Also, will this include refactoring i440fx/piix3?
Thanks,
-Jason
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