* [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-24 14:17 [Qemu-devel] [PATCH v12 00/14] QEMU MIPS ASE DSP support Jia Liu
@ 2012-10-24 14:17 ` Jia Liu
0 siblings, 0 replies; 13+ messages in thread
From: Jia Liu @ 2012-10-24 14:17 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
---
target-mips/dsp_helper.c | 55 ++++++++++
target-mips/helper.h | 7 ++
target-mips/translate.c | 249 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 311 insertions(+)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 86c27ec..919ff29 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3112,6 +3112,61 @@ DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
#undef DM_OPERATE
#endif
+/** DSP Bit/Manipulation Sub-class insns **/
+target_ulong helper_bitrev(target_ulong rt)
+{
+ int32_t temp;
+ uint32_t rd;
+ int i;
+
+ temp = rt & MIPSDSP_LO;
+ rd = 0;
+ for (i = 0; i < 16; i++) {
+ rd = (rd << 1) | (temp & 1);
+ temp = temp >> 1;
+ }
+
+ return (target_ulong)rd;
+}
+
+#define BIT_INSV(name, posfilter, sizefilter, ret_type) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
+ target_ulong rt) \
+{ \
+ uint32_t pos, size, msb, lsb; \
+ target_ulong filter; \
+ target_ulong temp, temprs, temprt; \
+ target_ulong dspc; \
+ \
+ dspc = env->active_tc.DSPControl; \
+ \
+ pos = dspc & posfilter; \
+ size = (dspc >> 7) & sizefilter; \
+ \
+ msb = pos + size - 1; \
+ lsb = pos; \
+ \
+ if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
+ return rt; \
+ } \
+ \
+ filter = ((int32_t)0x01 << size) - 1; \
+ filter = filter << pos; \
+ temprs = rs & filter; \
+ temprt = rt & ~filter; \
+ temp = temprs | temprt; \
+ \
+ return (target_long)(ret_type)temp; \
+}
+
+BIT_INSV(insv, 0x1F, 0x1F, int32_t);
+#ifdef TARGET_MIPS64
+BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
+#endif
+
+#undef BIT_INSV
+
+
#undef MIPSDSP_LHI
#undef MIPSDSP_LLO
#undef MIPSDSP_HI
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 6a6ca99..31475a2 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -617,4 +617,11 @@ DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env)
DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env)
#endif
+/* DSP Bit/Manipulation Sub-class insns */
+DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
+DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl)
+#if defined(TARGET_MIPS64)
+DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl);
+#endif
+
#include "def-helper.h"
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7c90941..63109f4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -343,6 +343,11 @@ enum {
#if defined(TARGET_MIPS64)
OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
#endif
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
+#if defined(TARGET_MIPS64)
+ OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
+#endif
};
/* BSHFL opcodes */
@@ -450,6 +455,12 @@ enum {
OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
};
#define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -518,6 +529,12 @@ enum {
OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
};
+#define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
+};
+
#if defined(TARGET_MIPS64)
#define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum {
@@ -539,6 +556,13 @@ enum {
OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
};
#endif
@@ -592,6 +616,14 @@ enum {
#endif
#if defined(TARGET_MIPS64)
+#define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
+};
+#endif
+
+#if defined(TARGET_MIPS64)
#define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum {
/* MIPS DSP Multiply Sub-class insns */
@@ -13598,6 +13630,149 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
}
+static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
+ uint32_t op1, uint32_t op2,
+ int ret, int val)
+{
+ const char *opn = "mipsdsp Bit/ Manipulation";
+ int16_t imm;
+ TCGv t0;
+ TCGv val_t;
+
+ if (ret == 0) {
+ /* Treat as NOP. */
+ MIPS_DEBUG("NOP");
+ return;
+ }
+
+ t0 = tcg_temp_new();
+ val_t = tcg_temp_new();
+ gen_load_gpr(val_t, val);
+
+ switch (op1) {
+ case OPC_ABSQ_S_PH_DSP:
+ switch (op2) {
+ case OPC_BITREV:
+ check_dsp(ctx);
+ gen_helper_bitrev(cpu_gpr[ret], val_t);
+ break;
+ case OPC_REPL_QB:
+ check_dsp(ctx);
+ {
+ target_long result;
+ imm = (ctx->opcode >> 16) & 0xFF;
+ result = (uint32_t)imm << 24 |
+ (uint32_t)imm << 16 |
+ (uint32_t)imm << 8 |
+ (uint32_t)imm;
+ result = (int32_t)result;
+ tcg_gen_movi_tl(cpu_gpr[ret], result);
+ }
+ break;
+ case OPC_REPLV_QB:
+ check_dsp(ctx);
+ tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ break;
+ case OPC_REPL_PH:
+ check_dsp(ctx);
+ {
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ tcg_gen_movi_tl(cpu_gpr[ret], \
+ (target_long)((int32_t)imm << 16 | \
+ (uint32_t)(uint16_t)imm));
+ }
+ break;
+ case OPC_REPLV_PH:
+ check_dsp(ctx);
+ tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ break;
+ }
+ break;
+#ifdef TARGET_MIPS64
+ case OPC_ABSQ_S_QH_DSP:
+ switch (op2) {
+ case OPC_REPL_OB:
+ check_dsp(ctx);
+ {
+ target_long temp;
+
+ imm = (ctx->opcode >> 16) & 0xFF;
+ temp = ((uint64_t)imm << 8) | (uint64_t)imm;
+ temp = (temp << 16) | temp;
+ temp = (temp << 32) | temp;
+ tcg_gen_movi_tl(cpu_gpr[ret], temp);
+ break;
+ }
+ case OPC_REPL_PW:
+ check_dsp(ctx);
+ {
+ target_long temp;
+
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ imm = (int16_t)(imm << 6) >> 6;
+ temp = ((target_long)imm << 32) \
+ | ((target_long)imm & 0xFFFFFFFF);
+ tcg_gen_movi_tl(cpu_gpr[ret], temp);
+ break;
+ }
+ case OPC_REPL_QH:
+ check_dsp(ctx);
+ {
+ target_long temp;
+
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ imm = (int16_t)(imm << 6) >> 6;
+
+ temp = ((uint64_t)(uint16_t)imm << 48) |
+ ((uint64_t)(uint16_t)imm << 32) |
+ ((uint64_t)(uint16_t)imm << 16) |
+ (uint64_t)(uint16_t)imm;
+ tcg_gen_movi_tl(cpu_gpr[ret], temp);
+ break;
+ }
+ case OPC_REPLV_OB:
+ check_dsp(ctx);
+ tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ break;
+ case OPC_REPLV_PW:
+ check_dsp(ctx);
+ tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ break;
+ case OPC_REPLV_QH:
+ check_dsp(ctx);
+ tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ break;
+ }
+ break;
+#endif
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(val_t);
+
+ (void)opn; /* avoid a compiler warning */
+ MIPS_DEBUG("%s", opn);
+}
+
/* End MIPSDSP functions. */
static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
@@ -14024,6 +14199,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
case OPC_PRECEU_PH_QBRA:
gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
break;
+ case OPC_BITREV:
+ case OPC_REPL_QB:
+ case OPC_REPLV_QB:
+ case OPC_REPL_PH:
+ case OPC_REPLV_PH:
+ gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt);
+ break;
default:
MIPS_INVAL("MASK ABSQ_S.PH");
generate_exception(ctx, EXCP_RI);
@@ -14124,6 +14306,37 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
break;
}
break;
+ case OPC_INSV_DSP:
+ op2 = MASK_INSV(ctx->opcode);
+ switch (op2) {
+ case OPC_INSV:
+ check_dsp(ctx);
+ {
+ TCGv t0, t1;
+
+ if (rt == 0) {
+ MIPS_DEBUG("NOP");
+ break;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+
+ gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ break;
+ }
+ default: /* Invalid */
+ MIPS_INVAL("MASK INSV");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+ break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
@@ -14165,6 +14378,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
case OPC_ABSQ_S_QH:
gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
break;
+ case OPC_REPL_OB:
+ case OPC_REPL_PW:
+ case OPC_REPL_QH:
+ case OPC_REPLV_OB:
+ case OPC_REPLV_PW:
+ case OPC_REPLV_QH:
+ gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt);
+ break;
default: /* Invalid */
MIPS_INVAL("MASK ABSQ_S.QH");
generate_exception(ctx, EXCP_RI);
@@ -14271,6 +14492,34 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
break;
}
break;
+ case OPC_DINSV_DSP:
+ op2 = MASK_INSV(ctx->opcode);
+ switch (op2) {
+ case OPC_DINSV:
+ {
+ TCGv t0, t1;
+
+ if (rt == 0) {
+ MIPS_DEBUG("NOP");
+ break;
+ }
+ check_dsp(ctx);
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+
+ gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
+ break;
+ }
+ default: /* Invalid */
+ MIPS_INVAL("MASK DINSV");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+ break;
case OPC_SHLL_OB_DSP:
gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
break;
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
@ 2012-10-27 22:58 Jovanovic, Petar
2012-10-29 12:36 ` Jia Liu
0 siblings, 1 reply; 13+ messages in thread
From: Jovanovic, Petar @ 2012-10-27 22:58 UTC (permalink / raw)
To: proljc@gmail.com; +Cc: qemu-devel@nongnu.org
+ case OPC_REPL_PH:
+ check_dsp(ctx);
+ {
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ tcg_gen_movi_tl(cpu_gpr[ret], \
+ (target_long)((int32_t)imm << 16 | \
+ (uint32_t)(uint16_t)imm));
+ }
10-bit integer in REPL.PH is signed, so this code will not work for negative
values.
You need to sign-extend it, e.g. something like this:
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ if (imm & (1 << 9)) {
+ /* imm is negative, sign-extend it to 16 bits. */
+ imm |= 0xFC00;
+ }
+ tcg_gen_movi_tl(cpu_gpr[ret], \
+ (target_long)((int32_t)imm << 16 | \
+ (uint32_t)(uint16_t)imm));
As far as I can see, the test cases for REPL.PH in
tests/tcg/mips/mips32-dsp/repl_ph.c cover only positive values.
Make sure you include test cases for negative values as well.
Petar
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-27 22:58 [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions Jovanovic, Petar
@ 2012-10-29 12:36 ` Jia Liu
2012-10-29 13:40 ` Jovanovic, Petar
2012-10-30 14:51 ` Peter Maydell
0 siblings, 2 replies; 13+ messages in thread
From: Jia Liu @ 2012-10-29 12:36 UTC (permalink / raw)
To: Jovanovic, Petar; +Cc: qemu-devel@nongnu.org
Hi Petar,
On Sun, Oct 28, 2012 at 6:58 AM, Jovanovic, Petar <petarj@mips.com> wrote:
> + case OPC_REPL_PH:
> + check_dsp(ctx);
> + {
> + imm = (ctx->opcode >> 16) & 0x03FF;
> + tcg_gen_movi_tl(cpu_gpr[ret], \
> + (target_long)((int32_t)imm << 16 | \
> + (uint32_t)(uint16_t)imm));
> + }
>
> 10-bit integer in REPL.PH is signed, so this code will not work for negative
> values.
> You need to sign-extend it, e.g. something like this:
>
> + imm = (ctx->opcode >> 16) & 0x03FF;
> + if (imm & (1 << 9)) {
> + /* imm is negative, sign-extend it to 16 bits. */
> + imm |= 0xFC00;
> + }
> + tcg_gen_movi_tl(cpu_gpr[ret], \
> + (target_long)((int32_t)imm << 16 | \
> + (uint32_t)(uint16_t)imm));
>
> As far as I can see, the test cases for REPL.PH in
> tests/tcg/mips/mips32-dsp/repl_ph.c cover only positive values.
> Make sure you include test cases for negative values as well.
>
> Petar
New code:
case OPC_REPL_PH:
check_dsp(ctx);
{
imm = (ctx->opcode >> 16) & 0x03FF;
imm = (int16_t)(imm << 6) >> 6;
tcg_gen_movi_tl(cpu_gpr[ret], \
(target_long)(int32_t)((int32_t)imm << 16 | \
(uint32_t)(uint16_t)imm));
}
break;
And the new test:
#include<stdio.h>
#include<assert.h>
int main()
{
int rd, result;
result = 0x01BF01BF;
__asm
("repl.ph %0, 0x1BF\n\t"
: "=r"(rd)
);
assert(rd == result);
result = 0xFFFFFFFF;
__asm
("repl.ph %0, -1\n\t"
: "=r"(rd)
);
assert(rd == result);
return 0;
}
is it OK?
And the other tests have be fixed.
Regards,
Jia.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-29 12:36 ` Jia Liu
@ 2012-10-29 13:40 ` Jovanovic, Petar
2012-10-30 14:34 ` Jia Liu
2012-10-30 14:51 ` Peter Maydell
1 sibling, 1 reply; 13+ messages in thread
From: Jovanovic, Petar @ 2012-10-29 13:40 UTC (permalink / raw)
To: Jia Liu; +Cc: qemu-devel@nongnu.org
Hi Jia,
> imm = (int16_t)(imm << 6) >> 6;
result of a bitwise shift of a signed type and a negative vlaue is
implementation-defined, so you can not rely on that.
Regards,
Petar
________________________________________
From: Jia Liu [proljc@gmail.com]
Sent: Monday, October 29, 2012 1:36 PM
To: Jovanovic, Petar
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
Hi Petar,
On Sun, Oct 28, 2012 at 6:58 AM, Jovanovic, Petar <petarj@mips.com> wrote:
> + case OPC_REPL_PH:
> + check_dsp(ctx);
> + {
> + imm = (ctx->opcode >> 16) & 0x03FF;
> + tcg_gen_movi_tl(cpu_gpr[ret], \
> + (target_long)((int32_t)imm << 16 | \
> + (uint32_t)(uint16_t)imm));
> + }
>
> 10-bit integer in REPL.PH is signed, so this code will not work for negative
> values.
> You need to sign-extend it, e.g. something like this:
>
> + imm = (ctx->opcode >> 16) & 0x03FF;
> + if (imm & (1 << 9)) {
> + /* imm is negative, sign-extend it to 16 bits. */
> + imm |= 0xFC00;
> + }
> + tcg_gen_movi_tl(cpu_gpr[ret], \
> + (target_long)((int32_t)imm << 16 | \
> + (uint32_t)(uint16_t)imm));
>
> As far as I can see, the test cases for REPL.PH in
> tests/tcg/mips/mips32-dsp/repl_ph.c cover only positive values.
> Make sure you include test cases for negative values as well.
>
> Petar
New code:
case OPC_REPL_PH:
check_dsp(ctx);
{
imm = (ctx->opcode >> 16) & 0x03FF;
imm = (int16_t)(imm << 6) >> 6;
tcg_gen_movi_tl(cpu_gpr[ret], \
(target_long)(int32_t)((int32_t)imm << 16 | \
(uint32_t)(uint16_t)imm));
}
break;
And the new test:
#include<stdio.h>
#include<assert.h>
int main()
{
int rd, result;
result = 0x01BF01BF;
__asm
("repl.ph %0, 0x1BF\n\t"
: "=r"(rd)
);
assert(rd == result);
result = 0xFFFFFFFF;
__asm
("repl.ph %0, -1\n\t"
: "=r"(rd)
);
assert(rd == result);
return 0;
}
is it OK?
And the other tests have be fixed.
Regards,
Jia.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-29 13:40 ` Jovanovic, Petar
@ 2012-10-30 14:34 ` Jia Liu
2012-10-30 14:44 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Jia Liu @ 2012-10-30 14:34 UTC (permalink / raw)
To: Jovanovic, Petar; +Cc: qemu-devel@nongnu.org
Hi Petar,
On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
> Hi Jia,
>
>> imm = (int16_t)(imm << 6) >> 6;
>
> result of a bitwise shift of a signed type and a negative vlaue is
> implementation-defined, so you can not rely on that.
>
I think it will take a 10bits signed value sign extend into 16bits
signed value, and I've tested it with negative values, it working
well.
> Regards,
> Petar
Regards,
Jia.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-30 14:34 ` Jia Liu
@ 2012-10-30 14:44 ` Peter Maydell
2012-10-31 5:26 ` Richard Henderson
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2012-10-30 14:44 UTC (permalink / raw)
To: Jia Liu; +Cc: Jovanovic, Petar, qemu-devel@nongnu.org
On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
>>> imm = (int16_t)(imm << 6) >> 6;
>>
>> result of a bitwise shift of a signed type and a negative vlaue is
>> implementation-defined, so you can not rely on that.
>>
>
> I think it will take a 10bits signed value sign extend into 16bits
> signed value, and I've tested it with negative values, it working
> well.
You cannot rely on the behaviour of a specific compiler implementation
as evidence that a piece of code is correct. C has a standard which
defines what is and is not valid.
Having said that, right shift of negative signed integers is one of
those bits of implementation defined behaviour which we allow ourselves
to rely on in QEMU because all the platforms we care about behave
that way. (That integers are 2s complement representation is another.)
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-29 12:36 ` Jia Liu
2012-10-29 13:40 ` Jovanovic, Petar
@ 2012-10-30 14:51 ` Peter Maydell
1 sibling, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2012-10-30 14:51 UTC (permalink / raw)
To: Jia Liu; +Cc: Jovanovic, Petar, qemu-devel@nongnu.org
On 29 October 2012 13:36, Jia Liu <proljc@gmail.com> wrote:
> case OPC_REPL_PH:
> check_dsp(ctx);
> {
> imm = (ctx->opcode >> 16) & 0x03FF;
> imm = (int16_t)(imm << 6) >> 6;
> tcg_gen_movi_tl(cpu_gpr[ret], \
> (target_long)(int32_t)((int32_t)imm << 16 | \
> (uint32_t)(uint16_t)imm));
> }
> break;
This code is using rather more casts than it needs to.
Also, if you kept the scope of 'imm' to the local blocks
where it is used then it would be easy to see at a glance
what type it is (in this case int16_t) and thus which
of these casts are needed. (It would also mean you could
use the sensible type for the job -- for instance
in the OPC_REPL_QB case a 32 bit type would let you
avoid a lot of the casts your current code has.)
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-30 14:44 ` Peter Maydell
@ 2012-10-31 5:26 ` Richard Henderson
2012-10-31 13:29 ` Jia Liu
0 siblings, 1 reply; 13+ messages in thread
From: Richard Henderson @ 2012-10-31 5:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: Jovanovic, Petar, Jia Liu, qemu-devel@nongnu.org
On 2012-10-31 01:44, Peter Maydell wrote:
> On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
>> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
>>>> imm = (int16_t)(imm << 6) >> 6;
>>>
>>> result of a bitwise shift of a signed type and a negative vlaue is
>>> implementation-defined, so you can not rely on that.
>>>
>>
>> I think it will take a 10bits signed value sign extend into 16bits
>> signed value, and I've tested it with negative values, it working
>> well.
>
> You cannot rely on the behaviour of a specific compiler implementation
> as evidence that a piece of code is correct. C has a standard which
> defines what is and is not valid.
Indeed. The only portable way is
val = ((val & (sign | (sign - 1))) ^ sign) - sign
with all unsigned types, and "sign" set to the sign bit.
>
> Having said that, right shift of negative signed integers is one of
> those bits of implementation defined behaviour which we allow ourselves
> to rely on in QEMU because all the platforms we care about behave
> that way. (That integers are 2s complement representation is another.)
Also very true. I don't like seeing the code in question though.
We've several implementations of sign-extend-to-N-bits functions
throughout qemu; we ought to unify them.
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-31 5:26 ` Richard Henderson
@ 2012-10-31 13:29 ` Jia Liu
2012-10-31 19:20 ` Aurelien Jarno
0 siblings, 1 reply; 13+ messages in thread
From: Jia Liu @ 2012-10-31 13:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: Peter Maydell, Jovanovic, Petar, qemu-devel@nongnu.org
Hi Richard Peter Jovanovic and Aurelien,
On Wed, Oct 31, 2012 at 1:26 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 2012-10-31 01:44, Peter Maydell wrote:
>> On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
>>> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
>>>>> imm = (int16_t)(imm << 6) >> 6;
>>>>
>>>> result of a bitwise shift of a signed type and a negative vlaue is
>>>> implementation-defined, so you can not rely on that.
>>>>
>>>
>>> I think it will take a 10bits signed value sign extend into 16bits
>>> signed value, and I've tested it with negative values, it working
>>> well.
>>
>> You cannot rely on the behaviour of a specific compiler implementation
>> as evidence that a piece of code is correct. C has a standard which
>> defines what is and is not valid.
>
> Indeed. The only portable way is
>
> val = ((val & (sign | (sign - 1))) ^ sign) - sign
>
> with all unsigned types, and "sign" set to the sign bit.
>
Thank you very much for the code.
Is this time OK?
static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
uint32_t op1, uint32_t op2,
int ret, int val)
{
const char *opn = "mipsdsp Bit/ Manipulation";
TCGv t0;
TCGv val_t;
if (ret == 0) {
/* Treat as NOP. */
MIPS_DEBUG("NOP");
return;
}
t0 = tcg_temp_new();
val_t = tcg_temp_new();
gen_load_gpr(val_t, val);
#define SIGN_EXTEND10_16(val, sign) \
val = (((val & (sign | (sign - 1))) ^ sign) - sign)
switch (op1) {
case OPC_ABSQ_S_PH_DSP:
switch (op2) {
case OPC_BITREV:
check_dsp(ctx);
gen_helper_bitrev(cpu_gpr[ret], val_t);
break;
case OPC_REPL_QB:
check_dsp(ctx);
{
uint32_t imm;
target_long result;
imm = (ctx->opcode >> 16) & 0xFF;
result = imm << 24 | imm << 16 | imm << 8 | imm;
result = (int32_t)result;
tcg_gen_movi_tl(cpu_gpr[ret], result);
}
break;
case OPC_REPLV_QB:
check_dsp(ctx);
tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
break;
case OPC_REPL_PH:
check_dsp(ctx);
{
uint16_t imm;
imm = (ctx->opcode >> 16) & 0x03FF;
SIGN_EXTEND10_16(imm, 0x200);
tcg_gen_movi_tl(cpu_gpr[ret],
(target_long)(int32_t)
((uint32_t)imm << 16 | imm));
}
break;
case OPC_REPLV_PH:
check_dsp(ctx);
tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
break;
}
break;
#ifdef TARGET_MIPS64
case OPC_ABSQ_S_QH_DSP:
switch (op2) {
case OPC_REPL_OB:
check_dsp(ctx);
{
target_ulong imm;
imm = (ctx->opcode >> 16) & 0xFF;
imm = (imm << 8) | imm;
imm = (imm << 16) | imm;
imm = (imm << 32) | imm;
tcg_gen_movi_tl(cpu_gpr[ret], imm);
break;
}
case OPC_REPL_PW:
check_dsp(ctx);
{
target_long imm;
imm = (ctx->opcode >> 16) & 0x03FF;
SIGN_EXTEND10_16(imm, 0x200);
tcg_gen_movi_tl(cpu_gpr[ret],
(imm << 32) | (imm & 0xFFFFFFFF));
break;
}
case OPC_REPL_QH:
check_dsp(ctx);
{
target_ulong imm;
imm = (ctx->opcode >> 16) & 0x03FF;
SIGN_EXTEND10_16(imm, 0x200);
imm = imm & 0xFFFF;
imm = (imm << 48) | (imm << 32) | (imm << 16) | imm;
tcg_gen_movi_tl(cpu_gpr[ret], imm);
break;
}
case OPC_REPLV_OB:
check_dsp(ctx);
tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
break;
case OPC_REPLV_PW:
check_dsp(ctx);
tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
break;
case OPC_REPLV_QH:
check_dsp(ctx);
tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
break;
}
break;
#endif
}
#undef SIGN_EXTEND10_16
tcg_temp_free(t0);
tcg_temp_free(val_t);
(void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s", opn);
}
>>
>> Having said that, right shift of negative signed integers is one of
>> those bits of implementation defined behaviour which we allow ourselves
>> to rely on in QEMU because all the platforms we care about behave
>> that way. (That integers are 2s complement representation is another.)
>
> Also very true. I don't like seeing the code in question though.
> We've several implementations of sign-extend-to-N-bits functions
> throughout qemu; we ought to unify them.
>
>
> r~
Regards,
Jia.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-31 13:29 ` Jia Liu
@ 2012-10-31 19:20 ` Aurelien Jarno
2012-11-01 0:34 ` Jia Liu
0 siblings, 1 reply; 13+ messages in thread
From: Aurelien Jarno @ 2012-10-31 19:20 UTC (permalink / raw)
To: Jia Liu
Cc: Peter Maydell, Jovanovic, Petar, qemu-devel@nongnu.org,
Richard Henderson
On Wed, Oct 31, 2012 at 09:29:30PM +0800, Jia Liu wrote:
> Hi Richard Peter Jovanovic and Aurelien,
>
> On Wed, Oct 31, 2012 at 1:26 PM, Richard Henderson <rth@twiddle.net> wrote:
> > On 2012-10-31 01:44, Peter Maydell wrote:
> >> On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
> >>> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
> >>>>> imm = (int16_t)(imm << 6) >> 6;
> >>>>
> >>>> result of a bitwise shift of a signed type and a negative vlaue is
> >>>> implementation-defined, so you can not rely on that.
> >>>>
> >>>
> >>> I think it will take a 10bits signed value sign extend into 16bits
> >>> signed value, and I've tested it with negative values, it working
> >>> well.
> >>
> >> You cannot rely on the behaviour of a specific compiler implementation
> >> as evidence that a piece of code is correct. C has a standard which
> >> defines what is and is not valid.
> >
> > Indeed. The only portable way is
> >
> > val = ((val & (sign | (sign - 1))) ^ sign) - sign
> >
> > with all unsigned types, and "sign" set to the sign bit.
> >
>
> Thank you very much for the code.
>
> Is this time OK?
As said by Peter, I don't think the code should be modified, the
previous code was fine.
> static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
> uint32_t op1, uint32_t op2,
> int ret, int val)
> {
> const char *opn = "mipsdsp Bit/ Manipulation";
> TCGv t0;
> TCGv val_t;
>
> if (ret == 0) {
> /* Treat as NOP. */
> MIPS_DEBUG("NOP");
> return;
> }
>
> t0 = tcg_temp_new();
> val_t = tcg_temp_new();
> gen_load_gpr(val_t, val);
>
> #define SIGN_EXTEND10_16(val, sign) \
> val = (((val & (sign | (sign - 1))) ^ sign) - sign)
>
> switch (op1) {
> case OPC_ABSQ_S_PH_DSP:
> switch (op2) {
> case OPC_BITREV:
> check_dsp(ctx);
> gen_helper_bitrev(cpu_gpr[ret], val_t);
> break;
> case OPC_REPL_QB:
> check_dsp(ctx);
> {
> uint32_t imm;
> target_long result;
>
> imm = (ctx->opcode >> 16) & 0xFF;
> result = imm << 24 | imm << 16 | imm << 8 | imm;
> result = (int32_t)result;
> tcg_gen_movi_tl(cpu_gpr[ret], result);
> }
> break;
> case OPC_REPLV_QB:
> check_dsp(ctx);
> tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
> break;
> case OPC_REPL_PH:
> check_dsp(ctx);
> {
> uint16_t imm;
> imm = (ctx->opcode >> 16) & 0x03FF;
> SIGN_EXTEND10_16(imm, 0x200);
> tcg_gen_movi_tl(cpu_gpr[ret],
> (target_long)(int32_t)
> ((uint32_t)imm << 16 | imm));
> }
> break;
> case OPC_REPLV_PH:
> check_dsp(ctx);
> tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
> break;
> }
> break;
> #ifdef TARGET_MIPS64
> case OPC_ABSQ_S_QH_DSP:
> switch (op2) {
> case OPC_REPL_OB:
> check_dsp(ctx);
> {
> target_ulong imm;
>
> imm = (ctx->opcode >> 16) & 0xFF;
> imm = (imm << 8) | imm;
> imm = (imm << 16) | imm;
> imm = (imm << 32) | imm;
> tcg_gen_movi_tl(cpu_gpr[ret], imm);
> break;
> }
> case OPC_REPL_PW:
> check_dsp(ctx);
> {
> target_long imm;
>
> imm = (ctx->opcode >> 16) & 0x03FF;
> SIGN_EXTEND10_16(imm, 0x200);
> tcg_gen_movi_tl(cpu_gpr[ret],
> (imm << 32) | (imm & 0xFFFFFFFF));
> break;
> }
> case OPC_REPL_QH:
> check_dsp(ctx);
> {
> target_ulong imm;
>
> imm = (ctx->opcode >> 16) & 0x03FF;
> SIGN_EXTEND10_16(imm, 0x200);
>
> imm = imm & 0xFFFF;
> imm = (imm << 48) | (imm << 32) | (imm << 16) | imm;
> tcg_gen_movi_tl(cpu_gpr[ret], imm);
> break;
> }
> case OPC_REPLV_OB:
> check_dsp(ctx);
> tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> break;
> case OPC_REPLV_PW:
> check_dsp(ctx);
> tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> break;
> case OPC_REPLV_QH:
> check_dsp(ctx);
> tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
> tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
> break;
> }
> break;
> #endif
> }
>
> #undef SIGN_EXTEND10_16
> tcg_temp_free(t0);
> tcg_temp_free(val_t);
>
> (void)opn; /* avoid a compiler warning */
> MIPS_DEBUG("%s", opn);
> }
>
>
> >>
> >> Having said that, right shift of negative signed integers is one of
> >> those bits of implementation defined behaviour which we allow ourselves
> >> to rely on in QEMU because all the platforms we care about behave
> >> that way. (That integers are 2s complement representation is another.)
> >
> > Also very true. I don't like seeing the code in question though.
> > We've several implementations of sign-extend-to-N-bits functions
> > throughout qemu; we ought to unify them.
> >
> >
> > r~
>
> Regards,
> Jia.
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-10-31 19:20 ` Aurelien Jarno
@ 2012-11-01 0:34 ` Jia Liu
2012-11-06 3:50 ` Jovanovic, Petar
0 siblings, 1 reply; 13+ messages in thread
From: Jia Liu @ 2012-11-01 0:34 UTC (permalink / raw)
To: Aurelien Jarno
Cc: Peter Maydell, Jovanovic, Petar, qemu-devel@nongnu.org,
Richard Henderson
Hi Aurelien,
On Thu, Nov 1, 2012 at 3:20 AM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Wed, Oct 31, 2012 at 09:29:30PM +0800, Jia Liu wrote:
>>
>> Is this time OK?
>
> As said by Peter, I don't think the code should be modified, the
> previous code was fine.
>
You mean my v12 09/14 is OK? It is a good news to me:D
>>
>> Regards,
>> Jia.
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
Regards,
Jia.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-11-01 0:34 ` Jia Liu
@ 2012-11-06 3:50 ` Jovanovic, Petar
2012-11-06 7:40 ` Aurelien Jarno
0 siblings, 1 reply; 13+ messages in thread
From: Jovanovic, Petar @ 2012-11-06 3:50 UTC (permalink / raw)
To: Jia Liu, Aurelien Jarno
Cc: Peter Maydell, qemu-devel@nongnu.org, Richard Henderson
Since the change has been committed as-is, who will be sending fixes for OPC_REPL_PH and other cases?
Jia, will you do that?
Regards,
Petar
________________________________________
From: Jia Liu [proljc@gmail.com]
Sent: Thursday, November 01, 2012 1:34 AM
To: Aurelien Jarno
Cc: Richard Henderson; Peter Maydell; Jovanovic, Petar; qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
Hi Aurelien,
On Thu, Nov 1, 2012 at 3:20 AM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Wed, Oct 31, 2012 at 09:29:30PM +0800, Jia Liu wrote:
>>
>> Is this time OK?
>
> As said by Peter, I don't think the code should be modified, the
> previous code was fine.
>
You mean my v12 09/14 is OK? It is a good news to me:D
>>
>> Regards,
>> Jia.
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
Regards,
Jia.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions
2012-11-06 3:50 ` Jovanovic, Petar
@ 2012-11-06 7:40 ` Aurelien Jarno
0 siblings, 0 replies; 13+ messages in thread
From: Aurelien Jarno @ 2012-11-06 7:40 UTC (permalink / raw)
To: Jovanovic, Petar
Cc: qemu-devel@nongnu.org, Peter Maydell, Jia Liu, Richard Henderson
On Tue, Nov 06, 2012 at 03:50:08AM +0000, Jovanovic, Petar wrote:
> Since the change has been committed as-is, who will be sending fixes for OPC_REPL_PH and other cases?
> Jia, will you do that?
>
I am working on a patch series fixing and cleaning DSP support, it will
include this fix. I hope to post it before the end of the week.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2012-11-06 7:40 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2012-10-27 22:58 [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions Jovanovic, Petar
2012-10-29 12:36 ` Jia Liu
2012-10-29 13:40 ` Jovanovic, Petar
2012-10-30 14:34 ` Jia Liu
2012-10-30 14:44 ` Peter Maydell
2012-10-31 5:26 ` Richard Henderson
2012-10-31 13:29 ` Jia Liu
2012-10-31 19:20 ` Aurelien Jarno
2012-11-01 0:34 ` Jia Liu
2012-11-06 3:50 ` Jovanovic, Petar
2012-11-06 7:40 ` Aurelien Jarno
2012-10-30 14:51 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2012-10-24 14:17 [Qemu-devel] [PATCH v12 00/14] QEMU MIPS ASE DSP support Jia Liu
2012-10-24 14:17 ` [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions Jia Liu
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