From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYous-0006kI-Gp for qemu-devel@nongnu.org; Wed, 14 Nov 2012 21:10:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TYoup-0006xh-8d for qemu-devel@nongnu.org; Wed, 14 Nov 2012 21:10:54 -0500 Received: from mx1.redhat.com ([209.132.183.28]:52580) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYouo-0006xY-G8 for qemu-devel@nongnu.org; Wed, 14 Nov 2012 21:10:50 -0500 Date: Thu, 15 Nov 2012 03:10:39 +0100 From: Igor Mammedov Message-ID: <20121115031039.78898b07@thinkpad.mammed.net> In-Reply-To: <1352917734-13213-2-git-send-email-ehabkost@redhat.com> References: <1352917734-13213-1-git-send-email-ehabkost@redhat.com> <1352917734-13213-2-git-send-email-ehabkost@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/3] target-i386: cpu: name new CPUID bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost Cc: Anthony Liguori , boris.ostrovsky@amd.com, osp@andrep.de, qemu-devel@nongnu.org, donald.d.dugger@intel.com On Wed, 14 Nov 2012 16:28:52 -0200 Eduardo Habkost wrote: > From: Andre Przywara > > Update QEMU's knowledge of CPUID bit names. This allows to > enable/disable those new features on QEMU's command line when > using KVM and prepares future feature enablement in QEMU. > > This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB, > FSGSBASE, BMI1, AVX2, BMI2, ERMS, PCID, InvPCID, RTM, RDSeed and ADX. > > Sources where the AMD BKDG for Family 15h/Model 10h, Intel Software Developer > Manual, and the Linux kernel for the leaf 7 bits. > > Signed-off-by: Andre Przywara > Signed-off-by: Boris Ostrovsky > [ehabkost: added CPUID_EXT_PCID] > [ehabkost: edited commit message] > [ehabkost: rebased against latest qemu.git master] > Signed-off-by: Eduardo Habkost > --- > Cc: boris.ostrovsky@amd.com, osp@andrep.de > Cc: donald.d.dugger@intel.com > > target-i386/cpu.c | 12 ++++++------ > target-i386/cpu.h | 22 ++++++++++++++++++++++ > 2 files changed, 28 insertions(+), 6 deletions(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index e1db639..f896e0c 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -66,7 +66,7 @@ static const char *ext_feature_name[] = { > NULL, "pcid", "dca", "sse4.1|sse4_1", > "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", > "tsc-deadline", "aes", "xsave", "osxsave", > - "avx", NULL, NULL, "hypervisor", > + "avx", "f16c", "rdrand", "hypervisor", > }; > /* Feature names that are already defined on feature_name[] but are set on > * CPUID[8000_0001].EDX on AMD CPUs don't have their names on > @@ -87,10 +87,10 @@ static const char *ext3_feature_name[] = { > "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, > "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", > "3dnowprefetch", "osvw", "ibs", "xop", > - "skinit", "wdt", NULL, NULL, > - "fma4", NULL, "cvt16", "nodeid_msr", > - NULL, NULL, NULL, NULL, > - NULL, NULL, NULL, NULL, > + "skinit", "wdt", NULL, "lwp", > + "fma4", "tce", NULL, "nodeid_msr", > + NULL, "tbm", "topoext", "perfctr_core", > + "perfctr_nb", NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > }; > > @@ -119,7 +119,7 @@ static const char *svm_feature_name[] = { > static const char *cpuid_7_0_ebx_feature_name[] = { > "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep", > "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL, > - NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL, > + NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, > NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, > }; > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index cdc59dc..90ef1ff 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -403,9 +403,11 @@ > #define CPUID_EXT_TM2 (1 << 8) > #define CPUID_EXT_SSSE3 (1 << 9) > #define CPUID_EXT_CID (1 << 10) > +#define CPUID_EXT_FMA (1 << 12) > #define CPUID_EXT_CX16 (1 << 13) > #define CPUID_EXT_XTPR (1 << 14) > #define CPUID_EXT_PDCM (1 << 15) > +#define CPUID_EXT_PCID (1 << 17) > #define CPUID_EXT_DCA (1 << 18) > #define CPUID_EXT_SSE41 (1 << 19) > #define CPUID_EXT_SSE42 (1 << 20) > @@ -417,6 +419,8 @@ > #define CPUID_EXT_XSAVE (1 << 26) > #define CPUID_EXT_OSXSAVE (1 << 27) > #define CPUID_EXT_AVX (1 << 28) > +#define CPUID_EXT_F16C (1 << 29) > +#define CPUID_EXT_RDRAND (1 << 30) > #define CPUID_EXT_HYPERVISOR (1 << 31) > > #define CPUID_EXT2_FPU (1 << 0) > @@ -472,7 +476,15 @@ > #define CPUID_EXT3_IBS (1 << 10) > #define CPUID_EXT3_XOP (1 << 11) > #define CPUID_EXT3_SKINIT (1 << 12) > +#define CPUID_EXT3_WDT (1 << 13) > +#define CPUID_EXT3_LWP (1 << 15) > #define CPUID_EXT3_FMA4 (1 << 16) > +#define CPUID_EXT3_TCE (1 << 17) > +#define CPUID_EXT3_NODEID (1 << 19) > +#define CPUID_EXT3_TBM (1 << 21) > +#define CPUID_EXT3_TOPOEXT (1 << 22) > +#define CPUID_EXT3_PERFCORE (1 << 23) > +#define CPUID_EXT3_PERFNB (1 << 24) > > #define CPUID_SVM_NPT (1 << 0) > #define CPUID_SVM_LBRV (1 << 1) > @@ -485,7 +497,17 @@ > #define CPUID_SVM_PAUSEFILTER (1 << 10) > #define CPUID_SVM_PFTHRESHOLD (1 << 12) > > +#define CPUID_7_0_EBX_FSGSBASE (1 << 0) > +#define CPUID_7_0_EBX_BMI1 (1 << 3) > +#define CPUID_7_0_EBX_HLE (1 << 4) > +#define CPUID_7_0_EBX_AVX2 (1 << 5) > #define CPUID_7_0_EBX_SMEP (1 << 7) > +#define CPUID_7_0_EBX_BMI2 (1 << 8) > +#define CPUID_7_0_EBX_ERMS (1 << 9) > +#define CPUID_7_0_EBX_INVPCID (1 << 10) > +#define CPUID_7_0_EBX_RTM (1 << 11) > +#define CPUID_7_0_EBX_RDSEED (1 << 18) > +#define CPUID_7_0_EBX_ADX (1 << 19) > #define CPUID_7_0_EBX_SMAP (1 << 20) > > #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ > -- > 1.7.11.7 > > Reviewed-By: Igor Mammedov -- Regards, Igor