[Qemu-devel] [PATCH 0/3] Opteron_G5 and Haswell CPU models

[Qemu-devel] [PATCH 0/3] Opteron_G5 and Haswell CPU models

[Eduardo Habkost]

I'm resending the patches sent by Boris Ostrovsky previously, as it has to be
rebased against latest qemu.git, and to add a new Haswell CPU model too.

Andre Przywara (2):
  target-i386: cpu: name new CPUID bits
  target-i386: cpu: add new Opteron CPU model

Eduardo Habkost (1):
  target-i386: add Haswell CPU model

 target-i386/cpu.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
 target-i386/cpu.h | 22 +++++++++++++++++
 2 files changed, 89 insertions(+), 6 deletions(-)

-- 
1.7.11.7

[Qemu-devel] [PATCH 1/3] target-i386: cpu: name new CPUID bits

[Eduardo Habkost]

From: Andre Przywara <osp@andrep.de>

Update QEMU's knowledge of CPUID bit names. This allows to
enable/disable those new features on QEMU's command line when
using KVM and prepares future feature enablement in QEMU.

This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,
FSGSBASE, BMI1, AVX2, BMI2, ERMS, PCID, InvPCID, RTM, RDSeed and ADX.

Sources where the AMD BKDG for Family 15h/Model 10h, Intel Software Developer
Manual, and the Linux kernel for the leaf 7 bits.

Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
[ehabkost: added CPUID_EXT_PCID]
[ehabkost: edited commit message]
[ehabkost: rebased against latest qemu.git master]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Cc: boris.ostrovsky@amd.com, osp@andrep.de
Cc: donald.d.dugger@intel.com

 target-i386/cpu.c | 12 ++++++------
 target-i386/cpu.h | 22 ++++++++++++++++++++++
 2 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index e1db639..f896e0c 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -66,7 +66,7 @@ static const char *ext_feature_name[] = {
     NULL, "pcid", "dca", "sse4.1|sse4_1",
     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
     "tsc-deadline", "aes", "xsave", "osxsave",
-    "avx", NULL, NULL, "hypervisor",
+    "avx", "f16c", "rdrand", "hypervisor",
 };
 /* Feature names that are already defined on feature_name[] but are set on
  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
@@ -87,10 +87,10 @@ static const char *ext3_feature_name[] = {
     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
     "3dnowprefetch", "osvw", "ibs", "xop",
-    "skinit", "wdt", NULL, NULL,
-    "fma4", NULL, "cvt16", "nodeid_msr",
-    NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL,
+    "skinit", "wdt", NULL, "lwp",
+    "fma4", "tce", NULL, "nodeid_msr",
+    NULL, "tbm", "topoext", "perfctr_core",
+    "perfctr_nb", NULL, NULL, NULL,
     NULL, NULL, NULL, NULL,
 };
 
@@ -119,7 +119,7 @@ static const char *svm_feature_name[] = {
 static const char *cpuid_7_0_ebx_feature_name[] = {
     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
+    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 };
 
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index cdc59dc..90ef1ff 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -403,9 +403,11 @@
 #define CPUID_EXT_TM2      (1 << 8)
 #define CPUID_EXT_SSSE3    (1 << 9)
 #define CPUID_EXT_CID      (1 << 10)
+#define CPUID_EXT_FMA      (1 << 12)
 #define CPUID_EXT_CX16     (1 << 13)
 #define CPUID_EXT_XTPR     (1 << 14)
 #define CPUID_EXT_PDCM     (1 << 15)
+#define CPUID_EXT_PCID     (1 << 17)
 #define CPUID_EXT_DCA      (1 << 18)
 #define CPUID_EXT_SSE41    (1 << 19)
 #define CPUID_EXT_SSE42    (1 << 20)
@@ -417,6 +419,8 @@
 #define CPUID_EXT_XSAVE    (1 << 26)
 #define CPUID_EXT_OSXSAVE  (1 << 27)
 #define CPUID_EXT_AVX      (1 << 28)
+#define CPUID_EXT_F16C     (1 << 29)
+#define CPUID_EXT_RDRAND   (1 << 30)
 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 
 #define CPUID_EXT2_FPU     (1 << 0)
@@ -472,7 +476,15 @@
 #define CPUID_EXT3_IBS     (1 << 10)
 #define CPUID_EXT3_XOP     (1 << 11)
 #define CPUID_EXT3_SKINIT  (1 << 12)
+#define CPUID_EXT3_WDT     (1 << 13)
+#define CPUID_EXT3_LWP     (1 << 15)
 #define CPUID_EXT3_FMA4    (1 << 16)
+#define CPUID_EXT3_TCE     (1 << 17)
+#define CPUID_EXT3_NODEID  (1 << 19)
+#define CPUID_EXT3_TBM     (1 << 21)
+#define CPUID_EXT3_TOPOEXT (1 << 22)
+#define CPUID_EXT3_PERFCORE (1 << 23)
+#define CPUID_EXT3_PERFNB  (1 << 24)
 
 #define CPUID_SVM_NPT          (1 << 0)
 #define CPUID_SVM_LBRV         (1 << 1)
@@ -485,7 +497,17 @@
 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 
+#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
+#define CPUID_7_0_EBX_BMI1     (1 << 3)
+#define CPUID_7_0_EBX_HLE      (1 << 4)
+#define CPUID_7_0_EBX_AVX2     (1 << 5)
 #define CPUID_7_0_EBX_SMEP     (1 << 7)
+#define CPUID_7_0_EBX_BMI2     (1 << 8)
+#define CPUID_7_0_EBX_ERMS     (1 << 9)
+#define CPUID_7_0_EBX_INVPCID  (1 << 10)
+#define CPUID_7_0_EBX_RTM      (1 << 11)
+#define CPUID_7_0_EBX_RDSEED   (1 << 18)
+#define CPUID_7_0_EBX_ADX      (1 << 19)
 #define CPUID_7_0_EBX_SMAP     (1 << 20)
 
 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
-- 
1.7.11.7

Re: [Qemu-devel] [PATCH 1/3] target-i386: cpu: name new CPUID bits

[Igor Mammedov]

On Wed, 14 Nov 2012 16:28:52 -0200
Eduardo Habkost <ehabkost@redhat.com> wrote:

> From: Andre Przywara <osp@andrep.de>
> 
> Update QEMU's knowledge of CPUID bit names. This allows to
> enable/disable those new features on QEMU's command line when
> using KVM and prepares future feature enablement in QEMU.
> 
> This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,
> FSGSBASE, BMI1, AVX2, BMI2, ERMS, PCID, InvPCID, RTM, RDSeed and ADX.
> 
> Sources where the AMD BKDG for Family 15h/Model 10h, Intel Software Developer
> Manual, and the Linux kernel for the leaf 7 bits.
> 
> Signed-off-by: Andre Przywara <osp@andrep.de>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
> [ehabkost: added CPUID_EXT_PCID]
> [ehabkost: edited commit message]
> [ehabkost: rebased against latest qemu.git master]
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Cc: boris.ostrovsky@amd.com, osp@andrep.de
> Cc: donald.d.dugger@intel.com
> 
>  target-i386/cpu.c | 12 ++++++------
>  target-i386/cpu.h | 22 ++++++++++++++++++++++
>  2 files changed, 28 insertions(+), 6 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index e1db639..f896e0c 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -66,7 +66,7 @@ static const char *ext_feature_name[] = {
>      NULL, "pcid", "dca", "sse4.1|sse4_1",
>      "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
>      "tsc-deadline", "aes", "xsave", "osxsave",
> -    "avx", NULL, NULL, "hypervisor",
> +    "avx", "f16c", "rdrand", "hypervisor",
>  };
>  /* Feature names that are already defined on feature_name[] but are set on
>   * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
> @@ -87,10 +87,10 @@ static const char *ext3_feature_name[] = {
>      "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
>      "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
>      "3dnowprefetch", "osvw", "ibs", "xop",
> -    "skinit", "wdt", NULL, NULL,
> -    "fma4", NULL, "cvt16", "nodeid_msr",
> -    NULL, NULL, NULL, NULL,
> -    NULL, NULL, NULL, NULL,
> +    "skinit", "wdt", NULL, "lwp",
> +    "fma4", "tce", NULL, "nodeid_msr",
> +    NULL, "tbm", "topoext", "perfctr_core",
> +    "perfctr_nb", NULL, NULL, NULL,
>      NULL, NULL, NULL, NULL,
>  };
>  
> @@ -119,7 +119,7 @@ static const char *svm_feature_name[] = {
>  static const char *cpuid_7_0_ebx_feature_name[] = {
>      "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
>      "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
> -    NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
> +    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
>      NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
>  };
>  
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index cdc59dc..90ef1ff 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -403,9 +403,11 @@
>  #define CPUID_EXT_TM2      (1 << 8)
>  #define CPUID_EXT_SSSE3    (1 << 9)
>  #define CPUID_EXT_CID      (1 << 10)
> +#define CPUID_EXT_FMA      (1 << 12)
>  #define CPUID_EXT_CX16     (1 << 13)
>  #define CPUID_EXT_XTPR     (1 << 14)
>  #define CPUID_EXT_PDCM     (1 << 15)
> +#define CPUID_EXT_PCID     (1 << 17)
>  #define CPUID_EXT_DCA      (1 << 18)
>  #define CPUID_EXT_SSE41    (1 << 19)
>  #define CPUID_EXT_SSE42    (1 << 20)
> @@ -417,6 +419,8 @@
>  #define CPUID_EXT_XSAVE    (1 << 26)
>  #define CPUID_EXT_OSXSAVE  (1 << 27)
>  #define CPUID_EXT_AVX      (1 << 28)
> +#define CPUID_EXT_F16C     (1 << 29)
> +#define CPUID_EXT_RDRAND   (1 << 30)
>  #define CPUID_EXT_HYPERVISOR  (1 << 31)
>  
>  #define CPUID_EXT2_FPU     (1 << 0)
> @@ -472,7 +476,15 @@
>  #define CPUID_EXT3_IBS     (1 << 10)
>  #define CPUID_EXT3_XOP     (1 << 11)
>  #define CPUID_EXT3_SKINIT  (1 << 12)
> +#define CPUID_EXT3_WDT     (1 << 13)
> +#define CPUID_EXT3_LWP     (1 << 15)
>  #define CPUID_EXT3_FMA4    (1 << 16)
> +#define CPUID_EXT3_TCE     (1 << 17)
> +#define CPUID_EXT3_NODEID  (1 << 19)
> +#define CPUID_EXT3_TBM     (1 << 21)
> +#define CPUID_EXT3_TOPOEXT (1 << 22)
> +#define CPUID_EXT3_PERFCORE (1 << 23)
> +#define CPUID_EXT3_PERFNB  (1 << 24)
>  
>  #define CPUID_SVM_NPT          (1 << 0)
>  #define CPUID_SVM_LBRV         (1 << 1)
> @@ -485,7 +497,17 @@
>  #define CPUID_SVM_PAUSEFILTER  (1 << 10)
>  #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
>  
> +#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
> +#define CPUID_7_0_EBX_BMI1     (1 << 3)
> +#define CPUID_7_0_EBX_HLE      (1 << 4)
> +#define CPUID_7_0_EBX_AVX2     (1 << 5)
>  #define CPUID_7_0_EBX_SMEP     (1 << 7)
> +#define CPUID_7_0_EBX_BMI2     (1 << 8)
> +#define CPUID_7_0_EBX_ERMS     (1 << 9)
> +#define CPUID_7_0_EBX_INVPCID  (1 << 10)
> +#define CPUID_7_0_EBX_RTM      (1 << 11)
> +#define CPUID_7_0_EBX_RDSEED   (1 << 18)
> +#define CPUID_7_0_EBX_ADX      (1 << 19)
>  #define CPUID_7_0_EBX_SMAP     (1 << 20)
>  
>  #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
> -- 
> 1.7.11.7
> 
> 
Reviewed-By: Igor Mammedov <imammedo@redhat.com>

-- 
Regards,
  Igor

[Qemu-devel] [PATCH 2/3] target-i386: cpu: add new Opteron CPU model

[Eduardo Habkost]

From: Andre Przywara <osp@andrep.de>

Add a new base CPU model called Opteron_G5 to model the latest
Opteron CPUs. This increases the model value and model numbers and
adds TBM, F16C and FMA over the latest G4 model.

Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
[ehabkost: edited commit message]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Cc: boris.ostrovsky@amd.com, osp@andrep.de

 target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index f896e0c..c3aff4f 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -756,6 +756,38 @@ static x86_def_t builtin_x86_defs[] = {
         .xlevel = 0x8000001A,
         .model_id = "AMD Opteron 62xx class CPU",
     },
+    {
+        .name = "Opteron_G5",
+        .level = 0xd,
+        .vendor1 = CPUID_VENDOR_AMD_1,
+        .vendor2 = CPUID_VENDOR_AMD_2,
+        .vendor3 = CPUID_VENDOR_AMD_3,
+        .family = 21,
+        .model = 2,
+        .stepping = 0,
+        .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+             CPUID_DE | CPUID_FP87,
+        .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
+             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
+             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
+             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
+             CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
+             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
+             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
+             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
+             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
+             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
+        .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
+             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
+             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
+             CPUID_EXT3_LAHF_LM,
+        .xlevel = 0x8000001A,
+        .model_id = "AMD Opteron 63xx class CPU",
+    },
 };
 
 #ifdef CONFIG_KVM
-- 
1.7.11.7

Re: [Qemu-devel] [PATCH 2/3] target-i386: cpu: add new Opteron CPU model

[Igor Mammedov]

On Wed, 14 Nov 2012 16:28:53 -0200
Eduardo Habkost <ehabkost@redhat.com> wrote:

> From: Andre Przywara <osp@andrep.de>
> 
> Add a new base CPU model called Opteron_G5 to model the latest
> Opteron CPUs. This increases the model value and model numbers and
> adds TBM, F16C and FMA over the latest G4 model.
> 
> Signed-off-by: Andre Przywara <osp@andrep.de>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
> [ehabkost: edited commit message]
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Cc: boris.ostrovsky@amd.com, osp@andrep.de
> 
>  target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index f896e0c..c3aff4f 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -756,6 +756,38 @@ static x86_def_t builtin_x86_defs[] = {
>          .xlevel = 0x8000001A,
>          .model_id = "AMD Opteron 62xx class CPU",
>      },
> +    {
> +        .name = "Opteron_G5",
> +        .level = 0xd,
> +        .vendor1 = CPUID_VENDOR_AMD_1,
> +        .vendor2 = CPUID_VENDOR_AMD_2,
> +        .vendor3 = CPUID_VENDOR_AMD_3,
> +        .family = 21,
> +        .model = 2,
> +        .stepping = 0,
> +        .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> +             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
> +             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> +             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> +             CPUID_DE | CPUID_FP87,
> +        .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
> +             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> +             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
> +             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> +        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
> +             CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> +             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
> +             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
> +             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
> +             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
> +             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
> +        .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
> +             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
> +             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
> +             CPUID_EXT3_LAHF_LM,
> +        .xlevel = 0x8000001A,
> +        .model_id = "AMD Opteron 63xx class CPU",
> +    },
>  };
>  
>  #ifdef CONFIG_KVM
> -- 
> 1.7.11.7
> 
> 
Reviewed-By: Igor Mammedov <imammedo@redhat.com>

-- 
Regards,
  Igor

[Qemu-devel] [PATCH 3/3] target-i386: add Haswell CPU model

[Eduardo Habkost]

Features added to the model, in relation to SandyBridge:

fma       CPUID[1].ECX[12]
pcid      CPUID[1].ECX[17]
movbe     CPUID[1].ECX[22]
fsgsbase  CPUID[EAX=7,ECX=0].EBX[0]
bmi1      CPUID[EAX=7,ECX=0].EBX[3]
hle       CPUID[EAX=7,ECX=0].EBX[4]
avx2      CPUID[EAX=7,ECX=0].EBX[5]
smep      CPUID[EAX=7,ECX=0].EBX[7]
bmi2      CPUID[EAX=7,ECX=0].EBX[8]
erms      CPUID[EAX=7,ECX=0].EBX[9]
invpcid   CPUID[EAX=7,ECX=0].EBX[10]
rtm       CPUID[EAX=7,ECX=0].EBX[11]

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Cc: donald.d.dugger@intel.com

 target-i386/cpu.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index c3aff4f..64c3491 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -647,6 +647,35 @@ static x86_def_t builtin_x86_defs[] = {
         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
     },
     {
+        .name = "Haswell",
+        .level = 0xd,
+        .vendor1 = CPUID_VENDOR_INTEL_1,
+        .vendor2 = CPUID_VENDOR_INTEL_2,
+        .vendor3 = CPUID_VENDOR_INTEL_3,
+        .family = 6,
+        .model = 60,
+        .stepping = 1,
+        .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+             CPUID_PGE | CPUID_MTRR | CPUID_APIC | CPUID_CX8 |
+             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+             CPUID_DE | CPUID_FP87,
+        .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+             CPUID_EXT_PCID,
+        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .ext3_features = CPUID_EXT3_LAHF_LM,
+        .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+            CPUID_7_0_EBX_RTM,
+        .xlevel = 0x8000000A,
+        .model_id = "Intel Core Processor (Haswell)",
+    },
+    {
         .name = "Opteron_G1",
         .level = 5,
         .vendor1 = CPUID_VENDOR_AMD_1,
-- 
1.7.11.7

Re: [Qemu-devel] [PATCH 3/3] target-i386: add Haswell CPU model

[Igor Mammedov]

On Wed, 14 Nov 2012 16:28:54 -0200
Eduardo Habkost <ehabkost@redhat.com> wrote:

> Features added to the model, in relation to SandyBridge:
> 
> fma       CPUID[1].ECX[12]
> pcid      CPUID[1].ECX[17]
> movbe     CPUID[1].ECX[22]
> fsgsbase  CPUID[EAX=7,ECX=0].EBX[0]
> bmi1      CPUID[EAX=7,ECX=0].EBX[3]
> hle       CPUID[EAX=7,ECX=0].EBX[4]
> avx2      CPUID[EAX=7,ECX=0].EBX[5]
> smep      CPUID[EAX=7,ECX=0].EBX[7]
> bmi2      CPUID[EAX=7,ECX=0].EBX[8]
> erms      CPUID[EAX=7,ECX=0].EBX[9]
> invpcid   CPUID[EAX=7,ECX=0].EBX[10]
> rtm       CPUID[EAX=7,ECX=0].EBX[11]
> 
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Cc: donald.d.dugger@intel.com
> 
>  target-i386/cpu.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index c3aff4f..64c3491 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -647,6 +647,35 @@ static x86_def_t builtin_x86_defs[] = {
>          .model_id = "Intel Xeon E312xx (Sandy Bridge)",
>      },
>      {
> +        .name = "Haswell",
> +        .level = 0xd,
> +        .vendor1 = CPUID_VENDOR_INTEL_1,
> +        .vendor2 = CPUID_VENDOR_INTEL_2,
> +        .vendor3 = CPUID_VENDOR_INTEL_3,
> +        .family = 6,
> +        .model = 60,
> +        .stepping = 1,
> +        .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> +             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
> +             CPUID_PGE | CPUID_MTRR | CPUID_APIC | CPUID_CX8 |
> +             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> +             CPUID_DE | CPUID_FP87,
> +        .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> +             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> +             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> +             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
> +             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
> +             CPUID_EXT_PCID,
> +        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
> +        .ext3_features = CPUID_EXT3_LAHF_LM,
> +        .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> +            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> +            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
> +            CPUID_7_0_EBX_RTM,
> +        .xlevel = 0x8000000A,
> +        .model_id = "Intel Core Processor (Haswell)",
> +    },
> +    {
>          .name = "Opteron_G1",
>          .level = 5,
>          .vendor1 = CPUID_VENDOR_AMD_1,
> -- 
> 1.7.11.7
> 
> 
Reviewed-By: Igor Mammedov <imammedo@redhat.com>

-- 
Regards,
  Igor

Re: [Qemu-devel] [PATCH 0/3] Opteron_G5 and Haswell CPU models

[Eduardo Habkost]

Andreas, I just noticed that I didn't CC you in this series, and I don't
know if this is something that would go through your tree. Should I CC
you on x86-specific series unrelated to QOM, like this one?

On Wed, Nov 14, 2012 at 04:28:51PM -0200, Eduardo Habkost wrote:
> I'm resending the patches sent by Boris Ostrovsky previously, as it has to be
> rebased against latest qemu.git, and to add a new Haswell CPU model too.
> 
> Andre Przywara (2):
>   target-i386: cpu: name new CPUID bits
>   target-i386: cpu: add new Opteron CPU model
> 
> Eduardo Habkost (1):
>   target-i386: add Haswell CPU model
> 
>  target-i386/cpu.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
>  target-i386/cpu.h | 22 +++++++++++++++++
>  2 files changed, 89 insertions(+), 6 deletions(-)
> 
> -- 
> 1.7.11.7
> 
> 

-- 
Eduardo

Re: [Qemu-devel] [PATCH 0/3] Opteron_G5 and Haswell CPU models

[Andreas Färber]

Am 14.11.2012 21:29, schrieb Eduardo Habkost:
> Andreas, I just noticed that I didn't CC you in this series, and I don't
> know if this is something that would go through your tree. Should I CC
> you on x86-specific series unrelated to QOM, like this one?

If I get cc'ed or notice and they're trivial or there's review, I will
pick x86 CPU patches up that would fall back to Anthony. If they touch
on KVM though, I expect them to go through (or be ack'ed by) Marcelo.

Andreas

P.S. Let's not over-do the inter-Sob change log, in all fairness to the
author. :)

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