From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYzt5-00010h-H7 for qemu-devel@nongnu.org; Thu, 15 Nov 2012 08:53:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TYzt2-0006kA-4B for qemu-devel@nongnu.org; Thu, 15 Nov 2012 08:53:47 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:59257) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYzt1-0006i5-TF for qemu-devel@nongnu.org; Thu, 15 Nov 2012 08:53:44 -0500 Date: Thu, 15 Nov 2012 14:53:36 +0100 From: Aurelien Jarno Message-ID: <20121115135336.GA20668@ohm.aurel32.net> References: <1352903901-8797-1-git-send-email-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Johnson, Eric" Cc: "qemu-devel@nongnu.org" On Wed, Nov 14, 2012 at 07:45:02PM +0000, Johnson, Eric wrote: > > -----Original Message----- > > From: qemu-devel-bounces+ericj=mips.com@nongnu.org [mailto:qemu-devel- > > bounces+ericj=mips.com@nongnu.org] On Behalf Of Aurelien Jarno > > Sent: Wednesday, November 14, 2012 6:38 AM > > To: qemu-devel@nongnu.org > > Cc: Aurelien Jarno > > Subject: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin > > > > According to the MIPS Malta Developement Platform User's Manual, the > > i8259 interrupt controller is supposed to be connected to the hardware > > IRQ0, and the CBUS UART to the hardware interrupt 2. > > > > In QEMU they are both connected to hardware interrupt 0, the CBUS UART > > interrupt being wrong. This patch fixes that. It should be noted that > > the irq array in QEMU includes the software interrupts, hence > > env->irq[2] is the first hardware interrupt. > > > > Cc: Ralf Baechle > > Signed-off-by: Aurelien Jarno > > --- > > hw/mips_malta.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/hw/mips_malta.c b/hw/mips_malta.c > > index 0571d58..4d2464a 100644 > > --- a/hw/mips_malta.c > > +++ b/hw/mips_malta.c > > @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) > > be = 0; > > #endif > > /* FPGA */ > > - malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], > > serial_hds[2]); > > + /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 > > */ > > + malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], > > serial_hds[2]); > > > > /* Load firmware in flash / BIOS. */ > > dinfo = drive_get(IF_PFLASH, 0, fl_idx); > > -- > > 1.7.10.4 > > > > I double checked with a Malta expert here. He verified that the CBUS UART is connected to the HW2 interrupt pin. > > Reviewed-by: Eric Johnson > Thanks for the review, I have applied the patch. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net