From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([208.118.235.92]:33909)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <stefanha@gmail.com>) id 1TZMOd-0004EV-UO
	for qemu-devel@nongnu.org; Fri, 16 Nov 2012 08:55:54 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <stefanha@gmail.com>) id 1TZMOa-0004XI-Le
	for qemu-devel@nongnu.org; Fri, 16 Nov 2012 08:55:51 -0500
Date: Fri, 16 Nov 2012 14:55:45 +0100
From: Stefan Hajnoczi <stefanha@gmail.com>
Message-ID: <20121116135545.GD31927@stefanha-thinkpad.redhat.com>
References: <20121116020552.GA48755@cs.nctu.edu.tw>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <20121116020552.GA48755@cs.nctu.edu.tw>
Subject: Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] target-mips: Clean up
 microMIPS32 major opcode
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: =?utf-8?B?6Zmz6Z+L5Lu7IChXZWktUmVuIENoZW4p?= <chenwj@iis.sinica.edu.tw>
Cc: qemu-trivial@nongnu.org, Jia Liu <proljc@gmail.com>, qemu-devel@nongnu.org, "Johnson, Eric" <ericj@mips.com>

On Fri, Nov 16, 2012 at 10:05:52AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> Hi all,
> 
>   I check MIPS microMIPS manual [1], and found the major opcode might be
> wrong. I add a comment to explicitly indicate what manual I am refering
> to, and according that manual I remove microMIPS32 major opcodes 0x1f.
> As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order
> MIPS ISA level or new revision of this microMIPS architecture. Quote
> from Johnson, they are belong MIPS64 [2].
> 
>   Please review, thanks.
> 
> [1] http://www.mips.com/products/architectures/micromips/#specifications
> 
>     MIPS Architecture for Programmers Volume II-B:
>       The microMIPS32 Instruction Set (Revision 3.05)
> 
>     MD00582-2B-microMIPS-AFP-03.05.pdf
> 
> [2] http://www.mips.com/products/architectures/mips64/
> 
>     MIPS Architecture For Programmers
>       Volume II-A: The MIPS64 Instruction Set
> 
>     MD00087-2B-MIPS64BIS-AFP-03.51.pdf
> 
> Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
> ---
>  target-mips/translate.c |   24 +++++++++++++++++-------
>  1 files changed, 17 insertions(+), 7 deletions(-)

Please send this through Aurelian as maintainer for target-mips/.  The
discussion on previous the thread show this isn't qemu-trivial material
:).

Stefan