From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcEt9-0006yb-Bd for qemu-devel@nongnu.org; Sat, 24 Nov 2012 07:31:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TcEt7-0002sl-Ot for qemu-devel@nongnu.org; Sat, 24 Nov 2012 07:31:15 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:48383) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcEt7-0002sg-IO for qemu-devel@nongnu.org; Sat, 24 Nov 2012 07:31:13 -0500 Date: Sat, 24 Nov 2012 13:31:03 +0100 From: Aurelien Jarno Message-ID: <20121124123103.GD4016@ohm.aurel32.net> References: <20121121060441.GA34107@cs.nctu.edu.tw> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20121121060441.GA34107@cs.nctu.edu.tw> Subject: Re: [Qemu-devel] [PATCH v3] target-mips: Clean up microMIPS32 major opcode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?utf-8?B?6Zmz6Z+L5Lu7IChXZWktUmVuIENoZW4p?= Cc: Jia Liu , "qemu-devel@nongnu.org" , "Johnson, Eric" On Wed, Nov 21, 2012 at 02:04:41PM +0800, 陳韋任 (Wei-Ren Chen) wrote: > I check MIPS microMIPS manual [1], and found the major opcode might > be wrong. I add a comment to explicitly indicate what manual I am refering > to, and according that manual I remove microMIPS32 major opcodes 0x1f. > As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order > MIPS ISA level or new revision of this microMIPS architecture. Quote > from Johnson, they are belong MIPS64 [2]. > > [1] http://www.mips.com/products/architectures/micromips/#specifications > > MIPS Architecture for Programmers Volume II-B: > The microMIPS32 Instruction Set (Revision 3.05) > > MD00582-2B-microMIPS-AFP-03.05.pdf > > [2] http://www.mips.com/products/architectures/mips64/ > > MIPS Architecture For Programmers > Volume II-A: The MIPS64 Instruction Set > > MD00087-2B-MIPS64BIS-AFP-03.51.pdf > > Signed-off-by: Chen Wei-Ren > --- > > v3: Correct commit message formatting. > > v2: Remove POOL48A only. The other three opcode are belong MIPS64. > > target-mips/translate.c | 24 +++++++++++++++++------- > 1 file changed, 17 insertions(+), 7 deletions(-) Thanks, applied. > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 8b438f8..7fe8d83 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -10239,9 +10239,19 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, > return n_bytes; > } > > -/* microMIPS extension to MIPS32 */ > +/* microMIPS extension to MIPS32/MIPS64 */ > > -/* microMIPS32 major opcodes */ > +/* > + * microMIPS32/microMIPS64 major opcodes > + * > + * 1. MIPS Architecture for Programmers Volume II-B: > + * The microMIPS32 Instruction Set (Revision 3.05) > + * > + * Table 6.2 microMIPS32 Encoding of Major Opcode Field > + * > + * 2. MIPS Architecture For Programmers Volume II-A: > + * The MIPS64 Instruction Set (Revision 3.51) > + */ > > enum { > POOL32A = 0x00, > @@ -10268,9 +10278,10 @@ enum { > POOL16D = 0x13, > ORI32 = 0x14, > POOL32F = 0x15, > - POOL32S = 0x16, > - DADDIU32 = 0x17, > + POOL32S = 0x16, /* MIPS64 */ > + DADDIU32 = 0x17, /* MIPS64 */ > > + /* 0x1f is reserved */ > POOL32C = 0x18, > LWGP16 = 0x19, > LW16 = 0x1a, > @@ -10278,7 +10289,6 @@ enum { > XORI32 = 0x1c, > JALS32 = 0x1d, > ADDIUPC = 0x1e, > - POOL48A = 0x1f, > > /* 0x20 is reserved */ > RES_20 = 0x20, > @@ -10307,8 +10317,8 @@ enum { > B16 = 0x33, > ANDI32 = 0x34, > J32 = 0x35, > - SD32 = 0x36, > - LD32 = 0x37, > + SD32 = 0x36, /* MIPS64 */ > + LD32 = 0x37, /* MIPS64 */ > > /* 0x38 and 0x39 are reserved */ > RES_38 = 0x38, > -- > 1.7.12.3 > > > -- > Wei-Ren Chen (陳韋任) > Computer Systems Lab, Institute of Information Science, > Academia Sinica, Taiwan (R.O.C.) > Tel:886-2-2788-3799 #1667 > Homepage: http://people.cs.nctu.edu.tw/~chenwj > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net