* [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV
@ 2012-11-26 15:13 Petar Jovanovic
2012-12-05 19:45 ` Johnson, Eric
2012-12-06 8:10 ` Aurelien Jarno
0 siblings, 2 replies; 3+ messages in thread
From: Petar Jovanovic @ 2012-11-26 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: petarj, aurelien
From: Petar Jovanovic <petarj@mips.com>
Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.
Signed-off-by: Petar Jovanovic <petarj@mips.com>
---
target-mips/dsp_helper.c | 2 +-
tests/tcg/mips/mips32-dsp/insv.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index e7949c2..fda5f04 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
\
filter = ((int32_t)0x01 << size) - 1; \
filter = filter << pos; \
- temprs = rs & filter; \
+ temprs = (rs << pos) & filter; \
temprt = rt & ~filter; \
temp = temprs | temprt; \
\
diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c
index 7e3b047..243b007 100644
--- a/tests/tcg/mips/mips32-dsp/insv.c
+++ b/tests/tcg/mips/mips32-dsp/insv.c
@@ -10,7 +10,7 @@ int main()
dsp = 0x305;
rt = 0x12345678;
rs = 0x87654321;
- result = 0x12345338;
+ result = 0x12345438;
__asm
("wrdsp %2, 0x03\n\t"
"insv %0, %1\n\t"
--
1.7.5.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV
2012-11-26 15:13 [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV Petar Jovanovic
@ 2012-12-05 19:45 ` Johnson, Eric
2012-12-06 8:10 ` Aurelien Jarno
1 sibling, 0 replies; 3+ messages in thread
From: Johnson, Eric @ 2012-12-05 19:45 UTC (permalink / raw)
To: Jovanovic, Petar, qemu-devel@nongnu.org; +Cc: aurelien@aurel32.net
> -----Original Message-----
> From: qemu-devel-bounces+ericj=mips.com@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips.com@nongnu.org] On Behalf Of Petar Jovanovic
> Sent: Monday, November 26, 2012 7:13 AM
> To: qemu-devel@nongnu.org
> Cc: Jovanovic, Petar; aurelien@aurel32.net
> Subject: [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for
> INSV
>
> From: Petar Jovanovic <petarj@mips.com>
>
> Content of register rs should be shifted for pos before applying a mask.
> This change contains both fix for the instruction and to the existing
> test.
>
> Signed-off-by: Petar Jovanovic <petarj@mips.com>
> ---
> target-mips/dsp_helper.c | 2 +-
> tests/tcg/mips/mips32-dsp/insv.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..fda5f04 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env,
> target_ulong rs, \
> \
> filter = ((int32_t)0x01 << size) - 1; \
> filter = filter << pos; \
> - temprs = rs & filter; \
> + temprs = (rs << pos) & filter; \
> temprt = rt & ~filter; \
> temp = temprs | temprt; \
> \
> diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-
> dsp/insv.c
> index 7e3b047..243b007 100644
> --- a/tests/tcg/mips/mips32-dsp/insv.c
> +++ b/tests/tcg/mips/mips32-dsp/insv.c
> @@ -10,7 +10,7 @@ int main()
> dsp = 0x305;
> rt = 0x12345678;
> rs = 0x87654321;
> - result = 0x12345338;
> + result = 0x12345438;
> __asm
> ("wrdsp %2, 0x03\n\t"
> "insv %0, %1\n\t"
> --
> 1.7.5.4
>
Reviewed-by: Eric Johnson <ericj@mips.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV
2012-11-26 15:13 [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV Petar Jovanovic
2012-12-05 19:45 ` Johnson, Eric
@ 2012-12-06 8:10 ` Aurelien Jarno
1 sibling, 0 replies; 3+ messages in thread
From: Aurelien Jarno @ 2012-12-06 8:10 UTC (permalink / raw)
To: Petar Jovanovic; +Cc: petarj, qemu-devel, qemu-stable
On Mon, Nov 26, 2012 at 04:13:21PM +0100, Petar Jovanovic wrote:
> From: Petar Jovanovic <petarj@mips.com>
>
> Content of register rs should be shifted for pos before applying a mask.
> This change contains both fix for the instruction and to the existing test.
>
> Signed-off-by: Petar Jovanovic <petarj@mips.com>
> ---
> target-mips/dsp_helper.c | 2 +-
> tests/tcg/mips/mips32-dsp/insv.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..fda5f04 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
> \
> filter = ((int32_t)0x01 << size) - 1; \
> filter = filter << pos; \
> - temprs = rs & filter; \
> + temprs = (rs << pos) & filter; \
> temprt = rt & ~filter; \
> temp = temprs | temprt; \
> \
> diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c
> index 7e3b047..243b007 100644
> --- a/tests/tcg/mips/mips32-dsp/insv.c
> +++ b/tests/tcg/mips/mips32-dsp/insv.c
> @@ -10,7 +10,7 @@ int main()
> dsp = 0x305;
> rt = 0x12345678;
> rs = 0x87654321;
> - result = 0x12345338;
> + result = 0x12345438;
> __asm
> ("wrdsp %2, 0x03\n\t"
> "insv %0, %1\n\t"
Thanks, applied. I added a CC: to qemu-stable@nongnu.org, as it is
definitely stable material.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 3+ messages in thread
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2012-11-26 15:13 [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV Petar Jovanovic
2012-12-05 19:45 ` Johnson, Eric
2012-12-06 8:10 ` Aurelien Jarno
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