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From: David Gibson <david@gibson.dropbear.id.au>
To: Alexander Graf <agraf@suse.de>
Cc: "qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 11/13] pseries: Fixes and enhancements to L1 cache properties
Date: Wed, 19 Dec 2012 15:34:30 +1100	[thread overview]
Message-ID: <20121219043430.GH8639@truffula.fritz.box> (raw)
In-Reply-To: <89E6E981-6248-4F17-BA9B-258180DAA304@suse.de>

On Tue, Dec 18, 2012 at 12:49:02AM +0100, Alexander Graf wrote:
> 
> On 18.12.2012, at 00:00, David Gibson wrote:
> 
> > On Mon, Dec 17, 2012 at 11:10:12AM +0100, Alexander Graf wrote:
> >> 
> >> 
> >> On 17.12.2012, at 03:32, David Gibson <david@gibson.dropbear.id.au> wrote:
> >> 
> >>> On Thu, Dec 13, 2012 at 01:50:25PM +0100, Alexander Graf wrote:
> >>>> 
> >>>> On 04.12.2012, at 03:42, David Gibson wrote:
> >>>> 
> >>>>> PAPR requires that the device tree's CPU nodes have several properties
> >>>>> with information about the L1 cache.  We created two of these
> >>>>> properties, but with incorrect names - "[id]cache-block-size" instead
> >>>>> of "[id]-cache-block-size" (note the extra hyphen).
> >>>>> 
> >>>>> We were also missing some of the required cache properties.  This
> >>>>> patch adds the [id]-cache-line-size properties (which have the same
> >>>>> values as the block size properties in all current cases).  We also
> >>>>> add the [id]-cache-size properties.  The latter requires some extra
> >>>>> infrastructure in the general target-ppc code to (optionally) set the
> >>>>> cache sizes for various CPUs.  We obtain the published values either
> >>>>> from there, or from the host when KVM is in use.
> >>>>> 
> >>>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> >>>>> ---
> >>>>> hw/spapr.c                  |   20 ++++++++++++++++++--
> >>>>> target-ppc/cpu.h            |    1 +
> >>>>> target-ppc/kvm.c            |   10 ++++++++++
> >>>>> target-ppc/kvm_ppc.h        |   12 ++++++++++++
> >>>>> target-ppc/translate_init.c |    4 ++++
> >>>>> 5 files changed, 45 insertions(+), 2 deletions(-)
> >>>>> 
> >>>>> diff --git a/hw/spapr.c b/hw/spapr.c
> >>>>> index d23aa9d..3bacf2f 100644
> >>>>> --- a/hw/spapr.c
> >>>>> +++ b/hw/spapr.c
> >>>>> @@ -315,6 +315,10 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
> >>>>>                          0xffffffff, 0xffffffff};
> >>>>>       uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
> >>>>>       uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
> >>>>> +        int dcache_size = kvm_enabled() ? kvmppc_get_dcache_size()
> >>>>> +            : env->l1_dcache_size;
> >>>>> +        int icache_size = kvm_enabled() ? kvmppc_get_icache_size()
> >>>>> +            : env->l1_icache_size;
> >>>> 
> >>>> By default with KVM we use -cpu host, right? So we already should
> >>>> get the correct cache sizes for the CPU you're on.
> >>> 
> >>> Um.. sort of.  The first problem with that is that I only just added
> >>> the cache size information to qemu, so only a few CPUs currently
> >>> populate that information.  Using the host info means we can get the
> >>> right information even for CPUs that don't yet have cache info in
> >>> qemu.
> >>> 
> >>>> Imagine we would support the compatibility feature where you could
> >>>> run with -cpu POWER6 on a POWER7 machine. Would exposing the POWER6
> >>>> cache size rather than the host's make any real difference to the
> >>>> guest? Or would it work nevertheless?
> >>> 
> >>> The second problem is that there may be circumstances where the
> >>> cache size is altered from the normal size for the cpu.  Running in
> >>> POWER6 compat mode
> >> 
> >> Well, either we want to be compatible or we don't :). If we run with
> >> -cpu POWER6 we want to generate the same dt as we did on a POWER6
> >> system itself.
> > 
> > Hrm.  Ok.
> > 
> > So, the remaining difficulty I have with that is that for -cpu HOST we
> > should still take the cache sizes from the host, but that can't easily
> > be done because they're only stored in the env, not the cpu_def.
> 
> Can we set a bit somewhere that allows us to do a sanity check
> later? After all, the values coming from the host and the values in
> the populated env really should just be identical for -cpu
> host. Every time they're not, it's simply a bug that needs to be
> reported.

That works.  Although it's not obvious where to put the check and
fixup.  kvmppc_fixup_cpu() seems like the obvious place, but that's no
good because it's called before the per-cpu-type init function, which
is what populates the expected cachesize values.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

  reply	other threads:[~2012-12-19  4:32 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-12-04  2:42 [Qemu-devel] [0/13] Pending pseries/ppc patches as at 1.3 release David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 01/13] pseries: Fix incorrect initialization of interrupt controller David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 02/13] pseries: Use #define for XICS base irq number David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 03/13] pseries: Return the token when we register an RTAS call David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 04/13] pseries: Allow RTAS tokens without a qemu handler David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 05/13] pseries: Add tracepoints to the XICS interrupt controller David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 06/13] pseries: Split xics irq configuration from state information David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 07/13] pseries: Implement PAPR NVRAM David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 08/13] pseries: Update SLOF for NVRAM support David Gibson
2012-12-04 13:20   ` Erlon Cruz
2012-12-04 22:54     ` [Qemu-devel] [Qemu-ppc] " David Gibson
2012-12-04 23:27       ` Erlon Cruz
2012-12-05  0:13         ` David Gibson
2012-12-05  2:27     ` [Qemu-devel] " Alexander Graf
2012-12-05 14:09       ` Erlon Cruz
2012-12-05 14:35         ` Alexander Graf
2012-12-05 14:37           ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2012-12-05 14:39             ` Alexander Graf
2012-12-06 19:41               ` Erlon Cruz
2012-12-06 19:41             ` Erlon Cruz
2012-12-06 19:41           ` [Qemu-devel] " Erlon Cruz
2012-12-07  8:10         ` [Qemu-devel] [Qemu-ppc] " Nikunj A Dadhania
2012-12-07 11:48           ` Erlon Cruz
2012-12-07 11:55             ` Alexander Graf
2012-12-04  2:42 ` [Qemu-devel] [PATCH 09/13] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs David Gibson
2012-12-04  2:42 ` [Qemu-devel] [PATCH 10/13] target-ppc: Don't use hwaddr to represent hardware state David Gibson
2012-12-13 12:51   ` Alexander Graf
2012-12-04  2:42 ` [Qemu-devel] [PATCH 11/13] pseries: Fixes and enhancements to L1 cache properties David Gibson
2012-12-13 12:50   ` Alexander Graf
2012-12-17  2:32     ` [Qemu-devel] [Qemu-ppc] " David Gibson
2012-12-17 10:10       ` Alexander Graf
2012-12-17 23:00         ` David Gibson
2012-12-17 23:49           ` Alexander Graf
2012-12-19  4:34             ` David Gibson [this message]
2012-12-19 22:40               ` Alexander Graf
2012-12-20  3:38                 ` David Gibson
2012-12-20  9:32                   ` Alexander Graf
2012-12-04  2:42 ` [Qemu-devel] [PATCH 12/13] pseries: Increase default NVRAM size David Gibson
2012-12-13 12:51   ` Alexander Graf
2012-12-04  2:42 ` [Qemu-devel] [PATCH 13/13] target-ppc: Give a meaningful error if too many threads are specified David Gibson
2012-12-04  3:11   ` David Gibson
2012-12-13 12:57     ` Alexander Graf
2012-12-13 13:17       ` David Gibson
2012-12-13 13:19         ` Alexander Graf
2012-12-13 14:17           ` Peter Maydell
2012-12-13 14:18             ` Peter Maydell
2012-12-17  2:13               ` David Gibson

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