From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59621) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TstBl-00058T-9U for qemu-devel@nongnu.org; Wed, 09 Jan 2013 05:47:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TstBg-0001Cu-ST for qemu-devel@nongnu.org; Wed, 09 Jan 2013 05:47:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:24751) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TstBg-0001Cq-Ja for qemu-devel@nongnu.org; Wed, 09 Jan 2013 05:47:12 -0500 Date: Wed, 9 Jan 2013 12:51:00 +0200 From: "Michael S. Tsirkin" Message-ID: <20130109105100.GA17137@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] e1000: make ICS write-only List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, wpaul@windriver.com, yan@daynix.com Cc: Paolo Bonzini , Anthony Liguori , Jason Wang , Stefan Hajnoczi , "Michael S. Tsirkin" Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968, qemu started updating ICS register when interrupt is sent, with the intent to match spec better (guests do not actually read this register). However, the function set_interrupt_cause where ICS is updated is often called internally by device emulation so reading it does not produce the last value written by driver. Looking closer at the spec, it documents ICS as write-only, so there's no need to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in. Tested with windows and linux guests. Cc: Bill Paul Reported-by: Yan Vugenfirer Signed-off-by: Michael S. Tsirkin --- hw/e1000.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/e1000.c b/hw/e1000.c index 92fb00a..928d804 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val) val |= E1000_ICR_INT_ASSERTED; } s->mac_reg[ICR] = val; - s->mac_reg[ICS] = val; qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); } -- MST