From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tt3eS-0003RO-FO for qemu-devel@nongnu.org; Wed, 09 Jan 2013 16:57:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tt3eP-0002vE-Mk for qemu-devel@nongnu.org; Wed, 09 Jan 2013 16:57:36 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45492) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tt3eP-0002vA-F3 for qemu-devel@nongnu.org; Wed, 09 Jan 2013 16:57:33 -0500 Date: Thu, 10 Jan 2013 00:01:22 +0200 From: "Michael S. Tsirkin" Message-ID: <20130109220122.GA12016@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] e1000: document ICS read behaviour List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Bill Paul Cc: Paolo Bonzini , Anthony Liguori , Jason Wang , Stefan Hajnoczi Add code comment to clarify the reason we set ICS with ICR: the reason was previously undocumented and git log (commit b1332393cdd7d023de8f1f8aa136ee7866a18968) confused rather than clarified the comments. Digging in the mailing list archives gives the real reason https://lists.gnu.org/archive/html/qemu-devel/2009-06/msg00401.html Add code comment with an explanation supplied by Bill Paul. Signed-off-by: Michael S. Tsirkin --- hw/e1000.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/e1000.c b/hw/e1000.c index 92fb00a..73e360e 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -230,7 +230,18 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val) val |= E1000_ICR_INT_ASSERTED; } s->mac_reg[ICR] = val; + + /* + * Make sure ICR and ICS registers have the same value. + * The spec says that the ICS register is write-only. However in practice, + * on real hardware ICS is readable, and for reads it has the same value as + * ICR (except that ICS does not have the clear on read behaviour of ICR). + * + * The VxWorks PRO/1000 driver relies on this behaviour, so we have to + * emulate it. + */ s->mac_reg[ICS] = val; + qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); } -- MST