* [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup
@ 2013-01-09 15:27 Aurelien Jarno
2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 Aurelien Jarno
` (9 more replies)
0 siblings, 10 replies; 18+ messages in thread
From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
This patch series contains some fixes and cleanup following the merge
of the DSP ASE patches.
Changes v1 -> v2:
- patch 1: unchanged
- patch 2: new patch as suggested by Richard Henderson
- patch 3: updated to use insn_flags from DisasContext
- patch 4: unchanged
- patch 5: fix the cast on the return value
- patch 6: fix the cast on the return value
- patch 7: unchanged
- patch 8: unchanged
Aurelien Jarno (8):
target-mips: fix DSP loads with rd = 0
target-mips: copy insn_flags in DisasContext
target-mips: generate a reserved instruction exception on CPU without DSP
target-mips: add unions to access DSP elements
target-mips: use DSP unions for binary DSP operators
target-mips: use DSP unions for unary DSP operators
target-mips: use DSP unions for reduction add instructions
target-mips: implement DSP (d)append sub-class with TCG
target-mips/dsp_helper.c | 623 ++++++++++---------------------
target-mips/helper.h | 13 -
target-mips/translate.c | 912 ++++++++++++++++++++++++----------------------
3 files changed, 670 insertions(+), 878 deletions(-)
--
1.7.10.4
^ permalink raw reply [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 2/8] target-mips: copy insn_flags in DisasContext Aurelien Jarno ` (8 subsequent siblings) 9 siblings, 0 replies; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno When rd is 0, which still need to do the actually load to possibly generate a TLB exception. Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/translate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 6281e70..d1fc5af 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12657,11 +12657,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, const char *opn = "ldx"; TCGv t0; - if (rd == 0) { - MIPS_DEBUG("NOP"); - return; - } - check_dsp(ctx); t0 = tcg_temp_new(); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 2/8] target-mips: copy insn_flags in DisasContext 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP Aurelien Jarno ` (7 subsequent siblings) 9 siblings, 0 replies; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno Copy insn_flags in DisasContext to avoid passing a CPUMIPSState pointer to subroutines, as suggested by Richard Henderson. Change subroutines to use this new field and remove the first argument. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/translate.c | 762 +++++++++++++++++++++++------------------------ 1 file changed, 381 insertions(+), 381 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index d1fc5af..33d04fb 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1066,6 +1066,7 @@ typedef struct DisasContext { target_ulong pc, saved_pc; uint32_t opcode; int singlestep_enabled; + int insn_flags; /* Routine used to access memory */ int mem_idx; uint32_t hflags, saved_hflags; @@ -1406,10 +1407,11 @@ static inline void check_dspr2(DisasContext *ctx) /* This code generates a "reserved instruction" exception if the CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags) +static inline void check_insn(DisasContext *ctx, int flags) { - if (unlikely(!(env->insn_flags & flags))) + if (unlikely(!(ctx->insn_flags & flags))) { generate_exception(ctx, EXCP_RI); + } } /* This code generates a "reserved instruction" exception if 64-bit @@ -1576,13 +1578,13 @@ static target_ulong pc_relative_pc (DisasContext *ctx) } /* Load */ -static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, - int rt, int base, int16_t offset) +static void gen_ld(DisasContext *ctx, uint32_t opc, + int rt, int base, int16_t offset) { const char *opn = "ld"; TCGv t0, t1, t2; - if (rt == 0 && env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) { + if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) { /* Loongson CPU uses a load to zero register for prefetch. We emulate it as a NOP. On other CPU we must perform the actual memory access. */ @@ -1921,8 +1923,8 @@ static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx, } /* Arithmetic with immediate operand */ -static void gen_arith_imm (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, - int rt, int rs, int16_t imm) +static void gen_arith_imm(DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ const char *opn = "imm arith"; @@ -2009,7 +2011,7 @@ static void gen_arith_imm (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Logic with immediate operand */ -static void gen_logic_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_logic_imm(DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { target_ulong uimm; @@ -2057,7 +2059,7 @@ static void gen_logic_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Set on less than with immediate operand */ -static void gen_slt_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_slt_imm(DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ @@ -2087,7 +2089,7 @@ static void gen_slt_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Shifts with immediate operand */ -static void gen_shift_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_shift_imm(DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { target_ulong uimm = ((uint16_t)imm) & 0x1f; @@ -2179,8 +2181,8 @@ static void gen_shift_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Arithmetic */ -static void gen_arith (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) +static void gen_arith(DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "arith"; @@ -2359,7 +2361,7 @@ static void gen_arith (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Conditional move */ -static void gen_cond_move(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_cond_move(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { const char *opn = "cond move"; @@ -2395,7 +2397,7 @@ static void gen_cond_move(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Logic */ -static void gen_logic(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_logic(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { const char *opn = "logic"; @@ -2457,7 +2459,7 @@ static void gen_logic(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Set on lower than */ -static void gen_slt(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_slt(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { const char *opn = "slt"; @@ -2490,8 +2492,8 @@ static void gen_slt(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Shifts */ -static void gen_shift (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) +static void gen_shift(DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "shifts"; TCGv t0, t1; @@ -4097,12 +4099,12 @@ static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) tcg_gen_st_tl(arg, cpu_env, off); } -static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; if (sel != 0) - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); switch (reg) { case 0: @@ -4112,17 +4114,17 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Index"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_mvpcontrol(arg, cpu_env); rn = "MVPControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_mvpconf0(arg, cpu_env); rn = "MVPConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_mvpconf1(arg, cpu_env); rn = "MVPConf1"; break; @@ -4137,37 +4139,37 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Random"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); rn = "VPEControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); rn = "VPEConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); rn = "VPEConf1"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); rn = "YQMask"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); rn = "VPEOpt"; break; @@ -4183,37 +4185,37 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "EntryLo0"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcstatus(arg, cpu_env); rn = "TCStatus"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcbind(arg, cpu_env); rn = "TCBind"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcrestart(arg, cpu_env); rn = "TCRestart"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tchalt(arg, cpu_env); rn = "TCHalt"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tccontext(arg, cpu_env); rn = "TCContext"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcschedule(arg, cpu_env); rn = "TCSchedule"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcschefback(arg, cpu_env); rn = "TCScheFBack"; break; @@ -4254,7 +4256,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "PageMask"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); rn = "PageGrain"; break; @@ -4269,27 +4271,27 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Wired"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); rn = "SRSConf0"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); rn = "SRSConf1"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); rn = "SRSConf2"; break; case 4: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); rn = "SRSConf3"; break; case 5: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); rn = "SRSConf4"; break; @@ -4300,7 +4302,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 7: switch (sel) { case 0: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); rn = "HWREna"; break; @@ -4368,17 +4370,17 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Status"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); rn = "IntCtl"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); rn = "SRSCtl"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); rn = "SRSMap"; break; @@ -4414,7 +4416,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "PRid"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase)); rn = "EBase"; break; @@ -4488,7 +4490,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i switch (sel) { case 0: #if defined(TARGET_MIPS64) - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); tcg_gen_ext32s_tl(arg, arg); rn = "XContext"; @@ -4677,12 +4679,12 @@ die: generate_exception(ctx, EXCP_RI); } -static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; if (sel != 0) - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); if (use_icount) gen_io_start(); @@ -4695,17 +4697,17 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Index"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); rn = "MVPControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); /* ignored */ rn = "MVPConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); /* ignored */ rn = "MVPConf1"; break; @@ -4720,37 +4722,37 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Random"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpecontrol(cpu_env, arg); rn = "VPEControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpeconf0(cpu_env, arg); rn = "VPEConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpeconf1(cpu_env, arg); rn = "VPEConf1"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_yqmask(cpu_env, arg); rn = "YQMask"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpeopt(cpu_env, arg); rn = "VPEOpt"; break; @@ -4765,37 +4767,37 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "EntryLo0"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); rn = "TCStatus"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); rn = "TCBind"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); rn = "TCRestart"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); rn = "TCHalt"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); rn = "TCContext"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); rn = "TCSchedule"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); rn = "TCScheFBack"; break; @@ -4834,7 +4836,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "PageMask"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); rn = "PageGrain"; break; @@ -4849,27 +4851,27 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Wired"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); rn = "SRSConf0"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); rn = "SRSConf1"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); rn = "SRSConf2"; break; case 4: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); rn = "SRSConf3"; break; case 5: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); rn = "SRSConf4"; break; @@ -4880,7 +4882,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 7: switch (sel) { case 0: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); rn = "HWREna"; break; @@ -4935,21 +4937,21 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Status"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -4987,7 +4989,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "PRid"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); rn = "EBase"; break; @@ -5066,7 +5068,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i switch (sel) { case 0: #if defined(TARGET_MIPS64) - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); rn = "XContext"; break; @@ -5274,12 +5276,12 @@ die: } #if defined(TARGET_MIPS64) -static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; if (sel != 0) - check_insn(env, ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS64); switch (reg) { case 0: @@ -5289,17 +5291,17 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Index"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_mvpcontrol(arg, cpu_env); rn = "MVPControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_mvpconf0(arg, cpu_env); rn = "MVPConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_mvpconf1(arg, cpu_env); rn = "MVPConf1"; break; @@ -5314,37 +5316,37 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Random"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); rn = "VPEControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); rn = "VPEConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); rn = "VPEConf1"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask)); rn = "YQMask"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); rn = "VPEOpt"; break; @@ -5359,37 +5361,37 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "EntryLo0"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcstatus(arg, cpu_env); rn = "TCStatus"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mfc0_tcbind(arg, cpu_env); rn = "TCBind"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dmfc0_tcrestart(arg, cpu_env); rn = "TCRestart"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dmfc0_tchalt(arg, cpu_env); rn = "TCHalt"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dmfc0_tccontext(arg, cpu_env); rn = "TCContext"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dmfc0_tcschedule(arg, cpu_env); rn = "TCSchedule"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dmfc0_tcschefback(arg, cpu_env); rn = "TCScheFBack"; break; @@ -5428,7 +5430,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "PageMask"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); rn = "PageGrain"; break; @@ -5443,27 +5445,27 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Wired"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); rn = "SRSConf0"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); rn = "SRSConf1"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); rn = "SRSConf2"; break; case 4: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); rn = "SRSConf3"; break; case 5: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); rn = "SRSConf4"; break; @@ -5474,7 +5476,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 7: switch (sel) { case 0: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); rn = "HWREna"; break; @@ -5540,17 +5542,17 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Status"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); rn = "IntCtl"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); rn = "SRSCtl"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); rn = "SRSMap"; break; @@ -5585,7 +5587,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "PRid"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase)); rn = "EBase"; break; @@ -5657,7 +5659,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 20: switch (sel) { case 0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); rn = "XContext"; break; @@ -5843,12 +5845,12 @@ die: generate_exception(ctx, EXCP_RI); } -static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; if (sel != 0) - check_insn(env, ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS64); if (use_icount) gen_io_start(); @@ -5861,17 +5863,17 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Index"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); rn = "MVPControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); /* ignored */ rn = "MVPConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); /* ignored */ rn = "MVPConf1"; break; @@ -5886,37 +5888,37 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Random"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpecontrol(cpu_env, arg); rn = "VPEControl"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpeconf0(cpu_env, arg); rn = "VPEConf0"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpeconf1(cpu_env, arg); rn = "VPEConf1"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_yqmask(cpu_env, arg); rn = "YQMask"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_vpeopt(cpu_env, arg); rn = "VPEOpt"; break; @@ -5931,37 +5933,37 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "EntryLo0"; break; case 1: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); rn = "TCStatus"; break; case 2: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); rn = "TCBind"; break; case 3: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); rn = "TCRestart"; break; case 4: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); rn = "TCHalt"; break; case 5: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); rn = "TCContext"; break; case 6: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); rn = "TCSchedule"; break; case 7: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); rn = "TCScheFBack"; break; @@ -6000,7 +6002,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "PageMask"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); rn = "PageGrain"; break; @@ -6015,27 +6017,27 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Wired"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); rn = "SRSConf0"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); rn = "SRSConf1"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); rn = "SRSConf2"; break; case 4: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); rn = "SRSConf3"; break; case 5: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); rn = "SRSConf4"; break; @@ -6046,7 +6048,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 7: switch (sel) { case 0: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); rn = "HWREna"; break; @@ -6105,21 +6107,21 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Status"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -6167,7 +6169,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "PRid"; break; case 1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); rn = "EBase"; break; @@ -6236,7 +6238,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 20: switch (sel) { case 0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); rn = "XContext"; break; @@ -6493,7 +6495,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, gen_helper_mftc0_tcschefback(t0, cpu_env); break; default: - gen_mfc0(env, ctx, t0, rt, sel); + gen_mfc0(ctx, t0, rt, sel); break; } break; @@ -6503,7 +6505,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, gen_helper_mftc0_entryhi(t0, cpu_env); break; default: - gen_mfc0(env, ctx, t0, rt, sel); + gen_mfc0(ctx, t0, rt, sel); break; } case 12: @@ -6512,7 +6514,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, gen_helper_mftc0_status(t0, cpu_env); break; default: - gen_mfc0(env, ctx, t0, rt, sel); + gen_mfc0(ctx, t0, rt, sel); break; } case 13: @@ -6561,12 +6563,12 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, gen_helper_mftc0_debug(t0, cpu_env); break; default: - gen_mfc0(env, ctx, t0, rt, sel); + gen_mfc0(ctx, t0, rt, sel); break; } break; default: - gen_mfc0(env, ctx, t0, rt, sel); + gen_mfc0(ctx, t0, rt, sel); } } else switch (sel) { /* GPR registers. */ @@ -6711,7 +6713,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, gen_helper_mttc0_tcschefback(cpu_env, t0); break; default: - gen_mtc0(env, ctx, t0, rd, sel); + gen_mtc0(ctx, t0, rd, sel); break; } break; @@ -6721,7 +6723,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, gen_helper_mttc0_entryhi(cpu_env, t0); break; default: - gen_mtc0(env, ctx, t0, rd, sel); + gen_mtc0(ctx, t0, rd, sel); break; } case 12: @@ -6730,7 +6732,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, gen_helper_mttc0_status(cpu_env, t0); break; default: - gen_mtc0(env, ctx, t0, rd, sel); + gen_mtc0(ctx, t0, rd, sel); break; } case 13: @@ -6759,12 +6761,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, gen_helper_mttc0_debug(cpu_env, t0); break; default: - gen_mtc0(env, ctx, t0, rd, sel); + gen_mtc0(ctx, t0, rd, sel); break; } break; default: - gen_mtc0(env, ctx, t0, rd, sel); + gen_mtc0(ctx, t0, rd, sel); } } else switch (sel) { /* GPR registers. */ @@ -6866,7 +6868,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, /* Treat as NOP. */ return; } - gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); + gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); opn = "mfc0"; break; case OPC_MTC0: @@ -6874,35 +6876,35 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rt); - gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7); + gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); tcg_temp_free(t0); } opn = "mtc0"; break; #if defined(TARGET_MIPS64) case OPC_DMFC0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); if (rt == 0) { /* Treat as NOP. */ return; } - gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); + gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); opn = "dmfc0"; break; case OPC_DMTC0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); { TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rt); - gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7); + gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); tcg_temp_free(t0); } opn = "dmtc0"; break; #endif case OPC_MFTR: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); if (rd == 0) { /* Treat as NOP. */ return; @@ -6912,7 +6914,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, opn = "mftr"; break; case OPC_MTTR: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); opn = "mttr"; @@ -6943,13 +6945,13 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, break; case OPC_ERET: opn = "eret"; - check_insn(env, ctx, ISA_MIPS2); + check_insn(ctx, ISA_MIPS2); gen_helper_eret(cpu_env); ctx->bstate = BS_EXCP; break; case OPC_DERET: opn = "deret"; - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { MIPS_INVAL(opn); generate_exception(ctx, EXCP_RI); @@ -6960,7 +6962,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, break; case OPC_WAIT: opn = "wait"; - check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); /* If we get an exception, we want to restart at next instruction */ ctx->pc += 4; save_cpu_state(ctx, 1); @@ -6980,15 +6982,15 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, #endif /* !CONFIG_USER_ONLY */ /* CP1 Branches (before delay slot) */ -static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t op, - int32_t cc, int32_t offset) +static void gen_compute_branch1(DisasContext *ctx, uint32_t op, + int32_t cc, int32_t offset) { target_ulong btarget; const char *opn = "cp1 cond branch"; TCGv_i32 t0 = tcg_temp_new_i32(); if (cc != 0) - check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); btarget = ctx->pc + 4 + offset; @@ -9032,15 +9034,14 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, fregnames[fs], fregnames[ft]); } -static void -gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd) +static void gen_rdhwr(DisasContext *ctx, int rt, int rd) { TCGv t0; #if !defined(CONFIG_USER_ONLY) /* The Linux kernel will emulate rdhwr if it's not supported natively. Therefore only check the ISA in system mode. */ - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); #endif t0 = tcg_temp_new(); @@ -9082,8 +9083,7 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd) tcg_temp_free(t0); } -static void handle_delay_slot (CPUMIPSState *env, DisasContext *ctx, - int insn_bytes) +static void handle_delay_slot(DisasContext *ctx, int insn_bytes) { if (ctx->hflags & MIPS_HFLAG_BMASK) { int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; @@ -9121,7 +9121,7 @@ static void handle_delay_slot (CPUMIPSState *env, DisasContext *ctx, case MIPS_HFLAG_BR: /* unconditional branch to register */ MIPS_DEBUG("branch to register"); - if (env->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { + if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { TCGv t0 = tcg_temp_new(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -9548,7 +9548,7 @@ static void gen_addiupc (DisasContext *ctx, int rx, int imm, } #if defined(TARGET_MIPS64) -static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx, +static void decode_i64_mips16 (DisasContext *ctx, int ry, int funct, int16_t offset, int extended) { @@ -9556,7 +9556,7 @@ static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx, case I64_LDSP: check_mips_64(ctx); offset = extended ? offset : offset << 3; - gen_ld(env, ctx, OPC_LD, ry, 29, offset); + gen_ld(ctx, OPC_LD, ry, 29, offset); break; case I64_SDSP: check_mips_64(ctx); @@ -9571,20 +9571,20 @@ static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx, case I64_DADJSP: check_mips_64(ctx); offset = extended ? offset : ((int8_t)ctx->opcode) << 3; - gen_arith_imm(env, ctx, OPC_DADDIU, 29, 29, offset); + gen_arith_imm(ctx, OPC_DADDIU, 29, 29, offset); break; case I64_LDPC: if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { generate_exception(ctx, EXCP_RI); } else { offset = extended ? offset : offset << 3; - gen_ld(env, ctx, OPC_LDPC, ry, 0, offset); + gen_ld(ctx, OPC_LDPC, ry, 0, offset); } break; case I64_DADDIU5: check_mips_64(ctx); offset = extended ? offset : ((int8_t)(offset << 3)) >> 3; - gen_arith_imm(env, ctx, OPC_DADDIU, ry, ry, offset); + gen_arith_imm(ctx, OPC_DADDIU, ry, ry, offset); break; case I64_DADDIUPC: check_mips_64(ctx); @@ -9594,7 +9594,7 @@ static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx, case I64_DADDIUSP: check_mips_64(ctx); offset = extended ? offset : offset << 2; - gen_arith_imm(env, ctx, OPC_DADDIU, ry, 29, offset); + gen_arith_imm(ctx, OPC_DADDIU, ry, 29, offset); break; } } @@ -9621,7 +9621,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, counterparts. */ switch (op) { case M16_OPC_ADDIUSP: - gen_arith_imm(env, ctx, OPC_ADDIU, rx, 29, imm); + gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm); break; case M16_OPC_ADDIUPC: gen_addiupc(ctx, rx, imm, 0, 1); @@ -9641,28 +9641,28 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, case M16_OPC_SHIFT: switch (ctx->opcode & 0x3) { case 0x0: - gen_shift_imm(env, ctx, OPC_SLL, rx, ry, sa); + gen_shift_imm(ctx, OPC_SLL, rx, ry, sa); break; case 0x1: #if defined(TARGET_MIPS64) check_mips_64(ctx); - gen_shift_imm(env, ctx, OPC_DSLL, rx, ry, sa); + gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else generate_exception(ctx, EXCP_RI); #endif break; case 0x2: - gen_shift_imm(env, ctx, OPC_SRL, rx, ry, sa); + gen_shift_imm(ctx, OPC_SRL, rx, ry, sa); break; case 0x3: - gen_shift_imm(env, ctx, OPC_SRA, rx, ry, sa); + gen_shift_imm(ctx, OPC_SRA, rx, ry, sa); break; } break; #if defined(TARGET_MIPS64) case M16_OPC_LD: check_mips_64(ctx); - gen_ld(env, ctx, OPC_LD, ry, rx, offset); + gen_ld(ctx, OPC_LD, ry, rx, offset); break; #endif case M16_OPC_RRIA: @@ -9673,22 +9673,22 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, if ((ctx->opcode >> 4) & 0x1) { #if defined(TARGET_MIPS64) check_mips_64(ctx); - gen_arith_imm(env, ctx, OPC_DADDIU, ry, rx, imm); + gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else generate_exception(ctx, EXCP_RI); #endif } else { - gen_arith_imm(env, ctx, OPC_ADDIU, ry, rx, imm); + gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); } break; case M16_OPC_ADDIU8: - gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm); + gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm); break; case M16_OPC_SLTI: - gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm); + gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm); break; case M16_OPC_SLTIU: - gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm); + gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm); break; case M16_OPC_I8: switch (funct) { @@ -9702,7 +9702,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, gen_st(ctx, OPC_SW, 31, 29, imm); break; case I8_ADJSP: - gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, imm); + gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm); break; case I8_SVRS: { @@ -9742,29 +9742,29 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, break; #endif case M16_OPC_LB: - gen_ld(env, ctx, OPC_LB, ry, rx, offset); + gen_ld(ctx, OPC_LB, ry, rx, offset); break; case M16_OPC_LH: - gen_ld(env, ctx, OPC_LH, ry, rx, offset); + gen_ld(ctx, OPC_LH, ry, rx, offset); break; case M16_OPC_LWSP: - gen_ld(env, ctx, OPC_LW, rx, 29, offset); + gen_ld(ctx, OPC_LW, rx, 29, offset); break; case M16_OPC_LW: - gen_ld(env, ctx, OPC_LW, ry, rx, offset); + gen_ld(ctx, OPC_LW, ry, rx, offset); break; case M16_OPC_LBU: - gen_ld(env, ctx, OPC_LBU, ry, rx, offset); + gen_ld(ctx, OPC_LBU, ry, rx, offset); break; case M16_OPC_LHU: - gen_ld(env, ctx, OPC_LHU, ry, rx, offset); + gen_ld(ctx, OPC_LHU, ry, rx, offset); break; case M16_OPC_LWPC: - gen_ld(env, ctx, OPC_LWPC, rx, 0, offset); + gen_ld(ctx, OPC_LWPC, rx, 0, offset); break; #if defined(TARGET_MIPS64) case M16_OPC_LWU: - gen_ld(env, ctx, OPC_LWU, ry, rx, offset); + gen_ld(ctx, OPC_LWU, ry, rx, offset); break; #endif case M16_OPC_SB: @@ -9781,7 +9781,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, break; #if defined(TARGET_MIPS64) case M16_OPC_I64: - decode_i64_mips16(env, ctx, ry, funct, offset, 1); + decode_i64_mips16(ctx, ry, funct, offset, 1); break; #endif default: @@ -9816,7 +9816,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, { int16_t imm = ((uint8_t) ctx->opcode) << 2; - gen_arith_imm(env, ctx, OPC_ADDIU, rx, 29, imm); + gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm); } break; case M16_OPC_ADDIUPC: @@ -9849,28 +9849,28 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, case M16_OPC_SHIFT: switch (ctx->opcode & 0x3) { case 0x0: - gen_shift_imm(env, ctx, OPC_SLL, rx, ry, sa); + gen_shift_imm(ctx, OPC_SLL, rx, ry, sa); break; case 0x1: #if defined(TARGET_MIPS64) check_mips_64(ctx); - gen_shift_imm(env, ctx, OPC_DSLL, rx, ry, sa); + gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else generate_exception(ctx, EXCP_RI); #endif break; case 0x2: - gen_shift_imm(env, ctx, OPC_SRL, rx, ry, sa); + gen_shift_imm(ctx, OPC_SRL, rx, ry, sa); break; case 0x3: - gen_shift_imm(env, ctx, OPC_SRA, rx, ry, sa); + gen_shift_imm(ctx, OPC_SRA, rx, ry, sa); break; } break; #if defined(TARGET_MIPS64) case M16_OPC_LD: check_mips_64(ctx); - gen_ld(env, ctx, OPC_LD, ry, rx, offset << 3); + gen_ld(ctx, OPC_LD, ry, rx, offset << 3); break; #endif case M16_OPC_RRIA: @@ -9880,12 +9880,12 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, if ((ctx->opcode >> 4) & 1) { #if defined(TARGET_MIPS64) check_mips_64(ctx); - gen_arith_imm(env, ctx, OPC_DADDIU, ry, rx, imm); + gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else generate_exception(ctx, EXCP_RI); #endif } else { - gen_arith_imm(env, ctx, OPC_ADDIU, ry, rx, imm); + gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); } } break; @@ -9893,19 +9893,19 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, { int16_t imm = (int8_t) ctx->opcode; - gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm); + gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm); } break; case M16_OPC_SLTI: { int16_t imm = (uint8_t) ctx->opcode; - gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm); + gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm); } break; case M16_OPC_SLTIU: { int16_t imm = (uint8_t) ctx->opcode; - gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm); + gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm); } break; case M16_OPC_I8: @@ -9926,7 +9926,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, gen_st(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2); break; case I8_ADJSP: - gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, + gen_arith_imm(ctx, OPC_ADDIU, 29, 29, ((int8_t)ctx->opcode) << 3); break; case I8_SVRS: @@ -9957,12 +9957,12 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, reg32 = (((ctx->opcode >> 3) & 0x3) << 3) | ((ctx->opcode >> 5) & 0x7); - gen_arith(env, ctx, OPC_ADDU, reg32, rz, 0); + gen_arith(ctx, OPC_ADDU, reg32, rz, 0); } break; case I8_MOVR32: reg32 = ctx->opcode & 0x1f; - gen_arith(env, ctx, OPC_ADDU, ry, reg32, 0); + gen_arith(ctx, OPC_ADDU, ry, reg32, 0); break; default: generate_exception(ctx, EXCP_RI); @@ -9974,13 +9974,13 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, { int16_t imm = (uint8_t) ctx->opcode; - gen_arith_imm(env, ctx, OPC_ADDIU, rx, 0, imm); + gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm); } break; case M16_OPC_CMPI: { int16_t imm = (uint8_t) ctx->opcode; - gen_logic_imm(env, ctx, OPC_XORI, 24, rx, imm); + gen_logic_imm(ctx, OPC_XORI, 24, rx, imm); } break; #if defined(TARGET_MIPS64) @@ -9990,30 +9990,30 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, break; #endif case M16_OPC_LB: - gen_ld(env, ctx, OPC_LB, ry, rx, offset); + gen_ld(ctx, OPC_LB, ry, rx, offset); break; case M16_OPC_LH: - gen_ld(env, ctx, OPC_LH, ry, rx, offset << 1); + gen_ld(ctx, OPC_LH, ry, rx, offset << 1); break; case M16_OPC_LWSP: - gen_ld(env, ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2); + gen_ld(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2); break; case M16_OPC_LW: - gen_ld(env, ctx, OPC_LW, ry, rx, offset << 2); + gen_ld(ctx, OPC_LW, ry, rx, offset << 2); break; case M16_OPC_LBU: - gen_ld(env, ctx, OPC_LBU, ry, rx, offset); + gen_ld(ctx, OPC_LBU, ry, rx, offset); break; case M16_OPC_LHU: - gen_ld(env, ctx, OPC_LHU, ry, rx, offset << 1); + gen_ld(ctx, OPC_LHU, ry, rx, offset << 1); break; case M16_OPC_LWPC: - gen_ld(env, ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); + gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); break; #if defined (TARGET_MIPS64) case M16_OPC_LWU: check_mips_64(ctx); - gen_ld(env, ctx, OPC_LWU, ry, rx, offset << 2); + gen_ld(ctx, OPC_LWU, ry, rx, offset << 2); break; #endif case M16_OPC_SB: @@ -10055,7 +10055,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, goto done; } - gen_arith(env, ctx, mips32_op, rz, rx, ry); + gen_arith(ctx, mips32_op, rz, rx, ry); done: ; } @@ -10084,7 +10084,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, /* XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { generate_exception(ctx, EXCP_DBp); } else { @@ -10092,46 +10092,46 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, } break; case RR_SLT: - gen_slt(env, ctx, OPC_SLT, 24, rx, ry); + gen_slt(ctx, OPC_SLT, 24, rx, ry); break; case RR_SLTU: - gen_slt(env, ctx, OPC_SLTU, 24, rx, ry); + gen_slt(ctx, OPC_SLTU, 24, rx, ry); break; case RR_BREAK: generate_exception(ctx, EXCP_BREAK); break; case RR_SLLV: - gen_shift(env, ctx, OPC_SLLV, ry, rx, ry); + gen_shift(ctx, OPC_SLLV, ry, rx, ry); break; case RR_SRLV: - gen_shift(env, ctx, OPC_SRLV, ry, rx, ry); + gen_shift(ctx, OPC_SRLV, ry, rx, ry); break; case RR_SRAV: - gen_shift(env, ctx, OPC_SRAV, ry, rx, ry); + gen_shift(ctx, OPC_SRAV, ry, rx, ry); break; #if defined (TARGET_MIPS64) case RR_DSRL: check_mips_64(ctx); - gen_shift_imm(env, ctx, OPC_DSRL, ry, ry, sa); + gen_shift_imm(ctx, OPC_DSRL, ry, ry, sa); break; #endif case RR_CMP: - gen_logic(env, ctx, OPC_XOR, 24, rx, ry); + gen_logic(ctx, OPC_XOR, 24, rx, ry); break; case RR_NEG: - gen_arith(env, ctx, OPC_SUBU, rx, 0, ry); + gen_arith(ctx, OPC_SUBU, rx, 0, ry); break; case RR_AND: - gen_logic(env, ctx, OPC_AND, rx, rx, ry); + gen_logic(ctx, OPC_AND, rx, rx, ry); break; case RR_OR: - gen_logic(env, ctx, OPC_OR, rx, rx, ry); + gen_logic(ctx, OPC_OR, rx, rx, ry); break; case RR_XOR: - gen_logic(env, ctx, OPC_XOR, rx, rx, ry); + gen_logic(ctx, OPC_XOR, rx, rx, ry); break; case RR_NOT: - gen_logic(env, ctx, OPC_NOR, rx, ry, 0); + gen_logic(ctx, OPC_NOR, rx, ry, 0); break; case RR_MFHI: gen_HILO(ctx, OPC_MFHI, rx); @@ -10171,19 +10171,19 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, #if defined (TARGET_MIPS64) case RR_DSRA: check_mips_64(ctx); - gen_shift_imm(env, ctx, OPC_DSRA, ry, ry, sa); + gen_shift_imm(ctx, OPC_DSRA, ry, ry, sa); break; case RR_DSLLV: check_mips_64(ctx); - gen_shift(env, ctx, OPC_DSLLV, ry, rx, ry); + gen_shift(ctx, OPC_DSLLV, ry, rx, ry); break; case RR_DSRLV: check_mips_64(ctx); - gen_shift(env, ctx, OPC_DSRLV, ry, rx, ry); + gen_shift(ctx, OPC_DSRLV, ry, rx, ry); break; case RR_DSRAV: check_mips_64(ctx); - gen_shift(env, ctx, OPC_DSRAV, ry, rx, ry); + gen_shift(ctx, OPC_DSRAV, ry, rx, ry); break; #endif case RR_MULT: @@ -10228,7 +10228,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, #if defined(TARGET_MIPS64) case M16_OPC_I64: funct = (ctx->opcode >> 8) & 0x7; - decode_i64_mips16(env, ctx, ry, funct, offset, 0); + decode_i64_mips16(ctx, ry, funct, offset, 0); break; #endif default: @@ -10730,23 +10730,23 @@ static int mmreg2 (int r) /* Zero-extended immediate */ #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width))) -static void gen_addiur1sp (CPUMIPSState *env, DisasContext *ctx) +static void gen_addiur1sp(DisasContext *ctx) { int rd = mmreg(uMIPS_RD(ctx->opcode)); - gen_arith_imm(env, ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); + gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); } -static void gen_addiur2 (CPUMIPSState *env, DisasContext *ctx) +static void gen_addiur2(DisasContext *ctx) { static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 }; int rd = mmreg(uMIPS_RD(ctx->opcode)); int rs = mmreg(uMIPS_RS(ctx->opcode)); - gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); + gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); } -static void gen_addiusp (CPUMIPSState *env, DisasContext *ctx) +static void gen_addiusp(DisasContext *ctx) { int encoded = ZIMM(ctx->opcode, 1, 9); int decoded; @@ -10761,18 +10761,18 @@ static void gen_addiusp (CPUMIPSState *env, DisasContext *ctx) decoded = encoded - 768; } - gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, decoded << 2); + gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2); } -static void gen_addius5 (CPUMIPSState *env, DisasContext *ctx) +static void gen_addius5(DisasContext *ctx) { int imm = SIMM(ctx->opcode, 1, 4); int rd = (ctx->opcode >> 5) & 0x1f; - gen_arith_imm(env, ctx, OPC_ADDIU, rd, rd, imm); + gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm); } -static void gen_andi16 (CPUMIPSState *env, DisasContext *ctx) +static void gen_andi16(DisasContext *ctx) { static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 }; @@ -10780,7 +10780,7 @@ static void gen_andi16 (CPUMIPSState *env, DisasContext *ctx) int rs = mmreg(uMIPS_RS(ctx->opcode)); int encoded = ZIMM(ctx->opcode, 0, 4); - gen_logic_imm(env, ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); + gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); } static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, @@ -10831,7 +10831,7 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, } -static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_branch) +static void gen_pool16c_insn(DisasContext *ctx, int *is_branch) { int rd = mmreg((ctx->opcode >> 3) & 0x7); int rs = mmreg(ctx->opcode & 0x7); @@ -10842,25 +10842,25 @@ static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_bran case NOT16 + 1: case NOT16 + 2: case NOT16 + 3: - gen_logic(env, ctx, OPC_NOR, rd, rs, 0); + gen_logic(ctx, OPC_NOR, rd, rs, 0); break; case XOR16 + 0: case XOR16 + 1: case XOR16 + 2: case XOR16 + 3: - gen_logic(env, ctx, OPC_XOR, rd, rd, rs); + gen_logic(ctx, OPC_XOR, rd, rd, rs); break; case AND16 + 0: case AND16 + 1: case AND16 + 2: case AND16 + 3: - gen_logic(env, ctx, OPC_AND, rd, rd, rs); + gen_logic(ctx, OPC_AND, rd, rd, rs); break; case OR16 + 0: case OR16 + 1: case OR16 + 2: case OR16 + 3: - gen_logic(env, ctx, OPC_OR, rd, rd, rs); + gen_logic(ctx, OPC_OR, rd, rd, rs); break; case LWM16 + 0: case LWM16 + 1: @@ -10935,7 +10935,7 @@ static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_bran /* XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { generate_exception(ctx, EXCP_DBp); } else { @@ -10948,7 +10948,7 @@ static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_bran int imm = ZIMM(ctx->opcode, 0, 5); gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0); - gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, imm << 2); + gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); /* Let normal delay slot handling in our caller take us to the branch target. */ } @@ -11085,7 +11085,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, /* Treat as NOP. */ break; } - gen_mfc0(env, ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); + gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); break; case MTC0: case MTC0 + 32: @@ -11094,7 +11094,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rt); - gen_mtc0(env, ctx, t0, rs, (ctx->opcode >> 11) & 0x7); + gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); tcg_temp_free(t0); } break; @@ -11113,11 +11113,11 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, case CLZ: mips32_op = OPC_CLZ; do_cl: - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: - gen_rdhwr(env, ctx, rt, rs); + gen_rdhwr(ctx, rt, rs); break; case WSBH: gen_bshfl(ctx, OPC_WSBH, rs, rt); @@ -11146,7 +11146,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, case MSUBU: mips32_op = OPC_MSUBU; do_muldiv: - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); gen_muldiv(ctx, mips32_op, rs, rt); break; default: @@ -11187,12 +11187,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, switch (minor) { case RDPGPR: check_cp0_enabled(ctx); - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_load_srsgpr(rt, rs); break; case WRPGPR: check_cp0_enabled(ctx); - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_store_srsgpr(rt, rs); break; default: @@ -11272,7 +11272,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, ctx->bstate = BS_STOP; break; case SDBBP: - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { generate_exception(ctx, EXCP_DBp); } else { @@ -11329,7 +11329,7 @@ enum { FMT_DWL_L = 2 }; -static void gen_pool32fxf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) +static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) { int extension = (ctx->opcode >> 6) & 0x3ff; uint32_t mips32_op; @@ -11614,7 +11614,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case ROTR: mips32_op = OPC_ROTR; do_shifti: - gen_shift_imm(env, ctx, mips32_op, rt, rs, rd); + gen_shift_imm(ctx, mips32_op, rt, rs, rd); break; default: goto pool32a_invalid; @@ -11639,7 +11639,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case MUL: mips32_op = OPC_MUL; do_arith: - gen_arith(env, ctx, mips32_op, rd, rs, rt); + gen_arith(ctx, mips32_op, rd, rs, rt); break; /* Shifts */ case SLLV: @@ -11654,7 +11654,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case ROTRV: mips32_op = OPC_ROTRV; do_shift: - gen_shift(env, ctx, mips32_op, rd, rs, rt); + gen_shift(ctx, mips32_op, rd, rs, rt); break; /* Logical operations */ case AND: @@ -11669,7 +11669,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case XOR32: mips32_op = OPC_XOR; do_logic: - gen_logic(env, ctx, mips32_op, rd, rs, rt); + gen_logic(ctx, mips32_op, rd, rs, rt); break; /* Set less than */ case SLT: @@ -11678,7 +11678,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case SLTU: mips32_op = OPC_SLTU; do_slt: - gen_slt(env, ctx, mips32_op, rd, rs, rt); + gen_slt(ctx, mips32_op, rd, rs, rt); break; default: goto pool32a_invalid; @@ -11694,7 +11694,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case MOVZ: mips32_op = OPC_MOVZ; do_cmov: - gen_cond_move(env, ctx, mips32_op, rd, rs, rt); + gen_cond_move(ctx, mips32_op, rd, rs, rt); break; case LWXS: gen_ldxs(ctx, rs, rt, rd); @@ -11839,7 +11839,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, } break; case POOL32FXF: - gen_pool32fxf(env, ctx, rt, rs); + gen_pool32fxf(ctx, rt, rs); break; case 0x00: /* PLL foo */ @@ -12107,7 +12107,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, target. */ break; case LUI: - gen_logic_imm(env, ctx, OPC_LUI, rs, -1, imm); + gen_logic_imm(ctx, OPC_LUI, rs, -1, imm); break; case SYNCI: break; @@ -12129,10 +12129,10 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, mips32_op = OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); - check_insn(env, ctx, ASE_MIPS3D); + check_insn(ctx, ASE_MIPS3D); /* Fall through */ do_cp1branch: - gen_compute_branch1(env, ctx, mips32_op, + gen_compute_branch1(ctx, mips32_op, (ctx->opcode >> 18) & 0x7, imm << 1); *is_branch = 1; break; @@ -12185,7 +12185,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, mips32_op = OPC_LL; goto do_ld_lr; do_ld_lr: - gen_ld(env, ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); + gen_ld(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); break; do_st_lr: gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); @@ -12213,7 +12213,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case ADDIU32: mips32_op = OPC_ADDIU; do_addi: - gen_arith_imm(env, ctx, mips32_op, rt, rs, imm); + gen_arith_imm(ctx, mips32_op, rt, rs, imm); break; /* Logical operations */ @@ -12226,7 +12226,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case ANDI32: mips32_op = OPC_ANDI; do_logici: - gen_logic_imm(env, ctx, mips32_op, rt, rs, imm); + gen_logic_imm(ctx, mips32_op, rt, rs, imm); break; /* Set less than immediate */ @@ -12236,7 +12236,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case SLTIU32: mips32_op = OPC_SLTIU; do_slti: - gen_slt_imm(env, ctx, mips32_op, rt, rs, imm); + gen_slt_imm(ctx, mips32_op, rt, rs, imm); break; case JALX32: offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; @@ -12323,7 +12323,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, mips32_op = OPC_SW; goto do_st; do_ld: - gen_ld(env, ctx, mips32_op, rt, rs, imm); + gen_ld(ctx, mips32_op, rt, rs, imm); break; do_st: gen_st(ctx, mips32_op, rt, rs, imm); @@ -12443,7 +12443,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b break; } - gen_arith(env, ctx, opc, rd, rs1, rs2); + gen_arith(ctx, opc, rd, rs1, rs2); } break; case POOL16B: @@ -12463,11 +12463,11 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b break; } - gen_shift_imm(env, ctx, opc, rd, rs, amount); + gen_shift_imm(ctx, opc, rd, rs, amount); } break; case POOL16C: - gen_pool16c_insn(env, ctx, is_branch); + gen_pool16c_insn(ctx, is_branch); break; case LWGP16: { @@ -12475,7 +12475,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b int rb = 28; /* GP */ int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; - gen_ld(env, ctx, OPC_LW, rd, rb, offset); + gen_ld(ctx, OPC_LW, rd, rb, offset); } break; case POOL16F: @@ -12496,8 +12496,8 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b rs = rs_rt_enc[enc_rs]; rt = rs_rt_enc[enc_rt]; - gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, 0); - gen_arith_imm(env, ctx, OPC_ADDIU, re, rt, 0); + gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0); + gen_arith_imm(ctx, OPC_ADDIU, re, rt, 0); } break; case LBU16: @@ -12507,7 +12507,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b int16_t offset = ZIMM(ctx->opcode, 0, 4); offset = (offset == 0xf ? -1 : offset); - gen_ld(env, ctx, OPC_LBU, rd, rb, offset); + gen_ld(ctx, OPC_LBU, rd, rb, offset); } break; case LHU16: @@ -12516,7 +12516,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b int rb = mmreg(uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; - gen_ld(env, ctx, OPC_LHU, rd, rb, offset); + gen_ld(ctx, OPC_LHU, rd, rb, offset); } break; case LWSP16: @@ -12525,7 +12525,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b int rb = 29; /* SP */ int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; - gen_ld(env, ctx, OPC_LW, rd, rb, offset); + gen_ld(ctx, OPC_LW, rd, rb, offset); } break; case LW16: @@ -12534,7 +12534,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b int rb = mmreg(uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; - gen_ld(env, ctx, OPC_LW, rd, rb, offset); + gen_ld(ctx, OPC_LW, rd, rb, offset); } break; case SB16: @@ -12578,29 +12578,29 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b int rd = uMIPS_RD5(ctx->opcode); int rs = uMIPS_RS5(ctx->opcode); - gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, 0); + gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0); } break; case ANDI16: - gen_andi16(env, ctx); + gen_andi16(ctx); break; case POOL16D: switch (ctx->opcode & 0x1) { case ADDIUS5: - gen_addius5(env, ctx); + gen_addius5(ctx); break; case ADDIUSP: - gen_addiusp(env, ctx); + gen_addiusp(ctx); break; } break; case POOL16E: switch (ctx->opcode & 0x1) { case ADDIUR2: - gen_addiur2(env, ctx); + gen_addiur2(ctx); break; case ADDIUR1SP: - gen_addiur1sp(env, ctx); + gen_addiur1sp(ctx); break; } break; @@ -12651,7 +12651,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b #endif /* MIPSDSP functions. */ -static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, +static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc, int rd, int base, int offset) { const char *opn = "ldx"; @@ -13712,8 +13712,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, } -static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx, - uint32_t op1, uint32_t op2, +static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, int ret, int val) { const char *opn = "mipsdsp Bit/ Manipulation"; @@ -14367,18 +14366,18 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) switch (op1) { case OPC_SLL: /* Shift with immediate */ case OPC_SRA: - gen_shift_imm(env, ctx, op1, rd, rt, sa); + gen_shift_imm(ctx, op1, rd, rt, sa); break; case OPC_SRL: switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* rotr is decoded as srl on non-R2 CPUs */ - if (env->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS32R2) { op1 = OPC_ROTR; } /* Fallthrough */ case 0: - gen_shift_imm(env, ctx, op1, rd, rt, sa); + gen_shift_imm(ctx, op1, rd, rt, sa); break; default: generate_exception(ctx, EXCP_RI); @@ -14387,27 +14386,27 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: - check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32 | + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | INSN_LOONGSON2E | INSN_LOONGSON2F); - gen_cond_move(env, ctx, op1, rd, rs, rt); + gen_cond_move(ctx, op1, rd, rs, rt); break; case OPC_ADD ... OPC_SUBU: - gen_arith(env, ctx, op1, rd, rs, rt); + gen_arith(ctx, op1, rd, rs, rt); break; case OPC_SLLV: /* Shifts */ case OPC_SRAV: - gen_shift(env, ctx, op1, rd, rs, rt); + gen_shift(ctx, op1, rd, rs, rt); break; case OPC_SRLV: switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* rotrv is decoded as srlv on non-R2 CPUs */ - if (env->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS32R2) { op1 = OPC_ROTRV; } /* Fallthrough */ case 0: - gen_shift(env, ctx, op1, rd, rs, rt); + gen_shift(ctx, op1, rd, rs, rt); break; default: generate_exception(ctx, EXCP_RI); @@ -14416,17 +14415,17 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_SLT: /* Set on less than */ case OPC_SLTU: - gen_slt(env, ctx, op1, rd, rs, rt); + gen_slt(ctx, op1, rd, rs, rt); break; case OPC_AND: /* Logic*/ case OPC_OR: case OPC_NOR: case OPC_XOR: - gen_logic(env, ctx, op1, rd, rs, rt); + gen_logic(ctx, op1, rd, rs, rt); break; case OPC_MULT ... OPC_DIVU: if (sa) { - check_insn(env, ctx, INSN_VR54XX); + check_insn(ctx, INSN_VR54XX); op1 = MASK_MUL_VR54XX(ctx->opcode); gen_mul_vr54xx(ctx, op1, rd, rs, rt); } else @@ -14478,7 +14477,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_MOVCI: - check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); if (env->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, @@ -14494,22 +14493,22 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_DSRA: case OPC_DSLL32: case OPC_DSRA32: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_shift_imm(env, ctx, op1, rd, rt, sa); + gen_shift_imm(ctx, op1, rd, rt, sa); break; case OPC_DSRL: switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr is decoded as dsrl on non-R2 CPUs */ - if (env->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS32R2) { op1 = OPC_DROTR; } /* Fallthrough */ case 0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_shift_imm(env, ctx, op1, rd, rt, sa); + gen_shift_imm(ctx, op1, rd, rt, sa); break; default: generate_exception(ctx, EXCP_RI); @@ -14520,14 +14519,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ - if (env->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS32R2) { op1 = OPC_DROTR32; } /* Fallthrough */ case 0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_shift_imm(env, ctx, op1, rd, rt, sa); + gen_shift_imm(ctx, op1, rd, rt, sa); break; default: generate_exception(ctx, EXCP_RI); @@ -14535,28 +14534,28 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } break; case OPC_DADD ... OPC_DSUBU: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_arith(env, ctx, op1, rd, rs, rt); + gen_arith(ctx, op1, rd, rs, rt); break; case OPC_DSLLV: case OPC_DSRAV: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_shift(env, ctx, op1, rd, rs, rt); + gen_shift(ctx, op1, rd, rs, rt); break; case OPC_DSRLV: switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* drotrv is decoded as dsrlv on non-R2 CPUs */ - if (env->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS32R2) { op1 = OPC_DROTRV; } /* Fallthrough */ case 0: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_shift(env, ctx, op1, rd, rs, rt); + gen_shift(ctx, op1, rd, rs, rt); break; default: generate_exception(ctx, EXCP_RI); @@ -14564,7 +14563,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } break; case OPC_DMULT ... OPC_DDIVU: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_muldiv(ctx, op1, rs, rt); break; @@ -14580,22 +14579,22 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) switch (op1) { case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */ case OPC_MSUB ... OPC_MSUBU: - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); gen_muldiv(ctx, op1, rs, rt); break; case OPC_MUL: - gen_arith(env, ctx, op1, rd, rs, rt); + gen_arith(ctx, op1, rd, rs, rt); break; case OPC_CLO: case OPC_CLZ: - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: /* XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(env, ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { generate_exception(ctx, EXCP_DBp); } else { @@ -14609,13 +14608,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_MULTU_G_2F: case OPC_MOD_G_2F: case OPC_MODU_G_2F: - check_insn(env, ctx, INSN_LOONGSON2F); + check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(env, ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS64); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; @@ -14625,7 +14624,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_DDIVU_G_2F: case OPC_DMOD_G_2F: case OPC_DMODU_G_2F: - check_insn(env, ctx, INSN_LOONGSON2F); + check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; #endif @@ -14640,19 +14639,19 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) switch (op1) { case OPC_EXT: case OPC_INS: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_BSHFL: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); op2 = MASK_BSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); break; case OPC_RDHWR: - gen_rdhwr(env, ctx, rt, rd); + gen_rdhwr(ctx, rt, rd); break; case OPC_FORK: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -14665,7 +14664,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } break; case OPC_YIELD: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); { TCGv t0 = tcg_temp_new(); @@ -14681,7 +14680,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_MULT_G_2E ... OPC_MULTU_G_2E: /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ - if ((env->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) { + if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) { op2 = MASK_ADDUH_QB(ctx->opcode); switch (op2) { case OPC_ADDUH_QB: @@ -14709,7 +14708,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) generate_exception(ctx, EXCP_RI); break; } - } else if (env->insn_flags & INSN_LOONGSON2E) { + } else if (ctx->insn_flags & INSN_LOONGSON2E) { gen_loongson_integer(ctx, op1, rd, rs, rt); } else { generate_exception(ctx, EXCP_RI); @@ -14724,7 +14723,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_LBUX: case OPC_LHX: case OPC_LWX: - gen_mipsdsp_ld(env, ctx, op2, rd, rs, rt); + gen_mipsdsp_ld(ctx, op2, rd, rs, rt); break; default: /* Invalid */ MIPS_INVAL("MASK LX"); @@ -14755,7 +14754,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_REPLV_QB: case OPC_REPL_PH: case OPC_REPLV_PH: - gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt); + gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); break; default: MIPS_INVAL("MASK ABSQ_S.PH"); @@ -14947,12 +14946,12 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: - check_insn(env, ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS64R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_DBSHFL: - check_insn(env, ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS64R2); check_mips_64(ctx); op2 = MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); @@ -14960,7 +14959,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E: case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E: case OPC_DMOD_G_2E ... OPC_DMODU_G_2E: - check_insn(env, ctx, INSN_LOONGSON2E); + check_insn(ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; case OPC_ABSQ_S_QH_DSP: @@ -14991,7 +14990,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_REPLV_OB: case OPC_REPLV_PW: case OPC_REPLV_QH: - gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt); + gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); break; default: /* Invalid */ MIPS_INVAL("MASK ABSQ_S.QH"); @@ -15212,7 +15211,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) gen_trap(ctx, op1, rs, -1, imm); break; case OPC_SYNCI: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); /* Treat as NOP. */ break; case OPC_BPOSGE32: /* MIPS DSP branch */ @@ -15258,27 +15257,27 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) op2 = MASK_MFMC0(ctx->opcode); switch (op2) { case OPC_DMT: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dmt(t0); gen_store_gpr(t0, rt); break; case OPC_EMT: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_emt(t0); gen_store_gpr(t0, rt); break; case OPC_DVPE: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); break; case OPC_EVPE: - check_insn(env, ctx, ASE_MT); + check_insn(ctx, ASE_MT); gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); break; case OPC_DI: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); save_cpu_state(ctx, 1); gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rt); @@ -15286,7 +15285,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) ctx->bstate = BS_STOP; break; case OPC_EI: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); @@ -15303,11 +15302,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) #endif /* !CONFIG_USER_ONLY */ break; case OPC_RDPGPR: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_load_srsgpr(rt, rd); break; case OPC_WRPGPR: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); gen_store_srsgpr(rt, rd); break; default: @@ -15318,17 +15317,17 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_ADDI: /* Arithmetic with immediate opcode */ case OPC_ADDIU: - gen_arith_imm(env, ctx, op, rt, rs, imm); + gen_arith_imm(ctx, op, rt, rs, imm); break; case OPC_SLTI: /* Set on less than with immediate opcode */ case OPC_SLTIU: - gen_slt_imm(env, ctx, op, rt, rs, imm); + gen_slt_imm(ctx, op, rt, rs, imm); break; case OPC_ANDI: /* Arithmetic with immediate opcode */ case OPC_LUI: case OPC_ORI: case OPC_XORI: - gen_logic_imm(env, ctx, op, rt, rs, imm); + gen_logic_imm(ctx, op, rt, rs, imm); break; case OPC_J ... OPC_JAL: /* Jump */ offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; @@ -15342,7 +15341,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_LB ... OPC_LWR: /* Load and stores */ case OPC_LL: - gen_ld(env, ctx, op, rt, rs, imm); + gen_ld(ctx, op, rt, rs, imm); break; case OPC_SB ... OPC_SW: case OPC_SWR: @@ -15353,11 +15352,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_CACHE: check_cp0_enabled(ctx); - check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); /* Treat as NOP. */ break; case OPC_PREF: - check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); /* Treat as NOP. */ break; @@ -15376,7 +15375,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) switch (op1) { case OPC_MFHC1: case OPC_MTHC1: - check_insn(env, ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS32R2); case OPC_MFC1: case OPC_CFC1: case OPC_MTC1: @@ -15386,17 +15385,17 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) #if defined(TARGET_MIPS64) case OPC_DMFC1: case OPC_DMTC1: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); gen_cp1(ctx, op1, rt, rd); break; #endif case OPC_BC1ANY2: case OPC_BC1ANY4: check_cop1x(ctx); - check_insn(env, ctx, ASE_MIPS3D); + check_insn(ctx, ASE_MIPS3D); /* fall through */ case OPC_BC1: - gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), + gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); *is_branch = 1; break; @@ -15427,7 +15426,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) generate_exception_err(ctx, EXCP_CpU, 2); break; case OPC_CP2: - check_insn(env, ctx, INSN_LOONGSON2F); + check_insn(ctx, INSN_LOONGSON2F); /* Note that these instructions use different fields. */ gen_loongson_multimedia(ctx, sa, rd, rt); break; @@ -15479,36 +15478,36 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_LDL ... OPC_LDR: case OPC_LLD: case OPC_LD: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_ld(env, ctx, op, rt, rs, imm); + gen_ld(ctx, op, rt, rs, imm); break; case OPC_SDL ... OPC_SDR: case OPC_SD: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_st(ctx, op, rt, rs, imm); break; case OPC_SCD: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_st_cond(ctx, op, rt, rs, imm); break; case OPC_DADDI: case OPC_DADDIU: - check_insn(env, ctx, ISA_MIPS3); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_arith_imm(env, ctx, op, rt, rs, imm); + gen_arith_imm(ctx, op, rt, rs, imm); break; #endif case OPC_JALX: - check_insn(env, ctx, ASE_MIPS16 | ASE_MICROMIPS); + check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS); offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, op, 4, rs, rt, offset); *is_branch = 1; break; case OPC_MDMX: - check_insn(env, ctx, ASE_MDMX); + check_insn(ctx, ASE_MDMX); /* MDMX: Not implemented. */ default: /* Invalid */ MIPS_INVAL("major opcode"); @@ -15539,6 +15538,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, ctx.pc = pc_start; ctx.saved_pc = -1; ctx.singlestep_enabled = env->singlestep_enabled; + ctx.insn_flags = env->insn_flags; ctx.tb = tb; ctx.bstate = BS_NONE; /* Restore delay slot state from the tb context. */ @@ -15591,10 +15591,10 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, ctx.opcode = cpu_ldl_code(env, ctx.pc); insn_bytes = 4; decode_opc(env, &ctx, &is_branch); - } else if (env->insn_flags & ASE_MICROMIPS) { + } else if (ctx.insn_flags & ASE_MICROMIPS) { ctx.opcode = cpu_lduw_code(env, ctx.pc); insn_bytes = decode_micromips_opc(env, &ctx, &is_branch); - } else if (env->insn_flags & ASE_MIPS16) { + } else if (ctx.insn_flags & ASE_MIPS16) { ctx.opcode = cpu_lduw_code(env, ctx.pc); insn_bytes = decode_mips16_opc(env, &ctx, &is_branch); } else { @@ -15603,7 +15603,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, break; } if (!is_branch) { - handle_delay_slot(env, &ctx, insn_bytes); + handle_delay_slot(&ctx, insn_bytes); } ctx.pc += insn_bytes; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 2/8] target-mips: copy insn_flags in DisasContext Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements Aurelien Jarno ` (6 subsequent siblings) 9 siblings, 0 replies; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno On CPU without DSP ASE support, a reserved instruction exception (instead of a DSP ASE sate disabled) should be generated. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/translate.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 33d04fb..2c238ef 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1394,14 +1394,22 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) static inline void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } } static inline void check_dspr2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (2 preceding siblings ...) 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators Aurelien Jarno ` (5 subsequent siblings) 9 siblings, 0 replies; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno Instead of playing with bit shifting, add two unions (one for 32-bit values, one for 64-bit ones) to access all the DSP elements with the correct type. This make the code easier to read and less error prone, and allow GCC to vectorize the code in some cases. Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/dsp_helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 4870e3d..aed4c63 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -20,6 +20,28 @@ #include "cpu.h" #include "helper.h" +/* As the byte ordering doesn't matter, i.e. all columns are treated + identically, these unions can be used directly. */ +typedef union { + uint8_t ub[4]; + int8_t sb[4]; + uint16_t uh[2]; + int16_t sh[2]; + uint32_t uw[1]; + int32_t sw[1]; +} DSP32Value; + +typedef union { + uint8_t ub[8]; + int8_t sb[8]; + uint16_t uh[4]; + int16_t sh[4]; + uint32_t uw[2]; + int32_t sw[2]; + uint64_t ul[1]; + int64_t sl[1]; +} DSP64Value; + /*** MIPS DSP internal functions begin ***/ #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x) #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d))) -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (3 preceding siblings ...) 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 21:16 ` Blue Swirl 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 6/8] target-mips: use DSP unions for unary " Aurelien Jarno ` (4 subsequent siblings) 9 siblings, 1 reply; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno This allow to reduce the number of macros. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/dsp_helper.c | 384 ++++++++++++++-------------------------------- 1 file changed, 116 insertions(+), 268 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index aed4c63..e01c8a9 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -1078,7 +1078,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) b = num & MIPSDSP_LO; \ } while (0) -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ (((uint32_t)a << 24) | \ (((uint32_t)b << 16) | \ @@ -1111,119 +1110,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) #endif /** DSP Arithmetic Sub-class insns **/ -#define ARITH_PH(name, func) \ -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ -{ \ - uint16_t rsh, rsl, rth, rtl, temph, templ; \ - \ - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ - \ - temph = mipsdsp_##func(rsh, rth); \ - templ = mipsdsp_##func(rsl, rtl); \ - \ - return MIPSDSP_RETURN32_16(temph, templ); \ -} - -#define ARITH_PH_ENV(name, func) \ -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - uint16_t rsh, rsl, rth, rtl, temph, templ; \ - \ - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ - \ - temph = mipsdsp_##func(rsh, rth, env); \ - templ = mipsdsp_##func(rsl, rtl, env); \ - \ - return MIPSDSP_RETURN32_16(temph, templ); \ -} - - -ARITH_PH_ENV(addq, add_i16); -ARITH_PH_ENV(addq_s, sat_add_i16); -ARITH_PH_ENV(addu, add_u16); -ARITH_PH_ENV(addu_s, sat_add_u16); - -ARITH_PH(addqh, rshift1_add_q16); -ARITH_PH(addqh_r, rrshift1_add_q16); - -ARITH_PH_ENV(subq, sub_i16); -ARITH_PH_ENV(subq_s, sat16_sub); -ARITH_PH_ENV(subu, sub_u16_u16); -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); - -ARITH_PH(subqh, rshift1_sub_q16); -ARITH_PH(subqh_r, rrshift1_sub_q16); - -#undef ARITH_PH -#undef ARITH_PH_ENV +#define MIPSDSP32_BINOP(name, func, element) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ +{ \ + DSP32Value ds, dt; \ + unsigned int i, n; \ + \ + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ + ds.sw[0] = rs; \ + dt.sw[0] = rt; \ + \ + for (i = 0 ; i < n ; i++) { \ + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \ + } \ + \ + return (target_long)ds.sw[0]; \ +} +MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh); +MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh); +MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw); +MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw); +MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub); +MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub); +MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh); +MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh); +MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw); +MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw); +#undef MIPSDSP32_BINOP + +#define MIPSDSP32_BINOP_ENV(name, func, element) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + DSP32Value ds, dt; \ + unsigned int i, n; \ + \ + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ + ds.sw[0] = rs; \ + dt.sw[0] = rt; \ + \ + for (i = 0 ; i < n ; i++) { \ + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \ + } \ + \ + return (target_long)ds.sw[0]; \ +} +MIPSDSP32_BINOP_ENV(addq_ph, add_i16, sh) +MIPSDSP32_BINOP_ENV(addq_s_ph, sat_add_i16, sh) +MIPSDSP32_BINOP_ENV(addq_s_w, sat_add_i32, sw); +MIPSDSP32_BINOP_ENV(addu_ph, add_u16, sh) +MIPSDSP32_BINOP_ENV(addu_qb, add_u8, ub); +MIPSDSP32_BINOP_ENV(addu_s_ph, sat_add_u16, sh) +MIPSDSP32_BINOP_ENV(addu_s_qb, sat_add_u8, ub); +MIPSDSP32_BINOP_ENV(subq_ph, sub_i16, sh); +MIPSDSP32_BINOP_ENV(subq_s_ph, sat16_sub, sh); +MIPSDSP32_BINOP_ENV(subq_s_w, sat32_sub, sw); +MIPSDSP32_BINOP_ENV(subu_ph, sub_u16_u16, sh); +MIPSDSP32_BINOP_ENV(subu_qb, sub_u8, ub); +MIPSDSP32_BINOP_ENV(subu_s_ph, satu16_sub_u16_u16, sh); +MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub); +#undef MIPSDSP32_BINOP_ENV #ifdef TARGET_MIPS64 -#define ARITH_QH_ENV(name, func) \ -target_ulong helper_##name##_qh(target_ulong rs, target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - uint16_t rs3, rs2, rs1, rs0; \ - uint16_t rt3, rt2, rt1, rt0; \ - uint16_t tempD, tempC, tempB, tempA; \ - \ - MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ - MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ - \ - tempD = mipsdsp_##func(rs3, rt3, env); \ - tempC = mipsdsp_##func(rs2, rt2, env); \ - tempB = mipsdsp_##func(rs1, rt1, env); \ - tempA = mipsdsp_##func(rs0, rt0, env); \ - \ - return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ -} - -ARITH_QH_ENV(addq, add_i16); -ARITH_QH_ENV(addq_s, sat_add_i16); -ARITH_QH_ENV(addu, add_u16); -ARITH_QH_ENV(addu_s, sat_add_u16); - -ARITH_QH_ENV(subq, sub_i16); -ARITH_QH_ENV(subq_s, sat16_sub); -ARITH_QH_ENV(subu, sub_u16_u16); -ARITH_QH_ENV(subu_s, satu16_sub_u16_u16); - -#undef ARITH_QH_ENV +#define MIPSDSP64_BINOP(name, func, element) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ +{ \ + DSP64Value ds, dt; \ + unsigned int i, n; \ + \ + n = sizeof(DSP64Value) / sizeof(ds.element[0]); \ + ds.sl[0] = rs; \ + dt.sl[0] = rt; \ + \ + for (i = 0 ; i < n ; i++) { \ + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \ + } \ + \ + return ds.sl[0]; \ +} +MIPSDSP64_BINOP(adduh_ob, rshift1_add_u8, ub); +MIPSDSP64_BINOP(adduh_r_ob, rrshift1_add_u8, ub); +MIPSDSP64_BINOP(subuh_ob, rshift1_sub_u8, ub); +MIPSDSP64_BINOP(subuh_r_ob, rrshift1_sub_u8, ub); +#undef MIPSDSP64_BINOP + +#define MIPSDSP64_BINOP_ENV(name, func, element) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + DSP64Value ds, dt; \ + unsigned int i, n; \ + \ + n = sizeof(DSP64Value) / sizeof(ds.element[0]); \ + ds.sl[0] = rs; \ + dt.sl[0] = rt; \ + \ + for (i = 0 ; i < n ; i++) { \ + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \ + } \ + \ + return ds.sl[0]; \ +} +MIPSDSP64_BINOP_ENV(addq_pw, add_i32, sw); +MIPSDSP64_BINOP_ENV(addq_qh, add_i16, sh); +MIPSDSP64_BINOP_ENV(addq_s_pw, sat_add_i32, sw); +MIPSDSP64_BINOP_ENV(addq_s_qh, sat_add_i16, sh); +MIPSDSP64_BINOP_ENV(addu_ob, add_u8, uh); +MIPSDSP64_BINOP_ENV(addu_qh, add_u16, uh); +MIPSDSP64_BINOP_ENV(addu_s_ob, sat_add_u8, uh); +MIPSDSP64_BINOP_ENV(addu_s_qh, sat_add_u16, uh); +MIPSDSP64_BINOP_ENV(subq_pw, sub32, sw); +MIPSDSP64_BINOP_ENV(subq_qh, sub_i16, sh); +MIPSDSP64_BINOP_ENV(subq_s_pw, sat32_sub, sw); +MIPSDSP64_BINOP_ENV(subq_s_qh, sat16_sub, sh); +MIPSDSP64_BINOP_ENV(subu_ob, sub_u8, uh); +MIPSDSP64_BINOP_ENV(subu_qh, sub_u16_u16, uh); +MIPSDSP64_BINOP_ENV(subu_s_ob, satu8_sub, uh); +MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh); +#undef MIPSDSP64_BINOP_ENV #endif -#define ARITH_W(name, func) \ -target_ulong helper_##name##_w(target_ulong rs, target_ulong rt) \ -{ \ - uint32_t rd; \ - rd = mipsdsp_##func(rs, rt); \ - return MIPSDSP_RETURN32(rd); \ -} - -#define ARITH_W_ENV(name, func) \ -target_ulong helper_##name##_w(target_ulong rs, target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - uint32_t rd; \ - rd = mipsdsp_##func(rs, rt, env); \ - return MIPSDSP_RETURN32(rd); \ -} - -ARITH_W_ENV(addq_s, sat_add_i32); - -ARITH_W(addqh, rshift1_add_q32); -ARITH_W(addqh_r, rrshift1_add_q32); - -ARITH_W_ENV(subq_s, sat32_sub); - -ARITH_W(subqh, rshift1_sub_q32); -ARITH_W(subqh_r, rrshift1_sub_q32); - -#undef ARITH_W -#undef ARITH_W_ENV - target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) { uint32_t rd; @@ -1234,164 +1241,6 @@ target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) } -#if defined(TARGET_MIPS64) - -#define ARITH_PW_ENV(name, func) \ -target_ulong helper_##name##_pw(target_ulong rs, target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - uint32_t rs1, rs0; \ - uint32_t rt1, rt0; \ - uint32_t tempB, tempA; \ - \ - MIPSDSP_SPLIT64_32(rs, rs1, rs0); \ - MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ - \ - tempB = mipsdsp_##func(rs1, rt1, env); \ - tempA = mipsdsp_##func(rs0, rt0, env); \ - \ - return MIPSDSP_RETURN64_32(tempB, tempA); \ -} - -ARITH_PW_ENV(addq, add_i32); -ARITH_PW_ENV(addq_s, sat_add_i32); -ARITH_PW_ENV(subq, sub32); -ARITH_PW_ENV(subq_s, sat32_sub); - -#undef ARITH_PW_ENV - -#endif - -#define ARITH_QB(name, func) \ -target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ -{ \ - uint8_t rs0, rs1, rs2, rs3; \ - uint8_t rt0, rt1, rt2, rt3; \ - uint8_t temp0, temp1, temp2, temp3; \ - \ - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ - MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ - \ - temp0 = mipsdsp_##func(rs0, rt0); \ - temp1 = mipsdsp_##func(rs1, rt1); \ - temp2 = mipsdsp_##func(rs2, rt2); \ - temp3 = mipsdsp_##func(rs3, rt3); \ - \ - return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \ -} - -#define ARITH_QB_ENV(name, func) \ -target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - uint8_t rs0, rs1, rs2, rs3; \ - uint8_t rt0, rt1, rt2, rt3; \ - uint8_t temp0, temp1, temp2, temp3; \ - \ - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ - MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ - \ - temp0 = mipsdsp_##func(rs0, rt0, env); \ - temp1 = mipsdsp_##func(rs1, rt1, env); \ - temp2 = mipsdsp_##func(rs2, rt2, env); \ - temp3 = mipsdsp_##func(rs3, rt3, env); \ - \ - return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \ -} - -ARITH_QB(adduh, rshift1_add_u8); -ARITH_QB(adduh_r, rrshift1_add_u8); - -ARITH_QB_ENV(addu, add_u8); -ARITH_QB_ENV(addu_s, sat_add_u8); - -#undef ADDU_QB -#undef ADDU_QB_ENV - -#if defined(TARGET_MIPS64) -#define ARITH_OB(name, func) \ -target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt) \ -{ \ - int i; \ - uint8_t rs_t[8], rt_t[8]; \ - uint8_t temp[8]; \ - uint64_t result; \ - \ - result = 0; \ - \ - for (i = 0; i < 8; i++) { \ - rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ - rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ - temp[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \ - result |= (uint64_t)temp[i] << (8 * i); \ - } \ - \ - return result; \ -} - -#define ARITH_OB_ENV(name, func) \ -target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - int i; \ - uint8_t rs_t[8], rt_t[8]; \ - uint8_t temp[8]; \ - uint64_t result; \ - \ - result = 0; \ - \ - for (i = 0; i < 8; i++) { \ - rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ - rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ - temp[i] = mipsdsp_##func(rs_t[i], rt_t[i], env); \ - result |= (uint64_t)temp[i] << (8 * i); \ - } \ - \ - return result; \ -} - -ARITH_OB_ENV(addu, add_u8); -ARITH_OB_ENV(addu_s, sat_add_u8); - -ARITH_OB(adduh, rshift1_add_u8); -ARITH_OB(adduh_r, rrshift1_add_u8); - -ARITH_OB_ENV(subu, sub_u8); -ARITH_OB_ENV(subu_s, satu8_sub); - -ARITH_OB(subuh, rshift1_sub_u8); -ARITH_OB(subuh_r, rrshift1_sub_u8); - -#undef ARITH_OB -#undef ARITH_OB_ENV - -#endif - -#define SUBU_QB(name, func) \ -target_ulong helper_##name##_qb(target_ulong rs, \ - target_ulong rt, \ - CPUMIPSState *env) \ -{ \ - uint8_t rs3, rs2, rs1, rs0; \ - uint8_t rt3, rt2, rt1, rt0; \ - uint8_t tempD, tempC, tempB, tempA; \ - \ - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ - MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ - \ - tempD = mipsdsp_##func(rs3, rt3, env); \ - tempC = mipsdsp_##func(rs2, rt2, env); \ - tempB = mipsdsp_##func(rs1, rt1, env); \ - tempA = mipsdsp_##func(rs0, rt0, env); \ - \ - return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \ -} - -SUBU_QB(subu, sub_u8); -SUBU_QB(subu_s, satu8_sub); - -#undef SUBU_QB - #define SUBUH_QB(name, var) \ target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ { \ @@ -4027,7 +3876,6 @@ target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env) #undef MIPSDSP_SPLIT32_8 #undef MIPSDSP_SPLIT32_16 -#undef MIPSDSP_RETURN32 #undef MIPSDSP_RETURN32_8 #undef MIPSDSP_RETURN32_16 -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators Aurelien Jarno @ 2013-01-09 21:16 ` Blue Swirl 2013-01-10 7:08 ` Aurelien Jarno 0 siblings, 1 reply; 18+ messages in thread From: Blue Swirl @ 2013-01-09 21:16 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > This allow to reduce the number of macros. > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > target-mips/dsp_helper.c | 384 ++++++++++++++-------------------------------- > 1 file changed, 116 insertions(+), 268 deletions(-) > > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c > index aed4c63..e01c8a9 100644 > --- a/target-mips/dsp_helper.c > +++ b/target-mips/dsp_helper.c > @@ -1078,7 +1078,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > b = num & MIPSDSP_LO; \ > } while (0) > > -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) > #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ > (((uint32_t)a << 24) | \ > (((uint32_t)b << 16) | \ > @@ -1111,119 +1110,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > #endif > > /** DSP Arithmetic Sub-class insns **/ > -#define ARITH_PH(name, func) \ > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ > -{ \ > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ > - \ > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ > - \ > - temph = mipsdsp_##func(rsh, rth); \ > - templ = mipsdsp_##func(rsl, rtl); \ > - \ > - return MIPSDSP_RETURN32_16(temph, templ); \ > -} > - > -#define ARITH_PH_ENV(name, func) \ > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ > - \ > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ > - \ > - temph = mipsdsp_##func(rsh, rth, env); \ > - templ = mipsdsp_##func(rsl, rtl, env); \ > - \ > - return MIPSDSP_RETURN32_16(temph, templ); \ > -} > - > - > -ARITH_PH_ENV(addq, add_i16); > -ARITH_PH_ENV(addq_s, sat_add_i16); > -ARITH_PH_ENV(addu, add_u16); > -ARITH_PH_ENV(addu_s, sat_add_u16); > - > -ARITH_PH(addqh, rshift1_add_q16); > -ARITH_PH(addqh_r, rrshift1_add_q16); > - > -ARITH_PH_ENV(subq, sub_i16); > -ARITH_PH_ENV(subq_s, sat16_sub); > -ARITH_PH_ENV(subu, sub_u16_u16); > -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); > - > -ARITH_PH(subqh, rshift1_sub_q16); > -ARITH_PH(subqh_r, rrshift1_sub_q16); > - > -#undef ARITH_PH > -#undef ARITH_PH_ENV > +#define MIPSDSP32_BINOP(name, func, element) \ > +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ > +{ \ > + DSP32Value ds, dt; \ > + unsigned int i, n; \ > + \ > + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ > + ds.sw[0] = rs; \ > + dt.sw[0] = rt; \ > + \ > + for (i = 0 ; i < n ; i++) { \ There's an extra space before ';', please remove. Also in the other for loops below. > + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \ > + } \ > + \ > + return (target_long)ds.sw[0]; \ > +} > +MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh); > +MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh); > +MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw); > +MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw); > +MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub); > +MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub); > +MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh); > +MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh); > +MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw); > +MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw); > +#undef MIPSDSP32_BINOP > + > +#define MIPSDSP32_BINOP_ENV(name, func, element) \ > +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ > + CPUMIPSState *env) \ > +{ \ > + DSP32Value ds, dt; \ > + unsigned int i, n; \ > + \ > + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ > + ds.sw[0] = rs; \ > + dt.sw[0] = rt; \ > + \ > + for (i = 0 ; i < n ; i++) { \ > + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \ > + } \ > + \ > + return (target_long)ds.sw[0]; \ > +} > +MIPSDSP32_BINOP_ENV(addq_ph, add_i16, sh) > +MIPSDSP32_BINOP_ENV(addq_s_ph, sat_add_i16, sh) > +MIPSDSP32_BINOP_ENV(addq_s_w, sat_add_i32, sw); > +MIPSDSP32_BINOP_ENV(addu_ph, add_u16, sh) > +MIPSDSP32_BINOP_ENV(addu_qb, add_u8, ub); > +MIPSDSP32_BINOP_ENV(addu_s_ph, sat_add_u16, sh) > +MIPSDSP32_BINOP_ENV(addu_s_qb, sat_add_u8, ub); > +MIPSDSP32_BINOP_ENV(subq_ph, sub_i16, sh); > +MIPSDSP32_BINOP_ENV(subq_s_ph, sat16_sub, sh); > +MIPSDSP32_BINOP_ENV(subq_s_w, sat32_sub, sw); > +MIPSDSP32_BINOP_ENV(subu_ph, sub_u16_u16, sh); > +MIPSDSP32_BINOP_ENV(subu_qb, sub_u8, ub); > +MIPSDSP32_BINOP_ENV(subu_s_ph, satu16_sub_u16_u16, sh); > +MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub); > +#undef MIPSDSP32_BINOP_ENV > > #ifdef TARGET_MIPS64 > -#define ARITH_QH_ENV(name, func) \ > -target_ulong helper_##name##_qh(target_ulong rs, target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - uint16_t rs3, rs2, rs1, rs0; \ > - uint16_t rt3, rt2, rt1, rt0; \ > - uint16_t tempD, tempC, tempB, tempA; \ > - \ > - MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ > - MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ > - \ > - tempD = mipsdsp_##func(rs3, rt3, env); \ > - tempC = mipsdsp_##func(rs2, rt2, env); \ > - tempB = mipsdsp_##func(rs1, rt1, env); \ > - tempA = mipsdsp_##func(rs0, rt0, env); \ > - \ > - return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ > -} > - > -ARITH_QH_ENV(addq, add_i16); > -ARITH_QH_ENV(addq_s, sat_add_i16); > -ARITH_QH_ENV(addu, add_u16); > -ARITH_QH_ENV(addu_s, sat_add_u16); > - > -ARITH_QH_ENV(subq, sub_i16); > -ARITH_QH_ENV(subq_s, sat16_sub); > -ARITH_QH_ENV(subu, sub_u16_u16); > -ARITH_QH_ENV(subu_s, satu16_sub_u16_u16); > - > -#undef ARITH_QH_ENV > +#define MIPSDSP64_BINOP(name, func, element) \ > +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ > +{ \ > + DSP64Value ds, dt; \ > + unsigned int i, n; \ > + \ > + n = sizeof(DSP64Value) / sizeof(ds.element[0]); \ > + ds.sl[0] = rs; \ > + dt.sl[0] = rt; \ > + \ > + for (i = 0 ; i < n ; i++) { \ > + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \ > + } \ > + \ > + return ds.sl[0]; \ > +} > +MIPSDSP64_BINOP(adduh_ob, rshift1_add_u8, ub); > +MIPSDSP64_BINOP(adduh_r_ob, rrshift1_add_u8, ub); > +MIPSDSP64_BINOP(subuh_ob, rshift1_sub_u8, ub); > +MIPSDSP64_BINOP(subuh_r_ob, rrshift1_sub_u8, ub); > +#undef MIPSDSP64_BINOP > + > +#define MIPSDSP64_BINOP_ENV(name, func, element) \ > +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ > + CPUMIPSState *env) \ > +{ \ > + DSP64Value ds, dt; \ > + unsigned int i, n; \ > + \ > + n = sizeof(DSP64Value) / sizeof(ds.element[0]); \ > + ds.sl[0] = rs; \ > + dt.sl[0] = rt; \ > + \ > + for (i = 0 ; i < n ; i++) { \ > + ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \ > + } \ > + \ > + return ds.sl[0]; \ > +} > +MIPSDSP64_BINOP_ENV(addq_pw, add_i32, sw); > +MIPSDSP64_BINOP_ENV(addq_qh, add_i16, sh); > +MIPSDSP64_BINOP_ENV(addq_s_pw, sat_add_i32, sw); > +MIPSDSP64_BINOP_ENV(addq_s_qh, sat_add_i16, sh); > +MIPSDSP64_BINOP_ENV(addu_ob, add_u8, uh); > +MIPSDSP64_BINOP_ENV(addu_qh, add_u16, uh); > +MIPSDSP64_BINOP_ENV(addu_s_ob, sat_add_u8, uh); > +MIPSDSP64_BINOP_ENV(addu_s_qh, sat_add_u16, uh); > +MIPSDSP64_BINOP_ENV(subq_pw, sub32, sw); > +MIPSDSP64_BINOP_ENV(subq_qh, sub_i16, sh); > +MIPSDSP64_BINOP_ENV(subq_s_pw, sat32_sub, sw); > +MIPSDSP64_BINOP_ENV(subq_s_qh, sat16_sub, sh); > +MIPSDSP64_BINOP_ENV(subu_ob, sub_u8, uh); > +MIPSDSP64_BINOP_ENV(subu_qh, sub_u16_u16, uh); > +MIPSDSP64_BINOP_ENV(subu_s_ob, satu8_sub, uh); > +MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh); > +#undef MIPSDSP64_BINOP_ENV > > #endif > > -#define ARITH_W(name, func) \ > -target_ulong helper_##name##_w(target_ulong rs, target_ulong rt) \ > -{ \ > - uint32_t rd; \ > - rd = mipsdsp_##func(rs, rt); \ > - return MIPSDSP_RETURN32(rd); \ > -} > - > -#define ARITH_W_ENV(name, func) \ > -target_ulong helper_##name##_w(target_ulong rs, target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - uint32_t rd; \ > - rd = mipsdsp_##func(rs, rt, env); \ > - return MIPSDSP_RETURN32(rd); \ > -} > - > -ARITH_W_ENV(addq_s, sat_add_i32); > - > -ARITH_W(addqh, rshift1_add_q32); > -ARITH_W(addqh_r, rrshift1_add_q32); > - > -ARITH_W_ENV(subq_s, sat32_sub); > - > -ARITH_W(subqh, rshift1_sub_q32); > -ARITH_W(subqh_r, rrshift1_sub_q32); > - > -#undef ARITH_W > -#undef ARITH_W_ENV > - > target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) > { > uint32_t rd; > @@ -1234,164 +1241,6 @@ target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) > } > > > -#if defined(TARGET_MIPS64) > - > -#define ARITH_PW_ENV(name, func) \ > -target_ulong helper_##name##_pw(target_ulong rs, target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - uint32_t rs1, rs0; \ > - uint32_t rt1, rt0; \ > - uint32_t tempB, tempA; \ > - \ > - MIPSDSP_SPLIT64_32(rs, rs1, rs0); \ > - MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ > - \ > - tempB = mipsdsp_##func(rs1, rt1, env); \ > - tempA = mipsdsp_##func(rs0, rt0, env); \ > - \ > - return MIPSDSP_RETURN64_32(tempB, tempA); \ > -} > - > -ARITH_PW_ENV(addq, add_i32); > -ARITH_PW_ENV(addq_s, sat_add_i32); > -ARITH_PW_ENV(subq, sub32); > -ARITH_PW_ENV(subq_s, sat32_sub); > - > -#undef ARITH_PW_ENV > - > -#endif > - > -#define ARITH_QB(name, func) \ > -target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ > -{ \ > - uint8_t rs0, rs1, rs2, rs3; \ > - uint8_t rt0, rt1, rt2, rt3; \ > - uint8_t temp0, temp1, temp2, temp3; \ > - \ > - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ > - MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ > - \ > - temp0 = mipsdsp_##func(rs0, rt0); \ > - temp1 = mipsdsp_##func(rs1, rt1); \ > - temp2 = mipsdsp_##func(rs2, rt2); \ > - temp3 = mipsdsp_##func(rs3, rt3); \ > - \ > - return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \ > -} > - > -#define ARITH_QB_ENV(name, func) \ > -target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - uint8_t rs0, rs1, rs2, rs3; \ > - uint8_t rt0, rt1, rt2, rt3; \ > - uint8_t temp0, temp1, temp2, temp3; \ > - \ > - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ > - MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ > - \ > - temp0 = mipsdsp_##func(rs0, rt0, env); \ > - temp1 = mipsdsp_##func(rs1, rt1, env); \ > - temp2 = mipsdsp_##func(rs2, rt2, env); \ > - temp3 = mipsdsp_##func(rs3, rt3, env); \ > - \ > - return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \ > -} > - > -ARITH_QB(adduh, rshift1_add_u8); > -ARITH_QB(adduh_r, rrshift1_add_u8); > - > -ARITH_QB_ENV(addu, add_u8); > -ARITH_QB_ENV(addu_s, sat_add_u8); > - > -#undef ADDU_QB > -#undef ADDU_QB_ENV > - > -#if defined(TARGET_MIPS64) > -#define ARITH_OB(name, func) \ > -target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt) \ > -{ \ > - int i; \ > - uint8_t rs_t[8], rt_t[8]; \ > - uint8_t temp[8]; \ > - uint64_t result; \ > - \ > - result = 0; \ > - \ > - for (i = 0; i < 8; i++) { \ > - rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ > - rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ > - temp[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \ > - result |= (uint64_t)temp[i] << (8 * i); \ > - } \ > - \ > - return result; \ > -} > - > -#define ARITH_OB_ENV(name, func) \ > -target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - int i; \ > - uint8_t rs_t[8], rt_t[8]; \ > - uint8_t temp[8]; \ > - uint64_t result; \ > - \ > - result = 0; \ > - \ > - for (i = 0; i < 8; i++) { \ > - rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ > - rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ > - temp[i] = mipsdsp_##func(rs_t[i], rt_t[i], env); \ > - result |= (uint64_t)temp[i] << (8 * i); \ > - } \ > - \ > - return result; \ > -} > - > -ARITH_OB_ENV(addu, add_u8); > -ARITH_OB_ENV(addu_s, sat_add_u8); > - > -ARITH_OB(adduh, rshift1_add_u8); > -ARITH_OB(adduh_r, rrshift1_add_u8); > - > -ARITH_OB_ENV(subu, sub_u8); > -ARITH_OB_ENV(subu_s, satu8_sub); > - > -ARITH_OB(subuh, rshift1_sub_u8); > -ARITH_OB(subuh_r, rrshift1_sub_u8); > - > -#undef ARITH_OB > -#undef ARITH_OB_ENV > - > -#endif > - > -#define SUBU_QB(name, func) \ > -target_ulong helper_##name##_qb(target_ulong rs, \ > - target_ulong rt, \ > - CPUMIPSState *env) \ > -{ \ > - uint8_t rs3, rs2, rs1, rs0; \ > - uint8_t rt3, rt2, rt1, rt0; \ > - uint8_t tempD, tempC, tempB, tempA; \ > - \ > - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ > - MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ > - \ > - tempD = mipsdsp_##func(rs3, rt3, env); \ > - tempC = mipsdsp_##func(rs2, rt2, env); \ > - tempB = mipsdsp_##func(rs1, rt1, env); \ > - tempA = mipsdsp_##func(rs0, rt0, env); \ > - \ > - return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \ > -} > - > -SUBU_QB(subu, sub_u8); > -SUBU_QB(subu_s, satu8_sub); > - > -#undef SUBU_QB > - > #define SUBUH_QB(name, var) \ > target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ > { \ > @@ -4027,7 +3876,6 @@ target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env) > #undef MIPSDSP_SPLIT32_8 > #undef MIPSDSP_SPLIT32_16 > > -#undef MIPSDSP_RETURN32 > #undef MIPSDSP_RETURN32_8 > #undef MIPSDSP_RETURN32_16 > > -- > 1.7.10.4 > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators 2013-01-09 21:16 ` Blue Swirl @ 2013-01-10 7:08 ` Aurelien Jarno 2013-01-12 10:39 ` Blue Swirl 0 siblings, 1 reply; 18+ messages in thread From: Aurelien Jarno @ 2013-01-10 7:08 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel On Wed, Jan 09, 2013 at 09:16:29PM +0000, Blue Swirl wrote: > On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > > This allow to reduce the number of macros. > > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > --- > > target-mips/dsp_helper.c | 384 ++++++++++++++-------------------------------- > > 1 file changed, 116 insertions(+), 268 deletions(-) > > > > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c > > index aed4c63..e01c8a9 100644 > > --- a/target-mips/dsp_helper.c > > +++ b/target-mips/dsp_helper.c > > @@ -1078,7 +1078,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > > b = num & MIPSDSP_LO; \ > > } while (0) > > > > -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) > > #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ > > (((uint32_t)a << 24) | \ > > (((uint32_t)b << 16) | \ > > @@ -1111,119 +1110,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > > #endif > > > > /** DSP Arithmetic Sub-class insns **/ > > -#define ARITH_PH(name, func) \ > > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ > > -{ \ > > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ > > - \ > > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ > > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ > > - \ > > - temph = mipsdsp_##func(rsh, rth); \ > > - templ = mipsdsp_##func(rsl, rtl); \ > > - \ > > - return MIPSDSP_RETURN32_16(temph, templ); \ > > -} > > - > > -#define ARITH_PH_ENV(name, func) \ > > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ > > - CPUMIPSState *env) \ > > -{ \ > > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ > > - \ > > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ > > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ > > - \ > > - temph = mipsdsp_##func(rsh, rth, env); \ > > - templ = mipsdsp_##func(rsl, rtl, env); \ > > - \ > > - return MIPSDSP_RETURN32_16(temph, templ); \ > > -} > > - > > - > > -ARITH_PH_ENV(addq, add_i16); > > -ARITH_PH_ENV(addq_s, sat_add_i16); > > -ARITH_PH_ENV(addu, add_u16); > > -ARITH_PH_ENV(addu_s, sat_add_u16); > > - > > -ARITH_PH(addqh, rshift1_add_q16); > > -ARITH_PH(addqh_r, rrshift1_add_q16); > > - > > -ARITH_PH_ENV(subq, sub_i16); > > -ARITH_PH_ENV(subq_s, sat16_sub); > > -ARITH_PH_ENV(subu, sub_u16_u16); > > -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); > > - > > -ARITH_PH(subqh, rshift1_sub_q16); > > -ARITH_PH(subqh_r, rrshift1_sub_q16); > > - > > -#undef ARITH_PH > > -#undef ARITH_PH_ENV > > +#define MIPSDSP32_BINOP(name, func, element) \ > > +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ > > +{ \ > > + DSP32Value ds, dt; \ > > + unsigned int i, n; \ > > + \ > > + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ > > + ds.sw[0] = rs; \ > > + dt.sw[0] = rt; \ > > + \ > > + for (i = 0 ; i < n ; i++) { \ > > There's an extra space before ';', please remove. Also in the other > for loops below. It is not something I can find in CODING_STYLE, and it is also not caught by checkpatch.pl. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators 2013-01-10 7:08 ` Aurelien Jarno @ 2013-01-12 10:39 ` Blue Swirl 2013-01-12 14:34 ` Aurelien Jarno 0 siblings, 1 reply; 18+ messages in thread From: Blue Swirl @ 2013-01-12 10:39 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On Thu, Jan 10, 2013 at 7:08 AM, Aurelien Jarno <aurelien@aurel32.net> wrote: > On Wed, Jan 09, 2013 at 09:16:29PM +0000, Blue Swirl wrote: >> On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: >> > This allow to reduce the number of macros. >> > >> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> >> > --- >> > target-mips/dsp_helper.c | 384 ++++++++++++++-------------------------------- >> > 1 file changed, 116 insertions(+), 268 deletions(-) >> > >> > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c >> > index aed4c63..e01c8a9 100644 >> > --- a/target-mips/dsp_helper.c >> > +++ b/target-mips/dsp_helper.c >> > @@ -1078,7 +1078,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) >> > b = num & MIPSDSP_LO; \ >> > } while (0) >> > >> > -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) >> > #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ >> > (((uint32_t)a << 24) | \ >> > (((uint32_t)b << 16) | \ >> > @@ -1111,119 +1110,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) >> > #endif >> > >> > /** DSP Arithmetic Sub-class insns **/ >> > -#define ARITH_PH(name, func) \ >> > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ >> > -{ \ >> > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ >> > - \ >> > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ >> > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ >> > - \ >> > - temph = mipsdsp_##func(rsh, rth); \ >> > - templ = mipsdsp_##func(rsl, rtl); \ >> > - \ >> > - return MIPSDSP_RETURN32_16(temph, templ); \ >> > -} >> > - >> > -#define ARITH_PH_ENV(name, func) \ >> > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ >> > - CPUMIPSState *env) \ >> > -{ \ >> > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ >> > - \ >> > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ >> > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ >> > - \ >> > - temph = mipsdsp_##func(rsh, rth, env); \ >> > - templ = mipsdsp_##func(rsl, rtl, env); \ >> > - \ >> > - return MIPSDSP_RETURN32_16(temph, templ); \ >> > -} >> > - >> > - >> > -ARITH_PH_ENV(addq, add_i16); >> > -ARITH_PH_ENV(addq_s, sat_add_i16); >> > -ARITH_PH_ENV(addu, add_u16); >> > -ARITH_PH_ENV(addu_s, sat_add_u16); >> > - >> > -ARITH_PH(addqh, rshift1_add_q16); >> > -ARITH_PH(addqh_r, rrshift1_add_q16); >> > - >> > -ARITH_PH_ENV(subq, sub_i16); >> > -ARITH_PH_ENV(subq_s, sat16_sub); >> > -ARITH_PH_ENV(subu, sub_u16_u16); >> > -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); >> > - >> > -ARITH_PH(subqh, rshift1_sub_q16); >> > -ARITH_PH(subqh_r, rrshift1_sub_q16); >> > - >> > -#undef ARITH_PH >> > -#undef ARITH_PH_ENV >> > +#define MIPSDSP32_BINOP(name, func, element) \ >> > +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ >> > +{ \ >> > + DSP32Value ds, dt; \ >> > + unsigned int i, n; \ >> > + \ >> > + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ >> > + ds.sw[0] = rs; \ >> > + dt.sw[0] = rt; \ >> > + \ >> > + for (i = 0 ; i < n ; i++) { \ >> >> There's an extra space before ';', please remove. Also in the other >> for loops below. > > It is not something I can find in CODING_STYLE, and it is also not > caught by checkpatch.pl. No, but it's not common style by far: egrep -r '--exclude-dir=obj-*' '--exclude-dir=.git*' '--exclude-dir=roms' '--exclude-dir=pc-bios' '--exclude-dir=pixman' '--include=*.c' 'for.* ;' .|wc -l 74 egrep -r '--exclude-dir=obj-*' '--exclude-dir=.git*' '--exclude-dir=roms' '--exclude-dir=pc-bios' '--exclude-dir=pixman' '--include=*.c' 'for.*;' .|wc -l 4585 Original K&R style, from which QEMU style derives, didn't have the spaces either. Perhaps you are influenced by French punctuation rules? > > -- > Aurelien Jarno GPG: 1024D/F1BCDB73 > aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators 2013-01-12 10:39 ` Blue Swirl @ 2013-01-12 14:34 ` Aurelien Jarno 2013-01-12 15:08 ` Blue Swirl 0 siblings, 1 reply; 18+ messages in thread From: Aurelien Jarno @ 2013-01-12 14:34 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel On Sat, Jan 12, 2013 at 10:39:47AM +0000, Blue Swirl wrote: > On Thu, Jan 10, 2013 at 7:08 AM, Aurelien Jarno <aurelien@aurel32.net> wrote: > > On Wed, Jan 09, 2013 at 09:16:29PM +0000, Blue Swirl wrote: > >> On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > >> > This allow to reduce the number of macros. > >> > > >> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > >> > --- > >> > target-mips/dsp_helper.c | 384 ++++++++++++++-------------------------------- > >> > 1 file changed, 116 insertions(+), 268 deletions(-) > >> > > >> > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c > >> > index aed4c63..e01c8a9 100644 > >> > --- a/target-mips/dsp_helper.c > >> > +++ b/target-mips/dsp_helper.c > >> > @@ -1078,7 +1078,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > >> > b = num & MIPSDSP_LO; \ > >> > } while (0) > >> > > >> > -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) > >> > #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ > >> > (((uint32_t)a << 24) | \ > >> > (((uint32_t)b << 16) | \ > >> > @@ -1111,119 +1110,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > >> > #endif > >> > > >> > /** DSP Arithmetic Sub-class insns **/ > >> > -#define ARITH_PH(name, func) \ > >> > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ > >> > -{ \ > >> > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ > >> > - \ > >> > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ > >> > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ > >> > - \ > >> > - temph = mipsdsp_##func(rsh, rth); \ > >> > - templ = mipsdsp_##func(rsl, rtl); \ > >> > - \ > >> > - return MIPSDSP_RETURN32_16(temph, templ); \ > >> > -} > >> > - > >> > -#define ARITH_PH_ENV(name, func) \ > >> > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ > >> > - CPUMIPSState *env) \ > >> > -{ \ > >> > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ > >> > - \ > >> > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ > >> > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ > >> > - \ > >> > - temph = mipsdsp_##func(rsh, rth, env); \ > >> > - templ = mipsdsp_##func(rsl, rtl, env); \ > >> > - \ > >> > - return MIPSDSP_RETURN32_16(temph, templ); \ > >> > -} > >> > - > >> > - > >> > -ARITH_PH_ENV(addq, add_i16); > >> > -ARITH_PH_ENV(addq_s, sat_add_i16); > >> > -ARITH_PH_ENV(addu, add_u16); > >> > -ARITH_PH_ENV(addu_s, sat_add_u16); > >> > - > >> > -ARITH_PH(addqh, rshift1_add_q16); > >> > -ARITH_PH(addqh_r, rrshift1_add_q16); > >> > - > >> > -ARITH_PH_ENV(subq, sub_i16); > >> > -ARITH_PH_ENV(subq_s, sat16_sub); > >> > -ARITH_PH_ENV(subu, sub_u16_u16); > >> > -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); > >> > - > >> > -ARITH_PH(subqh, rshift1_sub_q16); > >> > -ARITH_PH(subqh_r, rrshift1_sub_q16); > >> > - > >> > -#undef ARITH_PH > >> > -#undef ARITH_PH_ENV > >> > +#define MIPSDSP32_BINOP(name, func, element) \ > >> > +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ > >> > +{ \ > >> > + DSP32Value ds, dt; \ > >> > + unsigned int i, n; \ > >> > + \ > >> > + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ > >> > + ds.sw[0] = rs; \ > >> > + dt.sw[0] = rt; \ > >> > + \ > >> > + for (i = 0 ; i < n ; i++) { \ > >> > >> There's an extra space before ';', please remove. Also in the other > >> for loops below. > > > > It is not something I can find in CODING_STYLE, and it is also not > > caught by checkpatch.pl. > > No, but it's not common style by far: > egrep -r '--exclude-dir=obj-*' '--exclude-dir=.git*' > '--exclude-dir=roms' '--exclude-dir=pc-bios' '--exclude-dir=pixman' > '--include=*.c' 'for.* ;' .|wc -l > 74 > egrep -r '--exclude-dir=obj-*' '--exclude-dir=.git*' > '--exclude-dir=roms' '--exclude-dir=pc-bios' '--exclude-dir=pixman' > '--include=*.c' 'for.*;' .|wc -l > 4585 > > Original K&R style, from which QEMU style derives, didn't have the > spaces either. Perhaps you are influenced by French punctuation rules? I don't really care if it is common or not. What I am saying is that if you want a rule to be enforced, it's better to at least have it written. It's also a good idea to have it added to checkpatch.pl, otherwise the benefit of this tool is greatly reduced. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators 2013-01-12 14:34 ` Aurelien Jarno @ 2013-01-12 15:08 ` Blue Swirl 0 siblings, 0 replies; 18+ messages in thread From: Blue Swirl @ 2013-01-12 15:08 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On Sat, Jan 12, 2013 at 2:34 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > On Sat, Jan 12, 2013 at 10:39:47AM +0000, Blue Swirl wrote: >> On Thu, Jan 10, 2013 at 7:08 AM, Aurelien Jarno <aurelien@aurel32.net> wrote: >> > On Wed, Jan 09, 2013 at 09:16:29PM +0000, Blue Swirl wrote: >> >> On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: >> >> > This allow to reduce the number of macros. >> >> > >> >> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> >> >> > --- >> >> > target-mips/dsp_helper.c | 384 ++++++++++++++-------------------------------- >> >> > 1 file changed, 116 insertions(+), 268 deletions(-) >> >> > >> >> > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c >> >> > index aed4c63..e01c8a9 100644 >> >> > --- a/target-mips/dsp_helper.c >> >> > +++ b/target-mips/dsp_helper.c >> >> > @@ -1078,7 +1078,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) >> >> > b = num & MIPSDSP_LO; \ >> >> > } while (0) >> >> > >> >> > -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) >> >> > #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ >> >> > (((uint32_t)a << 24) | \ >> >> > (((uint32_t)b << 16) | \ >> >> > @@ -1111,119 +1110,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) >> >> > #endif >> >> > >> >> > /** DSP Arithmetic Sub-class insns **/ >> >> > -#define ARITH_PH(name, func) \ >> >> > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ >> >> > -{ \ >> >> > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ >> >> > - \ >> >> > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ >> >> > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ >> >> > - \ >> >> > - temph = mipsdsp_##func(rsh, rth); \ >> >> > - templ = mipsdsp_##func(rsl, rtl); \ >> >> > - \ >> >> > - return MIPSDSP_RETURN32_16(temph, templ); \ >> >> > -} >> >> > - >> >> > -#define ARITH_PH_ENV(name, func) \ >> >> > -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ >> >> > - CPUMIPSState *env) \ >> >> > -{ \ >> >> > - uint16_t rsh, rsl, rth, rtl, temph, templ; \ >> >> > - \ >> >> > - MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ >> >> > - MIPSDSP_SPLIT32_16(rt, rth, rtl); \ >> >> > - \ >> >> > - temph = mipsdsp_##func(rsh, rth, env); \ >> >> > - templ = mipsdsp_##func(rsl, rtl, env); \ >> >> > - \ >> >> > - return MIPSDSP_RETURN32_16(temph, templ); \ >> >> > -} >> >> > - >> >> > - >> >> > -ARITH_PH_ENV(addq, add_i16); >> >> > -ARITH_PH_ENV(addq_s, sat_add_i16); >> >> > -ARITH_PH_ENV(addu, add_u16); >> >> > -ARITH_PH_ENV(addu_s, sat_add_u16); >> >> > - >> >> > -ARITH_PH(addqh, rshift1_add_q16); >> >> > -ARITH_PH(addqh_r, rrshift1_add_q16); >> >> > - >> >> > -ARITH_PH_ENV(subq, sub_i16); >> >> > -ARITH_PH_ENV(subq_s, sat16_sub); >> >> > -ARITH_PH_ENV(subu, sub_u16_u16); >> >> > -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); >> >> > - >> >> > -ARITH_PH(subqh, rshift1_sub_q16); >> >> > -ARITH_PH(subqh_r, rrshift1_sub_q16); >> >> > - >> >> > -#undef ARITH_PH >> >> > -#undef ARITH_PH_ENV >> >> > +#define MIPSDSP32_BINOP(name, func, element) \ >> >> > +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ >> >> > +{ \ >> >> > + DSP32Value ds, dt; \ >> >> > + unsigned int i, n; \ >> >> > + \ >> >> > + n = sizeof(DSP32Value) / sizeof(ds.element[0]); \ >> >> > + ds.sw[0] = rs; \ >> >> > + dt.sw[0] = rt; \ >> >> > + \ >> >> > + for (i = 0 ; i < n ; i++) { \ >> >> >> >> There's an extra space before ';', please remove. Also in the other >> >> for loops below. >> > >> > It is not something I can find in CODING_STYLE, and it is also not >> > caught by checkpatch.pl. >> >> No, but it's not common style by far: >> egrep -r '--exclude-dir=obj-*' '--exclude-dir=.git*' >> '--exclude-dir=roms' '--exclude-dir=pc-bios' '--exclude-dir=pixman' >> '--include=*.c' 'for.* ;' .|wc -l >> 74 >> egrep -r '--exclude-dir=obj-*' '--exclude-dir=.git*' >> '--exclude-dir=roms' '--exclude-dir=pc-bios' '--exclude-dir=pixman' >> '--include=*.c' 'for.*;' .|wc -l >> 4585 >> >> Original K&R style, from which QEMU style derives, didn't have the >> spaces either. Perhaps you are influenced by French punctuation rules? > > I don't really care if it is common or not. But commonality is the whole point of the CODING_STYLE and checkpatch.pl, we want to drive the code base to be more uniform. If having extra spaces was very common, like 25% or more of 'for' statements, it would be clear that there is no general rule but in this case it's clearly not. > What I am saying is that if > you want a rule to be enforced, it's better to at least have it written. > It's also a good idea to have it added to checkpatch.pl, otherwise the > benefit of this tool is greatly reduced. I'm pretty sure there are many things that a simple Perl script which only sees a few lines being patched can't ever catch and CODING_STYLE or other documents can't also cover all aspects of how to make code. In this case, a rule for avoiding space before a semicolon (probably also colons too) could be possible. To avoid false positives, it should be allowed where it's the only thing on a line. Also, cases like this: /src/qemu/hw/spapr_hcall.c:133: for (i = 0; ; ++i) { where the second statement in the for loop is not present, it makes the text even clearer. > > -- > Aurelien Jarno GPG: 1024D/F1BCDB73 > aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 6/8] target-mips: use DSP unions for unary DSP operators 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (4 preceding siblings ...) 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 21:17 ` Blue Swirl 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions Aurelien Jarno ` (3 subsequent siblings) 9 siblings, 1 reply; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno This allow to reduce the number of macros. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/dsp_helper.c | 124 ++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 82 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index e01c8a9..1bc77a2 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -1110,6 +1110,48 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) #endif /** DSP Arithmetic Sub-class insns **/ +#define MIPSDSP32_UNOP_ENV(name, func, element) \ +target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \ +{ \ + DSP32Value dt; \ + unsigned int i, n; \ + \ + n = sizeof(DSP32Value) / sizeof(dt.element[0]); \ + dt.sw[0] = rt; \ + \ + for (i = 0 ; i < n ; i++) { \ + dt.element[i] = mipsdsp_##func(dt.element[i], env); \ + } \ + \ + return (target_long)dt.sw[0]; \ +} +MIPSDSP32_UNOP_ENV(absq_s_ph, sat_abs16, sh) +MIPSDSP32_UNOP_ENV(absq_s_qb, sat_abs8, sb) +MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw) +#undef MIPSDSP32_UNOP_ENV + +#if defined(TARGET_MIPS64) +#define MIPSDSP64_UNOP_ENV(name, func, element) \ +target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \ +{ \ + DSP64Value dt; \ + unsigned int i, n; \ + \ + n = sizeof(DSP64Value) / sizeof(dt.element[0]); \ + dt.sl[0] = rt; \ + \ + for (i = 0 ; i < n ; i++) { \ + dt.element[i] = mipsdsp_##func(dt.element[i], env); \ + } \ + \ + return dt.sl[0]; \ +} +MIPSDSP64_UNOP_ENV(absq_s_ob, sat_abs8, sb) +MIPSDSP64_UNOP_ENV(absq_s_qh, sat_abs16, sh) +MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw) +#undef MIPSDSP64_UNOP_ENV +#endif + #define MIPSDSP32_BINOP(name, func, element) \ target_ulong helper_##name(target_ulong rs, target_ulong rt) \ { \ @@ -1231,16 +1273,6 @@ MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh); #endif -target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) -{ - uint32_t rd; - - rd = mipsdsp_sat_abs32(rt, env); - - return (target_ulong)rd; -} - - #define SUBUH_QB(name, var) \ target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ { \ @@ -1348,78 +1380,6 @@ target_ulong helper_raddu_l_ob(target_ulong rs) } #endif -target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env) -{ - uint8_t tempD, tempC, tempB, tempA; - - MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA); - - tempD = mipsdsp_sat_abs8(tempD, env); - tempC = mipsdsp_sat_abs8(tempC, env); - tempB = mipsdsp_sat_abs8(tempB, env); - tempA = mipsdsp_sat_abs8(tempA, env); - - return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); -} - -target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env) -{ - uint16_t tempB, tempA; - - MIPSDSP_SPLIT32_16(rt, tempB, tempA); - - tempB = mipsdsp_sat_abs16 (tempB, env); - tempA = mipsdsp_sat_abs16 (tempA, env); - - return MIPSDSP_RETURN32_16(tempB, tempA); -} - -#if defined(TARGET_MIPS64) -target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env) -{ - int i; - int8_t temp[8]; - uint64_t result; - - for (i = 0; i < 8; i++) { - temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0; - temp[i] = mipsdsp_sat_abs8(temp[i], env); - } - - for (i = 0; i < 8; i++) { - result = (uint64_t)(uint8_t)temp[i] << (8 * i); - } - - return result; -} - -target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env) -{ - int16_t tempD, tempC, tempB, tempA; - - MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA); - - tempD = mipsdsp_sat_abs16(tempD, env); - tempC = mipsdsp_sat_abs16(tempC, env); - tempB = mipsdsp_sat_abs16(tempB, env); - tempA = mipsdsp_sat_abs16(tempA, env); - - return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); -} - -target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env) -{ - int32_t tempB, tempA; - - MIPSDSP_SPLIT64_32(rt, tempB, tempA); - - tempB = mipsdsp_sat_abs32(tempB, env); - tempA = mipsdsp_sat_abs32(tempA, env); - - return MIPSDSP_RETURN64_32(tempB, tempA); -} -#endif - #define PRECR_QB_PH(name, a, b)\ target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \ { \ -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 6/8] target-mips: use DSP unions for unary DSP operators 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 6/8] target-mips: use DSP unions for unary " Aurelien Jarno @ 2013-01-09 21:17 ` Blue Swirl 0 siblings, 0 replies; 18+ messages in thread From: Blue Swirl @ 2013-01-09 21:17 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > This allow to reduce the number of macros. > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > target-mips/dsp_helper.c | 124 ++++++++++++++++------------------------------ > 1 file changed, 42 insertions(+), 82 deletions(-) > > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c > index e01c8a9..1bc77a2 100644 > --- a/target-mips/dsp_helper.c > +++ b/target-mips/dsp_helper.c > @@ -1110,6 +1110,48 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) > #endif > > /** DSP Arithmetic Sub-class insns **/ > +#define MIPSDSP32_UNOP_ENV(name, func, element) \ > +target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \ > +{ \ > + DSP32Value dt; \ > + unsigned int i, n; \ > + \ > + n = sizeof(DSP32Value) / sizeof(dt.element[0]); \ > + dt.sw[0] = rt; \ > + \ > + for (i = 0 ; i < n ; i++) { \ Extra space before ';', also below. > + dt.element[i] = mipsdsp_##func(dt.element[i], env); \ > + } \ > + \ > + return (target_long)dt.sw[0]; \ > +} > +MIPSDSP32_UNOP_ENV(absq_s_ph, sat_abs16, sh) > +MIPSDSP32_UNOP_ENV(absq_s_qb, sat_abs8, sb) > +MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw) > +#undef MIPSDSP32_UNOP_ENV > + > +#if defined(TARGET_MIPS64) > +#define MIPSDSP64_UNOP_ENV(name, func, element) \ > +target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \ > +{ \ > + DSP64Value dt; \ > + unsigned int i, n; \ > + \ > + n = sizeof(DSP64Value) / sizeof(dt.element[0]); \ > + dt.sl[0] = rt; \ > + \ > + for (i = 0 ; i < n ; i++) { \ > + dt.element[i] = mipsdsp_##func(dt.element[i], env); \ > + } \ > + \ > + return dt.sl[0]; \ > +} > +MIPSDSP64_UNOP_ENV(absq_s_ob, sat_abs8, sb) > +MIPSDSP64_UNOP_ENV(absq_s_qh, sat_abs16, sh) > +MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw) > +#undef MIPSDSP64_UNOP_ENV > +#endif > + > #define MIPSDSP32_BINOP(name, func, element) \ > target_ulong helper_##name(target_ulong rs, target_ulong rt) \ > { \ > @@ -1231,16 +1273,6 @@ MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh); > > #endif > > -target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) > -{ > - uint32_t rd; > - > - rd = mipsdsp_sat_abs32(rt, env); > - > - return (target_ulong)rd; > -} > - > - > #define SUBUH_QB(name, var) \ > target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ > { \ > @@ -1348,78 +1380,6 @@ target_ulong helper_raddu_l_ob(target_ulong rs) > } > #endif > > -target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env) > -{ > - uint8_t tempD, tempC, tempB, tempA; > - > - MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA); > - > - tempD = mipsdsp_sat_abs8(tempD, env); > - tempC = mipsdsp_sat_abs8(tempC, env); > - tempB = mipsdsp_sat_abs8(tempB, env); > - tempA = mipsdsp_sat_abs8(tempA, env); > - > - return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); > -} > - > -target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env) > -{ > - uint16_t tempB, tempA; > - > - MIPSDSP_SPLIT32_16(rt, tempB, tempA); > - > - tempB = mipsdsp_sat_abs16 (tempB, env); > - tempA = mipsdsp_sat_abs16 (tempA, env); > - > - return MIPSDSP_RETURN32_16(tempB, tempA); > -} > - > -#if defined(TARGET_MIPS64) > -target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env) > -{ > - int i; > - int8_t temp[8]; > - uint64_t result; > - > - for (i = 0; i < 8; i++) { > - temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0; > - temp[i] = mipsdsp_sat_abs8(temp[i], env); > - } > - > - for (i = 0; i < 8; i++) { > - result = (uint64_t)(uint8_t)temp[i] << (8 * i); > - } > - > - return result; > -} > - > -target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env) > -{ > - int16_t tempD, tempC, tempB, tempA; > - > - MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA); > - > - tempD = mipsdsp_sat_abs16(tempD, env); > - tempC = mipsdsp_sat_abs16(tempC, env); > - tempB = mipsdsp_sat_abs16(tempB, env); > - tempA = mipsdsp_sat_abs16(tempA, env); > - > - return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); > -} > - > -target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env) > -{ > - int32_t tempB, tempA; > - > - MIPSDSP_SPLIT64_32(rt, tempB, tempA); > - > - tempB = mipsdsp_sat_abs32(tempB, env); > - tempA = mipsdsp_sat_abs32(tempA, env); > - > - return MIPSDSP_RETURN64_32(tempB, tempA); > -} > -#endif > - > #define PRECR_QB_PH(name, a, b)\ > target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \ > { \ > -- > 1.7.10.4 > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (5 preceding siblings ...) 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 6/8] target-mips: use DSP unions for unary " Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 21:18 ` Blue Swirl 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 8/8] target-mips: implement DSP (d)append sub-class with TCG Aurelien Jarno ` (2 subsequent siblings) 9 siblings, 1 reply; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/dsp_helper.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 1bc77a2..ea7a99f 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -1352,31 +1352,29 @@ target_ulong helper_modsub(target_ulong rs, target_ulong rt) target_ulong helper_raddu_w_qb(target_ulong rs) { - uint8_t rs3, rs2, rs1, rs0; - uint16_t temp; - - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); - - temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0; + target_ulong ret = 0; + DSP32Value ds; + unsigned int i; - return (target_ulong)temp; + ds.uw[0] = rs; + for (i = 0 ; i < 4 ; i++) { + ret += ds.ub[i]; + } + return ret; } #if defined(TARGET_MIPS64) target_ulong helper_raddu_l_ob(target_ulong rs) { - int i; - uint16_t rs_t[8]; - uint64_t temp; - - temp = 0; + target_ulong ret = 0; + DSP64Value ds; + unsigned int i; - for (i = 0; i < 8; i++) { - rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; - temp += (uint64_t)rs_t[i]; + ds.ul[0] = rs; + for (i = 0 ; i < 8 ; i++) { + ret += ds.ub[i]; } - - return temp; + return ret; } #endif -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions Aurelien Jarno @ 2013-01-09 21:18 ` Blue Swirl 0 siblings, 0 replies; 18+ messages in thread From: Blue Swirl @ 2013-01-09 21:18 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > target-mips/dsp_helper.c | 32 +++++++++++++++----------------- > 1 file changed, 15 insertions(+), 17 deletions(-) > > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c > index 1bc77a2..ea7a99f 100644 > --- a/target-mips/dsp_helper.c > +++ b/target-mips/dsp_helper.c > @@ -1352,31 +1352,29 @@ target_ulong helper_modsub(target_ulong rs, target_ulong rt) > > target_ulong helper_raddu_w_qb(target_ulong rs) > { > - uint8_t rs3, rs2, rs1, rs0; > - uint16_t temp; > - > - MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); > - > - temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0; > + target_ulong ret = 0; > + DSP32Value ds; > + unsigned int i; > > - return (target_ulong)temp; > + ds.uw[0] = rs; > + for (i = 0 ; i < 4 ; i++) { Extra space again and below too. > + ret += ds.ub[i]; > + } > + return ret; > } > > #if defined(TARGET_MIPS64) > target_ulong helper_raddu_l_ob(target_ulong rs) > { > - int i; > - uint16_t rs_t[8]; > - uint64_t temp; > - > - temp = 0; > + target_ulong ret = 0; > + DSP64Value ds; > + unsigned int i; > > - for (i = 0; i < 8; i++) { > - rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; > - temp += (uint64_t)rs_t[i]; > + ds.ul[0] = rs; > + for (i = 0 ; i < 8 ; i++) { > + ret += ds.ub[i]; > } > - > - return temp; > + return ret; > } > #endif > > -- > 1.7.10.4 > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v2 8/8] target-mips: implement DSP (d)append sub-class with TCG 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (6 preceding siblings ...) 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions Aurelien Jarno @ 2013-01-09 15:27 ` Aurelien Jarno 2013-01-09 18:51 ` [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Richard Henderson 2013-01-09 21:19 ` Blue Swirl 9 siblings, 0 replies; 18+ messages in thread From: Aurelien Jarno @ 2013-01-09 15:27 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno DSP instruction from the (d)append sub-class can be implemented with TCG. Use a different function for these instructions are they are quite different from compare-pick sub-class. Fix BALIGN instruction for negative value, where the value should be zero-extended before being shift to the right. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-mips/dsp_helper.c | 67 ----------------------- target-mips/helper.h | 13 ----- target-mips/translate.c | 133 ++++++++++++++++++++++++++++++---------------- 3 files changed, 87 insertions(+), 126 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index ea7a99f..b0429d1 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3111,73 +3111,6 @@ PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0); #endif #undef PICK_INSN -#define APPEND_INSN(name, ret_32) \ -target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \ -{ \ - target_ulong temp; \ - \ - if (ret_32) { \ - temp = ((rt & MIPSDSP_LLO) << sa) | \ - ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \ - temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \ - } else { \ - temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \ - } \ - \ - return temp; \ -} - -APPEND_INSN(append, 1); -#ifdef TARGET_MIPS64 -APPEND_INSN(dappend, 0); -#endif -#undef APPEND_INSN - -#define PREPEND_INSN(name, or_val, ret_32) \ -target_ulong helper_##name(target_ulong rs, target_ulong rt, \ - uint32_t sa) \ -{ \ - sa |= or_val; \ - \ - if (1) { \ - return (target_long)(int32_t)(uint32_t) \ - (((rs & MIPSDSP_LLO) << (32 - sa)) | \ - ((rt & MIPSDSP_LLO) >> sa)); \ - } else { \ - return (rs << (64 - sa)) | (rt >> sa); \ - } \ -} - -PREPEND_INSN(prepend, 0, 1); -#ifdef TARGET_MIPS64 -PREPEND_INSN(prependw, 0, 0); -PREPEND_INSN(prependd, 0x20, 0); -#endif -#undef PREPEND_INSN - -#define BALIGN_INSN(name, filter, ret32) \ -target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \ -{ \ - bp = bp & 0x03; \ - \ - if ((bp & 1) == 0) { \ - return rt; \ - } else { \ - if (ret32) { \ - return (target_long)(int32_t)((rt << (8 * bp)) | \ - (rs >> (8 * (4 - bp)))); \ - } else { \ - return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \ - } \ - } \ -} - -BALIGN_INSN(balign, 0x03, 1); -#if defined(TARGET_MIPS64) -BALIGN_INSN(dbalign, 0x07, 0); -#endif -#undef BALIGN_INSN - target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt) { uint32_t rsl, rth; diff --git a/target-mips/helper.h b/target-mips/helper.h index 9ea60ec..cd48738 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -654,19 +654,6 @@ DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env) DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env) DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env) #endif -DEF_HELPER_FLAGS_3(append, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dappend, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -#endif -DEF_HELPER_FLAGS_3(prepend, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(prependd, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -DEF_HELPER_FLAGS_3(prependw, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -#endif -DEF_HELPER_FLAGS_3(balign, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dbalign, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -#endif DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) #if defined(TARGET_MIPS64) DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) diff --git a/target-mips/translate.c b/target-mips/translate.c index 2c238ef..874768b 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -336,7 +336,7 @@ enum { /* DSP Bit/Manipulation Sub-class */ OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, - /* MIPS DSP Compare-Pick Sub-class */ + /* MIPS DSP Append Sub-class */ OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, /* MIPS DSP Accumulator and DSPControl Access Sub-class */ @@ -543,7 +543,7 @@ enum { #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { - /* MIPS DSP Compare-Pick Sub-class */ + /* MIPS DSP Append Sub-class */ OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, @@ -667,7 +667,7 @@ enum { #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { - /* DSP Compare-Pick Sub-class */ + /* DSP Append Sub-class */ OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, @@ -13868,7 +13868,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, int ret, int v1, int v2, int check_ret) { const char *opn = "mipsdsp add compare pick"; - TCGv_i32 t0; TCGv t1; TCGv v1_t; TCGv v2_t; @@ -13879,7 +13878,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, return; } - t0 = tcg_temp_new_i32(); t1 = tcg_temp_new(); v1_t = tcg_temp_new(); v2_t = tcg_temp_new(); @@ -13888,26 +13886,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, gen_load_gpr(v2_t, v2); switch (op1) { - case OPC_APPEND_DSP: - switch (op2) { - case OPC_APPEND: - tcg_gen_movi_i32(t0, v2); - gen_helper_append(cpu_gpr[ret], cpu_gpr[ret], v1_t, t0); - break; - case OPC_PREPEND: - tcg_gen_movi_i32(t0, v2); - gen_helper_prepend(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); - break; - case OPC_BALIGN: - tcg_gen_movi_i32(t0, v2); - gen_helper_balign(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); - break; - default: /* Invid */ - MIPS_INVAL("MASK APPEND"); - generate_exception(ctx, EXCP_RI); - break; - } - break; case OPC_CMPU_EQ_QB_DSP: switch (op2) { case OPC_CMPU_EQ_QB: @@ -14065,23 +14043,95 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, break; } break; +#endif + } + + tcg_temp_free(t1); + tcg_temp_free(v1_t); + tcg_temp_free(v2_t); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} + +static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, + uint32_t op1, int rt, int rs, int sa) +{ + const char *opn = "mipsdsp append/dappend"; + TCGv t0; + + check_dspr2(ctx); + + if (rt == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + + switch (op1) { + case OPC_APPEND_DSP: + switch (MASK_APPEND(ctx->opcode)) { + case OPC_APPEND: + if (sa != 0) { + tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); + } + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + break; + case OPC_PREPEND: + if (sa != 0) { + tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]); + tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); + tcg_gen_shli_tl(t0, t0, 32 - sa); + tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); + } + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + break; + case OPC_BALIGN: + sa &= 3; + if (sa != 0 && sa != 2) { + tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); + tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); + } + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + break; + default: /* Invalid */ + MIPS_INVAL("MASK APPEND"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#ifdef TARGET_MIPS64 case OPC_DAPPEND_DSP: - switch (op2) { + switch (MASK_DAPPEND(ctx->opcode)) { case OPC_DAPPEND: - tcg_gen_movi_i32(t0, v2); - gen_helper_dappend(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + if (sa != 0) { + tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); + } break; case OPC_PREPENDD: - tcg_gen_movi_i32(t0, v2); - gen_helper_prependd(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa); + tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); + tcg_gen_or_tl(cpu_gpr[rt], t0, t0); break; case OPC_PREPENDW: - tcg_gen_movi_i32(t0, v2); - gen_helper_prependw(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + if (sa != 0) { + tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); + tcg_gen_shli_tl(t0, t0, 64 - sa); + tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); + } break; case OPC_DBALIGN: - tcg_gen_movi_i32(t0, v2); - gen_helper_dbalign(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + sa &= 7; + if (sa != 0 && sa != 2 && sa != 4) { + tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); + tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); + tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); + } break; default: /* Invalid */ MIPS_INVAL("MASK DAPPEND"); @@ -14091,12 +14141,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, break; #endif } - - tcg_temp_free_i32(t0); - tcg_temp_free(t1); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); - + tcg_temp_free(t0); (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s", opn); } @@ -14915,9 +14960,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } break; case OPC_APPEND_DSP: - check_dspr2(ctx); - op2 = MASK_APPEND(ctx->opcode); - gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); + gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); break; case OPC_EXTR_W_DSP: op2 = MASK_EXTR_W(ctx->opcode); @@ -15091,9 +15134,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } break; case OPC_DAPPEND_DSP: - check_dspr2(ctx); - op2 = MASK_DAPPEND(ctx->opcode); - gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); + gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); break; case OPC_DEXTR_W_DSP: op2 = MASK_DEXTR_W(ctx->opcode); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (7 preceding siblings ...) 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 8/8] target-mips: implement DSP (d)append sub-class with TCG Aurelien Jarno @ 2013-01-09 18:51 ` Richard Henderson 2013-01-09 21:19 ` Blue Swirl 9 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2013-01-09 18:51 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On 01/09/2013 07:27 AM, Aurelien Jarno wrote: > Aurelien Jarno (8): > target-mips: fix DSP loads with rd = 0 > target-mips: copy insn_flags in DisasContext > target-mips: generate a reserved instruction exception on CPU without DSP > target-mips: add unions to access DSP elements > target-mips: use DSP unions for binary DSP operators > target-mips: use DSP unions for unary DSP operators > target-mips: use DSP unions for reduction add instructions > target-mips: implement DSP (d)append sub-class with TCG > > target-mips/dsp_helper.c | 623 ++++++++++--------------------- > target-mips/helper.h | 13 - > target-mips/translate.c | 912 ++++++++++++++++++++++++---------------------- > 3 files changed, 670 insertions(+), 878 deletions(-) Reviewed-by: Richard Henderson <rth@twiddle.net> r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno ` (8 preceding siblings ...) 2013-01-09 18:51 ` [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Richard Henderson @ 2013-01-09 21:19 ` Blue Swirl 9 siblings, 0 replies; 18+ messages in thread From: Blue Swirl @ 2013-01-09 21:19 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel On Wed, Jan 9, 2013 at 3:27 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > This patch series contains some fixes and cleanup following the merge > of the DSP ASE patches. Please fix the spacing in the for loops. > > Changes v1 -> v2: > - patch 1: unchanged > - patch 2: new patch as suggested by Richard Henderson > - patch 3: updated to use insn_flags from DisasContext > - patch 4: unchanged > - patch 5: fix the cast on the return value > - patch 6: fix the cast on the return value > - patch 7: unchanged > - patch 8: unchanged > > > Aurelien Jarno (8): > target-mips: fix DSP loads with rd = 0 > target-mips: copy insn_flags in DisasContext > target-mips: generate a reserved instruction exception on CPU without DSP > target-mips: add unions to access DSP elements > target-mips: use DSP unions for binary DSP operators > target-mips: use DSP unions for unary DSP operators > target-mips: use DSP unions for reduction add instructions > target-mips: implement DSP (d)append sub-class with TCG > > target-mips/dsp_helper.c | 623 ++++++++++--------------------- > target-mips/helper.h | 13 - > target-mips/translate.c | 912 ++++++++++++++++++++++++---------------------- > 3 files changed, 670 insertions(+), 878 deletions(-) > > -- > 1.7.10.4 > > ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2013-01-12 15:09 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-01-09 15:27 [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 2/8] target-mips: copy insn_flags in DisasContext Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements Aurelien Jarno 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators Aurelien Jarno 2013-01-09 21:16 ` Blue Swirl 2013-01-10 7:08 ` Aurelien Jarno 2013-01-12 10:39 ` Blue Swirl 2013-01-12 14:34 ` Aurelien Jarno 2013-01-12 15:08 ` Blue Swirl 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 6/8] target-mips: use DSP unions for unary " Aurelien Jarno 2013-01-09 21:17 ` Blue Swirl 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions Aurelien Jarno 2013-01-09 21:18 ` Blue Swirl 2013-01-09 15:27 ` [Qemu-devel] [PATCH v2 8/8] target-mips: implement DSP (d)append sub-class with TCG Aurelien Jarno 2013-01-09 18:51 ` [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup Richard Henderson 2013-01-09 21:19 ` Blue Swirl
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