From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tv25I-0007po-5k for qemu-devel@nongnu.org; Tue, 15 Jan 2013 03:41:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tv25B-0004Ht-HB for qemu-devel@nongnu.org; Tue, 15 Jan 2013 03:41:28 -0500 Received: from mx1.redhat.com ([209.132.183.28]:57894) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tv25A-0004HP-Vl for qemu-devel@nongnu.org; Tue, 15 Jan 2013 03:41:21 -0500 Date: Tue, 15 Jan 2013 09:41:04 +0100 From: Igor Mammedov Message-ID: <20130115094104.73ca60af@thinkpad.mammed.net> In-Reply-To: <1355180372-6525-2-git-send-email-afaerber@suse.de> References: <1355180372-6525-1-git-send-email-afaerber@suse.de> <1355180372-6525-2-git-send-email-afaerber@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC qom-cpu v2 1/2] target-i386: Convert CPU definitions into X86CPU subclasses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?UTF-8?B?RsOkcmJlcg==?= Cc: blauwirbel@gmail.com, qemu-devel@nongnu.org, anthony@codemonkey.ws, ehabkost@redhat.com On Mon, 10 Dec 2012 23:59:31 +0100 Andreas F=C3=A4rber wrote: > TODO: sort classes for -cpu ?, generalize X86CPUListState, more testing >=20 > Signed-off-by: Andreas F=C3=A4rber > Cc: Eduardo Habkost > Cc: Igor Mammedov > --- > target-i386/cpu-qom.h | 17 + > target-i386/cpu.c | 1481 +++++++++++++++++++++++++++++--------------= ------ > target-i386/helper.c | 24 - > 3 Dateien ge=C3=A4ndert, 911 Zeilen hinzugef=C3=BCgt(+), 611 Zeilen entf= ernt(-) >=20 > diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h > index 5901140..19f5aa7 100644 > --- a/target-i386/cpu-qom.h > +++ b/target-i386/cpu-qom.h > @@ -49,6 +49,23 @@ typedef struct X86CPUClass { > /*< public >*/ > =20 > void (*parent_reset)(CPUState *cpu); > + > + uint32_t level; > + uint32_t vendor1, vendor2, vendor3; > + int family; > + int model; > + int stepping; > + int tsc_khz; > + uint32_t features, ext_features, ext2_features, ext3_features; > + uint32_t kvm_features, svm_features; > + uint32_t xlevel; > + char model_id[48]; > + int vendor_override; > + /* Store the results of Centaur's CPUID instructions */ > + uint32_t ext4_features; > + uint32_t xlevel2; > + /* The feature bits on CPUID[EAX=3D7,ECX=3D0].EBX */ > + uint32_t cpuid_7_0_ebx_features; > } X86CPUClass; > =20 > /** > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 6465040..c59c6a5 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -271,26 +271,6 @@ static void add_flagname_to_bitmaps(const char *flag= name, uint32_t *features, > fprintf(stderr, "CPU feature %s not found\n", flagname); > } > =20 > -typedef struct x86_def_t { > - const char *name; > - uint32_t level; > - uint32_t vendor1, vendor2, vendor3; > - int family; > - int model; > - int stepping; > - int tsc_khz; > - uint32_t features, ext_features, ext2_features, ext3_features; > - uint32_t kvm_features, svm_features; > - uint32_t xlevel; > - char model_id[48]; > - int vendor_override; > - /* Store the results of Centaur's CPUID instructions */ > - uint32_t ext4_features; > - uint32_t xlevel2; > - /* The feature bits on CPUID[EAX=3D7,ECX=3D0].EBX */ > - uint32_t cpuid_7_0_ebx_features; > -} x86_def_t; > - > #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) > #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ > CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) > @@ -331,488 +311,735 @@ typedef struct x86_def_t { > =20 > /* built-in cpu model definitions > */ > -static x86_def_t builtin_x86_defs[] =3D { > - { > - .name =3D "qemu64", > - .level =3D 4, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 6, > - .model =3D 2, > - .stepping =3D 3, > - .features =3D PPRO_FEATURES | > + > +#define TYPE(x) x "-" TYPE_X86_CPU > + > +static void qemu64_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + xcc->level =3D 4; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 6; > + xcc->model =3D 2; > + xcc->stepping =3D 3; > + xcc->features =3D PPRO_FEATURES | > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | > - CPUID_PSE36, > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_PO= PCNT, > - .ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > - CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, > - .ext3_features =3D CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | > - CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, > - .xlevel =3D 0x8000000A, > - }, > - { > - .name =3D "phenom", > - .level =3D 5, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 16, > - .model =3D 2, > - .stepping =3D 3, > - .features =3D PPRO_FEATURES | > + CPUID_PSE36; > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_PO= PCNT; > + xcc->ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | > + CPUID_EXT3_ABM | CPUID_EXT3_SSE4A; > + xcc->xlevel =3D 0x8000000A; > + > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "QEMU Virtual CPU version "); > + pstrcat(xcc->model_id, sizeof(xcc->model_id), > + qemu_get_version()); > +} > + > +static const TypeInfo qemu64_cpu_type_info =3D { > + .name =3D TYPE("qemu64"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D qemu64_cpu_class_init, > +}; > + > +static void phenom_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 5; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 16; > + xcc->model =3D 2; > + xcc->stepping =3D 3; > + xcc->features =3D PPRO_FEATURES | > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | > - CPUID_PSE36 | CPUID_VME | CPUID_HT, > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _CX16 | > - CPUID_EXT_POPCNT, > - .ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > + CPUID_PSE36 | CPUID_VME | CPUID_HT; > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _CX16 | > + CPUID_EXT_POPCNT; > + xcc->ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | > CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | > - CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, > + CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP; > /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, > CPUID_EXT3_CR8LEG, > CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, > CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ > - .ext3_features =3D CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | > - CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, > - .svm_features =3D CPUID_SVM_NPT | CPUID_SVM_LBRV, > - .xlevel =3D 0x8000001A, > - .model_id =3D "AMD Phenom(tm) 9550 Quad-Core Processor" > - }, > - { > - .name =3D "core2duo", > - .level =3D 10, > - .family =3D 6, > - .model =3D 15, > - .stepping =3D 11, > - .features =3D PPRO_FEATURES | > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | > + CPUID_EXT3_ABM | CPUID_EXT3_SSE4A; > + xcc->svm_features =3D CPUID_SVM_NPT | CPUID_SVM_LBRV; > + xcc->xlevel =3D 0x8000001A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "AMD Phenom(tm) 9550 Quad-Core Processor"); > +} > + > +static const TypeInfo phenom_cpu_type_info =3D { > + .name =3D TYPE("phenom"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D phenom_cpu_class_init, > +}; > + > +static void core2duo_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 10; > + xcc->family =3D 6; > + xcc->model =3D 15; > + xcc->stepping =3D 11; > + xcc->features =3D PPRO_FEATURES | > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | > CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | > - CPUID_HT | CPUID_TM | CPUID_PBE, > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _SSSE3 | > + CPUID_HT | CPUID_TM | CPUID_PBE; > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _SSSE3 | > CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_E= XT_EST | > - CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_= PDCM, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EX= T2_NX, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x80000008, > - .model_id =3D "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", > - }, > - { > - .name =3D "kvm64", > - .level =3D 5, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 15, > - .model =3D 6, > - .stepping =3D 1, > + CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_= PDCM; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EX= T2_NX; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz"); > +} > + > +static const TypeInfo core2duo_cpu_type_info =3D { > + .name =3D TYPE("core2duo"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D core2duo_cpu_class_init, > +}; > + > +static void kvm64_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 5; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 15; > + xcc->model =3D 6; > + xcc->stepping =3D 1; > /* Missing: CPUID_VME, CPUID_HT */ > - .features =3D PPRO_FEATURES | > + xcc->features =3D PPRO_FEATURES | > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | > - CPUID_PSE36, > + CPUID_PSE36; > /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_CX16, > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_CX16; > /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ > - .ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > - CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, > + xcc->ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX; > /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_E= XTAPIC, > CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, > CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, > CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ > - .ext3_features =3D 0, > - .xlevel =3D 0x80000008, > - .model_id =3D "Common KVM processor" > - }, > - { > - .name =3D "qemu32", > - .level =3D 4, > - .family =3D 6, > - .model =3D 3, > - .stepping =3D 3, > - .features =3D PPRO_FEATURES, > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, > - .xlevel =3D 0x80000004, > - }, > - { > - .name =3D "kvm32", > - .level =3D 5, > - .family =3D 15, > - .model =3D 6, > - .stepping =3D 1, > - .features =3D PPRO_FEATURES | > - CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, > - .ext_features =3D CPUID_EXT_SSE3, > - .ext2_features =3D PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES, > - .ext3_features =3D 0, > - .xlevel =3D 0x80000008, > - .model_id =3D "Common 32-bit KVM processor" > - }, > - { > - .name =3D "coreduo", > - .level =3D 10, > - .family =3D 6, > - .model =3D 14, > - .stepping =3D 8, > - .features =3D PPRO_FEATURES | CPUID_VME | > + xcc->ext3_features =3D 0; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Common KVM processor"); > +} > + > +static const TypeInfo kvm64_cpu_type_info =3D { > + .name =3D TYPE("kvm64"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D kvm64_cpu_class_init, > +}; > + > +static void qemu32_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 4; > + xcc->family =3D 6; > + xcc->model =3D 3; > + xcc->stepping =3D 3; > + xcc->features =3D PPRO_FEATURES; > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_POPCNT; > + xcc->xlevel =3D 0x80000004; > + > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "QEMU Virtual CPU version "); > + pstrcat(xcc->model_id, sizeof(xcc->model_id), > + qemu_get_version()); > +} > + > +static const TypeInfo qemu32_cpu_type_info =3D { > + .name =3D TYPE("qemu32"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D qemu32_cpu_class_init, > +}; > + > +static void kvm32_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 5; > + xcc->family =3D 15; > + xcc->model =3D 6; > + xcc->stepping =3D 1; > + xcc->features =3D PPRO_FEATURES | > + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36; > + xcc->ext_features =3D CPUID_EXT_SSE3; > + xcc->ext2_features =3D PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES; > + xcc->ext3_features =3D 0; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Common 32-bit KVM processor"); > +} > + > +static const TypeInfo kvm32_cpu_type_info =3D { > + .name =3D TYPE("kvm32"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D kvm32_cpu_class_init, > +}; > + > +static void coreduo_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 10; > + xcc->family =3D 6; > + xcc->model =3D 14; > + xcc->stepping =3D 8; > + xcc->features =3D PPRO_FEATURES | CPUID_VME | > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_A= CPI | > - CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _VMX | > - CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_P= DCM, > - .ext2_features =3D CPUID_EXT2_NX, > - .xlevel =3D 0x80000008, > - .model_id =3D "Genuine Intel(R) CPU T2600 @ 2.16GHz", > - }, > - { > - .name =3D "486", > - .level =3D 1, > - .family =3D 4, > - .model =3D 0, > - .stepping =3D 0, > - .features =3D I486_FEATURES, > - .xlevel =3D 0, > - }, > - { > - .name =3D "pentium", > - .level =3D 1, > - .family =3D 5, > - .model =3D 4, > - .stepping =3D 3, > - .features =3D PENTIUM_FEATURES, > - .xlevel =3D 0, > - }, > - { > - .name =3D "pentium2", > - .level =3D 2, > - .family =3D 6, > - .model =3D 5, > - .stepping =3D 2, > - .features =3D PENTIUM2_FEATURES, > - .xlevel =3D 0, > - }, > - { > - .name =3D "pentium3", > - .level =3D 2, > - .family =3D 6, > - .model =3D 7, > - .stepping =3D 3, > - .features =3D PENTIUM3_FEATURES, > - .xlevel =3D 0, > - }, > - { > - .name =3D "athlon", > - .level =3D 2, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 6, > - .model =3D 2, > - .stepping =3D 3, > - .features =3D PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MT= RR | > - CPUID_MCA, > - .ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > - CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, > - .xlevel =3D 0x80000008, > - }, > - { > - .name =3D "n270", > - /* original is on level 10 */ > - .level =3D 5, > - .family =3D 6, > - .model =3D 28, > - .stepping =3D 2, > - .features =3D PPRO_FEATURES | > + CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE; > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _VMX | > + CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_P= DCM; > + xcc->ext2_features =3D CPUID_EXT2_NX; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Genuine Intel(R) CPU T2600 @ 2.16GHz"); > +} > + > +static const TypeInfo coreduo_cpu_type_info =3D { > + .name =3D TYPE("coreduo"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D coreduo_cpu_class_init, > +}; > + > +static void i486_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 1; > + xcc->family =3D 4; > + xcc->model =3D 0; > + xcc->stepping =3D 0; > + xcc->features =3D I486_FEATURES; > + xcc->xlevel =3D 0; > +} > + > +static const TypeInfo i486_cpu_type_info =3D { > + .name =3D TYPE("486"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D i486_cpu_class_init, > +}; > + > +static void pentium_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 1; > + xcc->family =3D 5; > + xcc->model =3D 4; > + xcc->stepping =3D 3; > + xcc->features =3D PENTIUM_FEATURES; > + xcc->xlevel =3D 0; > +} > + > +static const TypeInfo pentium_cpu_type_info =3D { > + .name =3D TYPE("pentium"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D pentium_cpu_class_init, > +}; > + > +static void pentium2_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 2; > + xcc->family =3D 6; > + xcc->model =3D 5; > + xcc->stepping =3D 2; > + xcc->features =3D PENTIUM2_FEATURES; > + xcc->xlevel =3D 0; > +} > + > +static const TypeInfo pentium2_cpu_type_info =3D { > + .name =3D TYPE("pentium2"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D pentium2_cpu_class_init, > +}; > + > +static void pentium3_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 2; > + xcc->family =3D 6; > + xcc->model =3D 7; > + xcc->stepping =3D 3; > + xcc->features =3D PENTIUM3_FEATURES; > + xcc->xlevel =3D 0; > +} > + > +static const TypeInfo pentium3_cpu_type_info =3D { > + .name =3D TYPE("pentium3"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D pentium3_cpu_class_init, > +}; > + > +static void athlon_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 2; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 6; > + xcc->model =3D 2; > + xcc->stepping =3D 3; > + xcc->features =3D PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MT= RR | > + CPUID_MCA; > + xcc->ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > + CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT; > + xcc->xlevel =3D 0x80000008; > + > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "QEMU Virtual CPU version "); > + pstrcat(xcc->model_id, sizeof(xcc->model_id), > + qemu_get_version()); > +} > + > +static const TypeInfo athlon_cpu_type_info =3D { > + .name =3D TYPE("athlon"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D athlon_cpu_class_init, > +}; > + > +static void n270_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + /* original is on level 10 */ > + xcc->level =3D 5; > + xcc->family =3D 6; > + xcc->model =3D 28; > + xcc->stepping =3D 2; > + xcc->features =3D PPRO_FEATURES | > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_D= TS | > - CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, > + CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE; > /* Some CPUs got no CPUID_SEP */ > - .ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _SSSE3 | > - CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_= XTPR, > - .ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > - CPUID_EXT2_NX, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", > - }, > - { > - .name =3D "Conroe", > - .level =3D 2, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 6, > - .model =3D 2, > - .stepping =3D 3, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + xcc->ext_features =3D CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT= _SSSE3 | > + CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_= XTPR; > + xcc->ext2_features =3D (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | > + CPUID_EXT2_NX; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel(R) Atom(TM) CPU N270 @ 1.60GHz"); > +} > + > +static const TypeInfo n270_cpu_type_info =3D { > + .name =3D TYPE("n270"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D n270_cpu_class_init, > +}; > + > +static void conroe_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 2; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 6; > + xcc->model =3D 2; > + xcc->stepping =3D 3; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SY= SCALL, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", > - }, > - { > - .name =3D "Penryn", > - .level =3D 2, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 6, > - .model =3D 2, > - .stepping =3D 3, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_SSSE3 | CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SY= SCALL; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"); > +} > + > +static const TypeInfo conroe_cpu_type_info =3D { > + .name =3D TYPE("Conroe"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D conroe_cpu_class_init, > +}; > + > +static void penryn_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 2; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 6; > + xcc->model =3D 2; > + xcc->stepping =3D 3; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_S= SSE3 | > - CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SY= SCALL, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", > - }, > - { > - .name =3D "Nehalem", > - .level =3D 2, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 6, > - .model =3D 2, > - .stepping =3D 3, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_S= SSE3 | > + CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SY= SCALL; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"); > +} > + > +static const TypeInfo penryn_cpu_type_info =3D { > + .name =3D TYPE("Penryn"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D penryn_cpu_class_init, > +}; > + > +static void nehalem_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 2; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 6; > + xcc->model =3D 2; > + xcc->stepping =3D 3; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT= _SSE41 | > - CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EX= T2_NX, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Intel Core i7 9xx (Nehalem Class Core i7)", > - }, > - { > - .name =3D "Westmere", > - .level =3D 11, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 6, > - .model =3D 44, > - .stepping =3D 1, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT= _SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EX= T2_NX; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel Core i7 9xx (Nehalem Class Core i7)"); > +} > + > +static const TypeInfo nehalem_cpu_type_info =3D { > + .name =3D TYPE("Nehalem"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D nehalem_cpu_class_init, > +}; > + > +static void westmere_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 11; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 6; > + xcc->model =3D 44; > + xcc->stepping =3D 1; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_S= SE42 | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_S= SE42 | > CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > - CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EX= T2_NX, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Westmere E56xx/L56xx/X56xx (Nehalem-C)", > - }, > - { > - .name =3D "SandyBridge", > - .level =3D 0xd, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 6, > - .model =3D 42, > - .stepping =3D 1, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EX= T2_NX; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Westmere E56xx/L56xx/X56xx (Nehalem-C)"); > +} > + > +static const TypeInfo westmere_cpu_type_info =3D { > + .name =3D TYPE("Westmere"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D westmere_cpu_class_init, > +}; > + > +static void sandybridge_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 0xd; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 6; > + xcc->model =3D 42; > + xcc->stepping =3D 1; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AE= S | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AE= S | > CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | > CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | > - CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_NX | > - CPUID_EXT2_SYSCALL, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Intel Xeon E312xx (Sandy Bridge)", > - }, > - { > - .name =3D "Haswell", > - .level =3D 0xd, > - .vendor1 =3D CPUID_VENDOR_INTEL_1, > - .vendor2 =3D CPUID_VENDOR_INTEL_2, > - .vendor3 =3D CPUID_VENDOR_INTEL_3, > - .family =3D 6, > - .model =3D 60, > - .stepping =3D 1, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_NX | > + CPUID_EXT2_SYSCALL; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel Xeon E312xx (Sandy Bridge)"); > +} > + > +static const TypeInfo sandybridge_cpu_type_info =3D { > + .name =3D TYPE("SandyBridge"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D sandybridge_cpu_class_init, > +}; > + > +static void haswell_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 0xd; > + xcc->vendor1 =3D CPUID_VENDOR_INTEL_1; > + xcc->vendor2 =3D CPUID_VENDOR_INTEL_2; > + xcc->vendor3 =3D CPUID_VENDOR_INTEL_3; > + xcc->family =3D 6; > + xcc->model =3D 60; > + xcc->stepping =3D 1; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AE= S | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AE= S | > CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | > CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | > CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MO= VBE | > - CPUID_EXT_PCID, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_NX | > - CPUID_EXT2_SYSCALL, > - .ext3_features =3D CPUID_EXT3_LAHF_LM, > - .cpuid_7_0_ebx_features =3D CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_E= BX_BMI1 | > + CPUID_EXT_PCID; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_NX | > + CPUID_EXT2_SYSCALL; > + xcc->ext3_features =3D CPUID_EXT3_LAHF_LM; > + xcc->cpuid_7_0_ebx_features =3D CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_E= BX_BMI1 | > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVP= CID | > - CPUID_7_0_EBX_RTM, > - .xlevel =3D 0x8000000A, > - .model_id =3D "Intel Core Processor (Haswell)", > - }, > - { > - .name =3D "Opteron_G1", > - .level =3D 5, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 15, > - .model =3D 6, > - .stepping =3D 1, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_7_0_EBX_RTM; > + xcc->xlevel =3D 0x8000000A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "Intel Core Processor (Haswell)"); > +} > + > +static const TypeInfo haswell_cpu_type_info =3D { > + .name =3D TYPE("Haswell"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D haswell_cpu_class_init, > +}; > + > +static void opteron_g1_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 5; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 15; > + xcc->model =3D 6; > + xcc->stepping =3D 1; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_= MMX | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_= MMX | > CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | > CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | > CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | > CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EX= T2_MSR | > - CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT= 2_FPU, > - .xlevel =3D 0x80000008, > - .model_id =3D "AMD Opteron 240 (Gen 1 Class Opteron)", > - }, > - { > - .name =3D "Opteron_G2", > - .level =3D 5, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 15, > - .model =3D 6, > - .stepping =3D 1, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT= 2_FPU; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "AMD Opteron 240 (Gen 1 Class Opteron)"); > +} > + > +static const TypeInfo opteron_g1_cpu_type_info =3D { > + .name =3D TYPE("Opteron_G1"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D opteron_g1_cpu_class_init, > +}; > + > +static void opteron_g2_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 5; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 15; > + xcc->model =3D 6; > + xcc->stepping =3D 1; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_CX16 | CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_FXSR | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_CX16 | CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_FXSR | > CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | > CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | > CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | > CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | > CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EX= T2_PSE | > - CPUID_EXT2_DE | CPUID_EXT2_FPU, > - .ext3_features =3D CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x80000008, > - .model_id =3D "AMD Opteron 22xx (Gen 2 Class Opteron)", > - }, > - { > - .name =3D "Opteron_G3", > - .level =3D 5, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 15, > - .model =3D 6, > - .stepping =3D 1, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_EXT2_DE | CPUID_EXT2_FPU; > + xcc->ext3_features =3D CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "AMD Opteron 22xx (Gen 2 Class Opteron)"); > +} > + > +static const TypeInfo opteron_g2_cpu_type_info =3D { > + .name =3D TYPE("Opteron_G2"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D opteron_g2_cpu_class_init, > +}; > + > +static void opteron_g3_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 5; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 15; > + xcc->model =3D 6; > + xcc->stepping =3D 1; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_= MONITOR | > - CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_FXSR | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_= MONITOR | > + CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT= 2_FXSR | > CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | > CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | > CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | > CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | > CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EX= T2_PSE | > - CPUID_EXT2_DE | CPUID_EXT2_FPU, > - .ext3_features =3D CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | > - CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x80000008, > - .model_id =3D "AMD Opteron 23xx (Gen 3 Class Opteron)", > - }, > - { > - .name =3D "Opteron_G4", > - .level =3D 0xd, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 21, > - .model =3D 1, > - .stepping =3D 2, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_EXT2_DE | CPUID_EXT2_FPU; > + xcc->ext3_features =3D CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | > + CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x80000008; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "AMD Opteron 23xx (Gen 3 Class Opteron)"); > +} > + > +static const TypeInfo opteron_g3_cpu_type_info =3D { > + .name =3D TYPE("Opteron_G3"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D opteron_g3_cpu_class_init, > +}; > + > +static void opteron_g4_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 0xd; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 21; > + xcc->model =3D 1; > + xcc->stepping =3D 2; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AE= S | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AE= S | > CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | > - CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > + CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | > CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | > CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | > CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | > CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EX= T2_MSR | > - CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT= 2_FPU, > - .ext3_features =3D CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | > + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT= 2_FPU; > + xcc->ext3_features =3D CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | > CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | > CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | > - CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000001A, > - .model_id =3D "AMD Opteron 62xx class CPU", > - }, > - { > - .name =3D "Opteron_G5", > - .level =3D 0xd, > - .vendor1 =3D CPUID_VENDOR_AMD_1, > - .vendor2 =3D CPUID_VENDOR_AMD_2, > - .vendor3 =3D CPUID_VENDOR_AMD_3, > - .family =3D 21, > - .model =3D 2, > - .stepping =3D 0, > - .features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000001A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "AMD Opteron 62xx class CPU"); > +} > + > +static const TypeInfo opteron_g4_cpu_type_info =3D { > + .name =3D TYPE("Opteron_G4"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D opteron_g4_cpu_class_init, > +}; > + > +static void opteron_g5_cpu_class_init(ObjectClass *oc, void *data) > +{ > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + > + xcc->level =3D 0xd; > + xcc->vendor1 =3D CPUID_VENDOR_AMD_1; > + xcc->vendor2 =3D CPUID_VENDOR_AMD_2; > + xcc->vendor3 =3D CPUID_VENDOR_AMD_3; > + xcc->family =3D 21; > + xcc->model =3D 2; > + xcc->stepping =3D 0; > + xcc->features =3D CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUI= D_MCA | > CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8= | > CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > - CPUID_DE | CPUID_FP87, > - .ext_features =3D CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSA= VE | > + CPUID_DE | CPUID_FP87; > + xcc->ext_features =3D CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSA= VE | > CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | > CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | > - CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, > - .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > + CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3; > + xcc->ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | > CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | > CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | > CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | > CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EX= T2_MSR | > - CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT= 2_FPU, > - .ext3_features =3D CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3= _XOP | > + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT= 2_FPU; > + xcc->ext3_features =3D CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3= _XOP | > CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | > CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | > - CPUID_EXT3_LAHF_LM, > - .xlevel =3D 0x8000001A, > - .model_id =3D "AMD Opteron 63xx class CPU", > - }, > + CPUID_EXT3_LAHF_LM; > + xcc->xlevel =3D 0x8000001A; > + pstrcpy(xcc->model_id, sizeof(xcc->model_id), > + "AMD Opteron 63xx class CPU"); > +} > + > +static const TypeInfo opteron_g5_cpu_type_info =3D { > + .name =3D TYPE("Opteron_G5"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D opteron_g5_cpu_class_init, > }; > =20 > #ifdef CONFIG_KVM > @@ -832,61 +1059,60 @@ static int cpu_x86_fill_model_id(char *str) > } > #endif > =20 > -/* Fill a x86_def_t struct with information about the host CPU, and > +#ifdef CONFIG_KVM > + > +/* Fill a CPU class with information about the host CPU, and > * the CPU features supported by the host hardware + host kernel > - * > - * This function may be called only if KVM is enabled. > */ > -static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) > +static void kvm_host_cpu_class_init(ObjectClass *oc, void *data) > { > -#ifdef CONFIG_KVM > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > KVMState *s =3D kvm_state; > uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; > =20 > assert(kvm_enabled()); > =20 > - x86_cpu_def->name =3D "host"; > host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); > - x86_cpu_def->vendor1 =3D ebx; > - x86_cpu_def->vendor2 =3D edx; > - x86_cpu_def->vendor3 =3D ecx; > + xcc->vendor1 =3D ebx; > + xcc->vendor2 =3D edx; > + xcc->vendor3 =3D ecx; > =20 > host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); > - x86_cpu_def->family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); > - x86_cpu_def->model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); > - x86_cpu_def->stepping =3D eax & 0x0F; > + xcc->family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); > + xcc->model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); > + xcc->stepping =3D eax & 0x0F; > =20 > - x86_cpu_def->level =3D kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX= ); > - x86_cpu_def->features =3D kvm_arch_get_supported_cpuid(s, 0x1, 0, R_= EDX); > - x86_cpu_def->ext_features =3D kvm_arch_get_supported_cpuid(s, 0x1, 0= , R_ECX); > + xcc->level =3D kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); > + xcc->features =3D kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX); > + xcc->ext_features =3D kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX); > =20 > - if (x86_cpu_def->level >=3D 7) { > - x86_cpu_def->cpuid_7_0_ebx_features =3D > + if (xcc->level >=3D 7) { > + xcc->cpuid_7_0_ebx_features =3D > kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX); > } else { > - x86_cpu_def->cpuid_7_0_ebx_features =3D 0; > + xcc->cpuid_7_0_ebx_features =3D 0; > } > =20 > - x86_cpu_def->xlevel =3D kvm_arch_get_supported_cpuid(s, 0x80000000, = 0, R_EAX); > - x86_cpu_def->ext2_features =3D > + xcc->xlevel =3D kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX= ); > + xcc->ext2_features =3D > kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX); > - x86_cpu_def->ext3_features =3D > + xcc->ext3_features =3D > kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX); > =20 > - cpu_x86_fill_model_id(x86_cpu_def->model_id); > - x86_cpu_def->vendor_override =3D 0; > + cpu_x86_fill_model_id(xcc->model_id); > + xcc->vendor_override =3D 0; > =20 > /* Call Centaur's CPUID instruction. */ > - if (x86_cpu_def->vendor1 =3D=3D CPUID_VENDOR_VIA_1 && > - x86_cpu_def->vendor2 =3D=3D CPUID_VENDOR_VIA_2 && > - x86_cpu_def->vendor3 =3D=3D CPUID_VENDOR_VIA_3) { > + if (xcc->vendor1 =3D=3D CPUID_VENDOR_VIA_1 && > + xcc->vendor2 =3D=3D CPUID_VENDOR_VIA_2 && > + xcc->vendor3 =3D=3D CPUID_VENDOR_VIA_3) { > host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); > eax =3D kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); > if (eax >=3D 0xC0000001) { > /* Support VIA max extended level */ > - x86_cpu_def->xlevel2 =3D eax; > + xcc->xlevel2 =3D eax; > host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); > - x86_cpu_def->ext4_features =3D > + xcc->ext4_features =3D > kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX= ); > } > } > @@ -897,10 +1123,17 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_d= ef) > * available on the host hardware. Just set all bits and mask out the > * unsupported ones later. > */ > - x86_cpu_def->svm_features =3D -1; > -#endif /* CONFIG_KVM */ > + xcc->svm_features =3D -1; > } > =20 > +static const TypeInfo kvm_host_cpu_type_info =3D { > + .name =3D TYPE("host"), > + .parent =3D TYPE_X86_CPU, > + .class_init =3D kvm_host_cpu_class_init, > +}; > + > +#endif /* CONFIG_KVM */ > + > static int unavailable_host_feature(struct model_features_t *f, uint32_t= mask) > { > int i; > @@ -922,24 +1155,24 @@ static int unavailable_host_feature(struct model_f= eatures_t *f, uint32_t mask) > * > * This function may be called only if KVM is enabled. > */ > -static int kvm_check_features_against_host(x86_def_t *guest_def) > +static int kvm_check_features_against_host(X86CPU *guest_cpu) > { > - x86_def_t host_def; > + CPUX86State *guest_env =3D &guest_cpu->env; > + X86CPUClass *host_xcc =3D X86_CPU_CLASS(object_class_by_name(TYPE("h= ost"))); > uint32_t mask; > int rv, i; > struct model_features_t ft[] =3D { > - {&guest_def->features, &host_def.features, > + {&guest_env->cpuid_features, &host_xcc->features, > ~0, feature_name, 0x00000000}, > - {&guest_def->ext_features, &host_def.ext_features, > + {&guest_env->cpuid_ext_features, &host_xcc->ext_features, > ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001}, > - {&guest_def->ext2_features, &host_def.ext2_features, > + {&guest_env->cpuid_ext2_features, &host_xcc->ext2_features, > ~PPRO_FEATURES, ext2_feature_name, 0x80000000}, > - {&guest_def->ext3_features, &host_def.ext3_features, > + {&guest_env->cpuid_ext3_features, &host_xcc->ext3_features, > ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}}; > =20 > assert(kvm_enabled()); > =20 > - kvm_cpu_fill_host(&host_def); > for (rv =3D 0, i =3D 0; i < ARRAY_SIZE(ft); ++i) > for (mask =3D 1; mask; mask <<=3D 1) > if (ft[i].check_feat & mask && *ft[i].guest_feat & mask && > @@ -1203,26 +1436,12 @@ static void x86_cpuid_set_tsc_freq(Object *obj, V= isitor *v, void *opaque, > cpu->env.tsc_khz =3D value / 1000; > } > =20 > -static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name) > -{ > - int i; > - > - for (i =3D 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { > - x86_def_t *def =3D &builtin_x86_defs[i]; > - if (strcmp(name, def->name) =3D=3D 0) { > - memcpy(x86_cpu_def, def, sizeof(*def)); > - return 0; > - } > - } > - > - return -1; > -} > - > /* Parse "+feature,-feature,feature=3Dfoo" CPU feature string > */ > -static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *featur= es) > +static int cpu_x86_parse_featurestr(X86CPU *cpu, char *features) > { > - unsigned int i; > + CPUX86State *env =3D &cpu->env; > + Error *error =3D NULL; > char *featurestr; /* Single 'key=3Dvalue" string being parsed */ > /* Features to be added */ > uint32_t plus_features =3D 0, plus_ext_features =3D 0; > @@ -1259,27 +1478,39 @@ static int cpu_x86_parse_featurestr(x86_def_t *x8= 6_cpu_def, char *features) > if (!strcmp(featurestr, "family")) { > char *err; > numvalue =3D strtoul(val, &err, 0); > - if (!*val || *err || numvalue > 0xff + 0xf) { > + if (!*val || *err) { > fprintf(stderr, "bad numerical value %s\n", val); > goto error; > } > - x86_cpu_def->family =3D numvalue; > + object_property_set_int(OBJECT(cpu), numvalue, "family", > + &error); > + if (error !=3D NULL) { > + goto error; > + } > } else if (!strcmp(featurestr, "model")) { > char *err; > numvalue =3D strtoul(val, &err, 0); > - if (!*val || *err || numvalue > 0xff) { > + if (!*val || *err) { > fprintf(stderr, "bad numerical value %s\n", val); > goto error; > } > - x86_cpu_def->model =3D numvalue; > + object_property_set_int(OBJECT(cpu), numvalue, "model", > + &error); > + if (error !=3D NULL) { > + goto error; > + } > } else if (!strcmp(featurestr, "stepping")) { > char *err; > numvalue =3D strtoul(val, &err, 0); > - if (!*val || *err || numvalue > 0xf) { > + if (!*val || *err) { > fprintf(stderr, "bad numerical value %s\n", val); > goto error; > } > - x86_cpu_def->stepping =3D numvalue ; > + object_property_set_int(OBJECT(cpu), numvalue, "stepping= ", > + &error); > + if (error !=3D NULL) { > + goto error; > + } > } else if (!strcmp(featurestr, "level")) { > char *err; > numvalue =3D strtoul(val, &err, 0); > @@ -1287,7 +1518,11 @@ static int cpu_x86_parse_featurestr(x86_def_t *x86= _cpu_def, char *features) > fprintf(stderr, "bad numerical value %s\n", val); > goto error; > } > - x86_cpu_def->level =3D numvalue; > + object_property_set_int(OBJECT(cpu), numvalue, "level", > + &error); > + if (error !=3D NULL) { > + goto error; > + } > } else if (!strcmp(featurestr, "xlevel")) { > char *err; > numvalue =3D strtoul(val, &err, 0); > @@ -1298,35 +1533,36 @@ static int cpu_x86_parse_featurestr(x86_def_t *x8= 6_cpu_def, char *features) > if (numvalue < 0x80000000) { > numvalue +=3D 0x80000000; > } > - x86_cpu_def->xlevel =3D numvalue; > - } else if (!strcmp(featurestr, "vendor")) { > - if (strlen(val) !=3D 12) { > - fprintf(stderr, "vendor string must be 12 chars long= \n"); > + object_property_set_int(OBJECT(cpu), numvalue, "xlevel", > + &error); > + if (error !=3D NULL) { > goto error; > } > - x86_cpu_def->vendor1 =3D 0; > - x86_cpu_def->vendor2 =3D 0; > - x86_cpu_def->vendor3 =3D 0; > - for(i =3D 0; i < 4; i++) { > - x86_cpu_def->vendor1 |=3D ((uint8_t)val[i ]) << (= 8 * i); > - x86_cpu_def->vendor2 |=3D ((uint8_t)val[i + 4]) << (= 8 * i); > - x86_cpu_def->vendor3 |=3D ((uint8_t)val[i + 8]) << (= 8 * i); > + } else if (!strcmp(featurestr, "vendor")) { > + object_property_set_str(OBJECT(cpu), val, "vendor", &err= or); > + if (error !=3D NULL) { > + goto error; > } > - x86_cpu_def->vendor_override =3D 1; > } else if (!strcmp(featurestr, "model_id")) { > - pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model= _id), > - val); > + object_property_set_str(OBJECT(cpu), val, "model-id", &e= rror); > + if (error !=3D NULL) { > + goto error; > + } > } else if (!strcmp(featurestr, "tsc_freq")) { > int64_t tsc_freq; > char *err; > =20 > tsc_freq =3D strtosz_suffix_unit(val, &err, > STRTOSZ_DEFSUFFIX_B, 1000= ); > - if (tsc_freq < 0 || *err) { > + if (*err) { > fprintf(stderr, "bad numerical value %s\n", val); > goto error; > } > - x86_cpu_def->tsc_khz =3D tsc_freq / 1000; > + object_property_set_int(OBJECT(cpu), tsc_freq, > + "tsc-frequency", &error); > + if (error !=3D NULL) { > + goto error; > + } > } else if (!strcmp(featurestr, "hv_spinlocks")) { > char *err; > numvalue =3D strtoul(val, &err, 0); > @@ -1353,27 +1589,32 @@ static int cpu_x86_parse_featurestr(x86_def_t *x8= 6_cpu_def, char *features) > } > featurestr =3D strtok(NULL, ","); > } > - x86_cpu_def->features |=3D plus_features; > - x86_cpu_def->ext_features |=3D plus_ext_features; > - x86_cpu_def->ext2_features |=3D plus_ext2_features; > - x86_cpu_def->ext3_features |=3D plus_ext3_features; > - x86_cpu_def->kvm_features |=3D plus_kvm_features; > - x86_cpu_def->svm_features |=3D plus_svm_features; > - x86_cpu_def->cpuid_7_0_ebx_features |=3D plus_7_0_ebx_features; > - x86_cpu_def->features &=3D ~minus_features; > - x86_cpu_def->ext_features &=3D ~minus_ext_features; > - x86_cpu_def->ext2_features &=3D ~minus_ext2_features; > - x86_cpu_def->ext3_features &=3D ~minus_ext3_features; > - x86_cpu_def->kvm_features &=3D ~minus_kvm_features; > - x86_cpu_def->svm_features &=3D ~minus_svm_features; > - x86_cpu_def->cpuid_7_0_ebx_features &=3D ~minus_7_0_ebx_features; > + env->cpuid_features |=3D plus_features; > + env->cpuid_ext_features |=3D plus_ext_features; > + env->cpuid_ext2_features |=3D plus_ext2_features; > + env->cpuid_ext3_features |=3D plus_ext3_features; > + env->cpuid_kvm_features |=3D plus_kvm_features; > + env->cpuid_svm_features |=3D plus_svm_features; > + env->cpuid_7_0_ebx_features |=3D plus_7_0_ebx_features; > + env->cpuid_features &=3D ~minus_features; > + env->cpuid_ext_features &=3D ~minus_ext_features; > + env->cpuid_ext2_features &=3D ~minus_ext2_features; > + env->cpuid_ext3_features &=3D ~minus_ext3_features; > + env->cpuid_kvm_features &=3D ~minus_kvm_features; > + env->cpuid_svm_features &=3D ~minus_svm_features; > + env->cpuid_7_0_ebx_features &=3D ~minus_7_0_ebx_features; > if (check_cpuid && kvm_enabled()) { > - if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpui= d) > + if (kvm_check_features_against_host(cpu) && enforce_cpuid) { > goto error; > + } > } > return 0; > =20 > error: > + if (error !=3D NULL) { > + fprintf(stderr, "%s\n", error_get_pretty(error)); > + error_free(error); > + } > return -1; > } > =20 > @@ -1407,23 +1648,60 @@ static void listflags(char *buf, int bufsize, uin= t32_t fbits, > } > } > =20 > +static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) > +{ > + ObjectClass *oc; > + char *typename; > + > + oc =3D object_class_by_name(cpu_model); > + if (oc !=3D NULL && object_class_dynamic_cast(oc, TYPE_X86_CPU) !=3D= NULL) { > + return oc; > + } > + > + typename =3D g_strdup_printf(TYPE("%s"), cpu_model); > + oc =3D object_class_by_name(typename); > + g_free(typename); > + if (oc !=3D NULL && object_class_dynamic_cast(oc, TYPE_X86_CPU) !=3D= NULL) { > + return oc; > + } > + > + return NULL; > +} > + > /* generate CPU information. */ > + > +typedef struct X86CPUListState { > + fprintf_function cpu_fprintf; > + FILE *file; > +} X86CPUListState; > + > +static void x86_cpu_list_entry(gpointer data, gpointer user_data) > +{ > + ObjectClass *oc =3D data; > + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); > + X86CPUListState *s =3D user_data; > + char buf[256]; > + > + snprintf(buf, MIN(sizeof(buf), strlen(object_class_get_name(oc)) > + - strlen("-" TYPE_X86_CPU) + 1), > + "%s", object_class_get_name(oc)); > + (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n", > + buf, xcc->model_id); > +} > + > void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf) > { > - int i; > + X86CPUListState s =3D { > + .file =3D f, > + .cpu_fprintf =3D cpu_fprintf, > + }; > + GSList *list; > char buf[256]; > =20 > - /* Force creation of CPU class */ > - object_class_by_name(TYPE_X86_CPU); > + list =3D object_class_get_list(TYPE_X86_CPU, false); > + g_slist_foreach(list, x86_cpu_list_entry, &s); > + g_slist_free(list); > =20 > - for (i =3D 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { > - x86_def_t *def =3D &builtin_x86_defs[i]; > - snprintf(buf, sizeof(buf), "%s", def->name); > - (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id); > - } > - if (kvm_enabled()) { > - (*cpu_fprintf)(f, "x86 %16s\n", "[host]"); > - } > (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n"); > listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1); > (*cpu_fprintf)(f, " %s\n", buf); > @@ -1435,25 +1713,38 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_f= printf) > (*cpu_fprintf)(f, " %s\n", buf); > } > =20 > -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > -{ > - CpuDefinitionInfoList *cpu_list =3D NULL; > - int i; > +typedef struct X86CPUDefsState { > + CpuDefinitionInfoList *cpu_list; > +} X86CPUDefsState; > =20 > - for (i =3D 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { > - CpuDefinitionInfoList *entry; > - CpuDefinitionInfo *info; > +static void x86_cpu_defs_entry(gpointer data, gpointer user_data) > +{ > + ObjectClass *oc =3D data; > + X86CPUDefsState *s =3D user_data; > + CpuDefinitionInfoList *entry; > + CpuDefinitionInfo *info; > + > + info =3D g_malloc0(sizeof(*info)); > + info->name =3D g_strdup(object_class_get_name(oc)); > + > + entry =3D g_malloc0(sizeof(*entry)); > + entry->value =3D info; > + entry->next =3D s->cpu_list; > + s->cpu_list =3D entry; > +} > =20 > - info =3D g_malloc0(sizeof(*info)); > - info->name =3D g_strdup(builtin_x86_defs[i].name); > +CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) > +{ > + X86CPUDefsState s =3D { > + .cpu_list =3D NULL, > + }; > + GSList *list; > =20 > - entry =3D g_malloc0(sizeof(*entry)); > - entry->value =3D info; > - entry->next =3D cpu_list; > - cpu_list =3D entry; > - } > + list =3D object_class_get_list(TYPE_X86_CPU, false); > + g_slist_foreach(list, x86_cpu_defs_entry, &s); > + g_slist_free(list); > =20 > - return cpu_list; > + return s.cpu_list; > } > =20 > #ifdef CONFIG_KVM > @@ -1482,16 +1773,16 @@ static void filter_features_for_kvm(X86CPU *cpu) > } > #endif > =20 > -int cpu_x86_register(X86CPU *cpu, const char *cpu_model) > +X86CPU *cpu_x86_init(const char *cpu_model) > { > - CPUX86State *env =3D &cpu->env; > - x86_def_t def1, *def =3D &def1; > + X86CPU *cpu =3D NULL; > + CPUX86State *env; > + ObjectClass *oc; > + X86CPUClass *xcc; > Error *error =3D NULL; > char *name, *features; > gchar **model_pieces; > =20 > - memset(def, 0, sizeof(*def)); > - > model_pieces =3D g_strsplit(cpu_model, ",", 2); > if (!model_pieces[0]) { > goto error; > @@ -1499,43 +1790,45 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu= _model) > name =3D model_pieces[0]; > features =3D model_pieces[1]; > =20 > - if (kvm_enabled() && strcmp(name, "host") =3D=3D 0) { > - kvm_cpu_fill_host(def); > - } else { > - if (cpu_x86_find_by_name(def, name) < 0) { > - goto error; > - } > + if (!kvm_enabled() && strcmp(name, "host") =3D=3D 0) { > + goto error; > } > - > - if (cpu_x86_parse_featurestr(def, features) < 0) { > + oc =3D x86_cpu_class_by_name(name); > + if (oc =3D=3D NULL) { > goto error; > } > - if (def->vendor1) { > - env->cpuid_vendor1 =3D def->vendor1; > - env->cpuid_vendor2 =3D def->vendor2; > - env->cpuid_vendor3 =3D def->vendor3; > + cpu =3D X86_CPU(object_new(object_class_get_name(oc))); > + env =3D &cpu->env; > + env->cpu_model_str =3D cpu_model; > + xcc =3D X86_CPU_GET_CLASS(cpu); > + > + if (xcc->vendor1) { > + env->cpuid_vendor1 =3D xcc->vendor1; > + env->cpuid_vendor2 =3D xcc->vendor2; > + env->cpuid_vendor3 =3D xcc->vendor3; > } else { > env->cpuid_vendor1 =3D CPUID_VENDOR_INTEL_1; > env->cpuid_vendor2 =3D CPUID_VENDOR_INTEL_2; > env->cpuid_vendor3 =3D CPUID_VENDOR_INTEL_3; > } > - env->cpuid_vendor_override =3D def->vendor_override; > - object_property_set_int(OBJECT(cpu), def->level, "level", &error); > - object_property_set_int(OBJECT(cpu), def->family, "family", &error); > - object_property_set_int(OBJECT(cpu), def->model, "model", &error); > - object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &err= or); > - env->cpuid_features =3D def->features; > - env->cpuid_ext_features =3D def->ext_features; > - env->cpuid_ext2_features =3D def->ext2_features; > - env->cpuid_ext3_features =3D def->ext3_features; > - object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error); > - env->cpuid_kvm_features =3D def->kvm_features; > - env->cpuid_svm_features =3D def->svm_features; > - env->cpuid_ext4_features =3D def->ext4_features; > - env->cpuid_7_0_ebx_features =3D def->cpuid_7_0_ebx_features; > - env->cpuid_xlevel2 =3D def->xlevel2; > - object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000, > + env->cpuid_vendor_override =3D xcc->vendor_override; > + object_property_set_int(OBJECT(cpu), xcc->level, "level", &error); > + object_property_set_int(OBJECT(cpu), xcc->family, "family", &error); > + object_property_set_int(OBJECT(cpu), xcc->model, "model", &error); > + object_property_set_int(OBJECT(cpu), xcc->stepping, "stepping", &err= or); > + env->cpuid_features =3D xcc->features; > + env->cpuid_ext_features =3D xcc->ext_features; > + env->cpuid_ext2_features =3D xcc->ext2_features; > + env->cpuid_ext3_features =3D xcc->ext3_features; > + object_property_set_int(OBJECT(cpu), xcc->xlevel, "xlevel", &error); > + env->cpuid_kvm_features =3D xcc->kvm_features; > + env->cpuid_svm_features =3D xcc->svm_features; > + env->cpuid_ext4_features =3D xcc->ext4_features; > + env->cpuid_7_0_ebx_features =3D xcc->cpuid_7_0_ebx_features; > + env->cpuid_xlevel2 =3D xcc->xlevel2; > + object_property_set_int(OBJECT(cpu), (int64_t)xcc->tsc_khz * 1000, > "tsc-frequency", &error); > + object_property_set_str(OBJECT(cpu), xcc->model_id, "model-id", &err= or); > =20 > /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on > * CPUID[1].EDX. > @@ -1544,7 +1837,11 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_= model) > env->cpuid_vendor2 =3D=3D CPUID_VENDOR_AMD_2 && > env->cpuid_vendor3 =3D=3D CPUID_VENDOR_AMD_3) { > env->cpuid_ext2_features &=3D ~CPUID_EXT2_AMD_ALIASES; > - env->cpuid_ext2_features |=3D (def->features & CPUID_EXT2_AMD_AL= IASES); > + env->cpuid_ext2_features |=3D (xcc->features & CPUID_EXT2_AMD_AL= IASES); > + } > + > + if (cpu_x86_parse_featurestr(cpu, features) < 0) { > + goto error; > } > =20 > if (!kvm_enabled()) { > @@ -1562,7 +1859,13 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_= model) > filter_features_for_kvm(cpu); > #endif > } > - object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &err= or); > + if (error) { > + fprintf(stderr, "%s\n", error_get_pretty(error)); > + error_free(error); > + goto error; > + } > + > + x86_cpu_realize(OBJECT(cpu), &error); > if (error) { > fprintf(stderr, "%s\n", error_get_pretty(error)); > error_free(error); > @@ -1570,10 +1873,13 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu= _model) > } > =20 > g_strfreev(model_pieces); > - return 0; > + return cpu; > error: > + if (cpu !=3D NULL) { > + object_delete(OBJECT(cpu)); > + } > g_strfreev(model_pieces); > - return -1; > + return NULL; > } > =20 > #if !defined(CONFIG_USER_ONLY) > @@ -1585,30 +1891,6 @@ void cpu_clear_apic_feature(CPUX86State *env) > =20 > #endif /* !CONFIG_USER_ONLY */ > =20 > -/* Initialize list of CPU models, filling some non-static fields if nece= ssary > - */ > -static void x86_cpudef_setup(void) > -{ > - int i, j; > - static const char *model_with_versions[] =3D { "qemu32", "qemu64", "= athlon" }; > - > - for (i =3D 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { > - x86_def_t *def =3D &builtin_x86_defs[i]; > - > - /* Look for specific "cpudef" models that */ > - /* have the QEMU version in .model_id */ > - for (j =3D 0; j < ARRAY_SIZE(model_with_versions); j++) { > - if (strcmp(model_with_versions[j], def->name) =3D=3D 0) { > - pstrcpy(def->model_id, sizeof(def->model_id), > - "QEMU Virtual CPU version "); > - pstrcat(def->model_id, sizeof(def->model_id), > - qemu_get_version()); > - break; > - } > - } > - } > -} > - > static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, > uint32_t *ecx, uint32_t *edx) > { > @@ -2140,8 +2422,6 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) > =20 > xcc->parent_reset =3D cc->reset; > cc->reset =3D x86_cpu_reset; > - > - x86_cpudef_setup(); > } > =20 > static const TypeInfo x86_cpu_type_info =3D { > @@ -2149,7 +2429,7 @@ static const TypeInfo x86_cpu_type_info =3D { > .parent =3D TYPE_CPU, > .instance_size =3D sizeof(X86CPU), > .instance_init =3D x86_cpu_initfn, > - .abstract =3D false, > + .abstract =3D true, > .class_size =3D sizeof(X86CPUClass), > .class_init =3D x86_cpu_common_class_init, > }; > @@ -2157,6 +2437,33 @@ static const TypeInfo x86_cpu_type_info =3D { > static void x86_cpu_register_types(void) > { > type_register_static(&x86_cpu_type_info); > + type_register_static(&qemu64_cpu_type_info); > + type_register_static(&phenom_cpu_type_info); > + type_register_static(&core2duo_cpu_type_info); > + type_register_static(&kvm64_cpu_type_info); > + type_register_static(&qemu32_cpu_type_info); > + type_register_static(&kvm32_cpu_type_info); > + type_register_static(&coreduo_cpu_type_info); > + type_register_static(&i486_cpu_type_info); > + type_register_static(&pentium_cpu_type_info); > + type_register_static(&pentium2_cpu_type_info); > + type_register_static(&pentium3_cpu_type_info); > + type_register_static(&athlon_cpu_type_info); > + type_register_static(&n270_cpu_type_info); > + type_register_static(&conroe_cpu_type_info); > + type_register_static(&penryn_cpu_type_info); > + type_register_static(&nehalem_cpu_type_info); > + type_register_static(&westmere_cpu_type_info); > + type_register_static(&sandybridge_cpu_type_info); > + type_register_static(&haswell_cpu_type_info); > + type_register_static(&opteron_g1_cpu_type_info); > + type_register_static(&opteron_g2_cpu_type_info); > + type_register_static(&opteron_g3_cpu_type_info); > + type_register_static(&opteron_g4_cpu_type_info); > + type_register_static(&opteron_g5_cpu_type_info); > +#ifdef CONFIG_KVM > + type_register_static(&kvm_host_cpu_type_info); > +#endif > } > =20 > type_init(x86_cpu_register_types) > diff --git a/target-i386/helper.c b/target-i386/helper.c > index bf206cf..47b53ed 100644 > --- a/target-i386/helper.c > +++ b/target-i386/helper.c > @@ -1240,30 +1240,6 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsi= gned int selector, > return 1; > } > =20 > -X86CPU *cpu_x86_init(const char *cpu_model) > -{ > - X86CPU *cpu; > - CPUX86State *env; > - Error *error =3D NULL; > - > - cpu =3D X86_CPU(object_new(TYPE_X86_CPU)); > - env =3D &cpu->env; > - env->cpu_model_str =3D cpu_model; > - > - if (cpu_x86_register(cpu, cpu_model) < 0) { > - object_delete(OBJECT(cpu)); > - return NULL; > - } > - > - x86_cpu_realize(OBJECT(cpu), &error); > - if (error) { > - error_free(error); > - object_delete(OBJECT(cpu)); > - return NULL; > - } > - return cpu; > -} > - > #if !defined(CONFIG_USER_ONLY) > void do_cpu_init(X86CPU *cpu) > { > --=20 > 1.7.10.4 >=20 The patch is just renaming of the current builtin_x86_defs into a bunch of functions and polluting X86CPUClass with fields from the former x86_def_t. object_new() still creates a dummy cpu instance whose defaults are still manually copied from X86CPUClass instead of x86_def_t. What's the point in having dummy sub-classes? How it can help in your CPU re-factoring? On the other hand converting features to static properties first and then converting X86CPU to sub-classes, yields already initialized to defaults sub-class completely removing notion of x86_def_t and not polluting X86CPUClass with redundant fields. For example see following patches on https://github.com/imammedo/qemu/commits/x86-cpu-classes.Jan142013 e9fd18f qdev: extend DEFINE_GENERIC_PROP() to support default values c65eca9 qdev: make qdev_prop_find_bit return non const so prop default valu= e could be modified 0311952 allow to expolit default value static props for model, family, step= ping & vendor props 8b3080e target-i386: add helpers to change default values of static propert= ies before object is created ed506d3 target-i386: prepare for subclasses to have its own instance of sta= tic properties definitions a48e252 target-i386: declare subclass for qemu64 cpu model 9c556c2 target-i386: move cpu_x86_init() & cpu_x86_register() into it and s= witch to subclasses. PS: implemended only for qemu64 f5dbfe6 CPU_CLASS_NAME(qemu64) hack 00e15b8 target-i386: properties list are per subclass: do not set them in s= uperclass to avoid defaults set by subclass be over-written --=20 Regards, Igor