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From: Paul Brook <paul@codesourcery.com>
Date: Mon, 4 Mar 2013 13:24:52 +0000
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Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: always set endian bits in
	big-endian mode
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To: Fabien Chouteau <chouteau@adacore.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, afaerber@suse.de

> On 03/01/2013 09:58 PM, Paul Brook wrote:
> >> +#ifdef TARGET_WORDS_BIGENDIAN
> >> +    if (arm_feature(env, ARM_FEATURE_V6)
> >> +        || arm_feature(env, ARM_FEATURE_V7)) {
> >> +        /* IE and EE bits stay set for big-endian */
> >> +        env->cp15.c1_sys |= (1 << 31) | (1 << 25);
> >> +    }
> >> +#endif
> > 
> > This is wrong for all the CPUs QEMU crrently supports. SCTLR.IE is
> > defined to be zero.
> 
> Again I'd like to have more information. Why is it wrong to set IE when
> we are in big-endian?

The ARM architecture defines two big-endian modes.  In BE8 mode only data 
accesses big-endian, code fetches are still little-endian.  In BE32 mode both 
code and data are big-endian.  In theory a fourth mode (big-endian code, 
little-endian data) exists, though I've never seen that used.

All the v7 cores QEMU currently supports[1] only implement BE8 mode.  The IE 
bit is reserved and most be zero.  Usermode emulation implements both, but the 
privileged cp15 registers can safely be ignored there.

Paul

[1] Except maybe the M profile cores, but they use a different system model 
anyway.