[Qemu-devel] [PATCH 0/7] pci: Create PCI Express bus type

[Qemu-devel] [PATCH 0/7] pci: Create PCI Express bus type

[Alex Williamson]

When setting PCIe capabilities we need to know the type of bus we
have.  On secondary buses we could poke around on the parent bridge
device to infer this data, but on root buses there's no parent device.
By creating a new PCIE TypeInfo we can inherit everything about PCI
buses while still allowing us to differentiate and potentially extend
in the future.

The first benefactor of this change is included here, mangling
Endpoints to Root Complex Integrated Endpoints, allowing nec-usb-xhci
to work on the root bus of q35 with Windows.  I also plan to use this
to drop link capabilities, control, and status on all Integrated
Endpoints and for PCIe capability modifications on assigned devices.
Thanks,

Alex

---

Alex Williamson (7):
      pci: Create and register a new PCI Express TypeInfo
      pci: Move PCI and PCIE type defines
      pci: Allow PCI bus creation interfaces to specify the type of bus
      pci: Q35, Root Ports, and Switches create PCI Express buses
      pci: Create pci_bus_is_express helper
      pci: Create and use API to determine root buses
      pcie: Mangle types to match topology


 hw/alpha_typhoon.c      |    2 +-
 hw/apb_pci.c            |    4 ++--
 hw/bonito.c             |    2 +-
 hw/dec_pci.c            |    7 ++++++-
 hw/grackle_pci.c        |    2 +-
 hw/gt64xxx.c            |    2 +-
 hw/i82801b11.c          |    2 +-
 hw/ioh3420.c            |    2 +-
 hw/pci/pci.c            |   36 ++++++++++++++++++++++++++----------
 hw/pci/pci.h            |   13 ++++++++++---
 hw/pci/pci_bridge.c     |    5 ++---
 hw/pci/pci_bridge.h     |    2 +-
 hw/pci/pci_bus.h        |    3 ---
 hw/pci/pcie.c           |   13 +++++++++++++
 hw/pci_bridge_dev.c     |    2 +-
 hw/piix_pci.c           |    2 +-
 hw/ppc4xx_pci.c         |    2 +-
 hw/ppce500_pci.c        |    2 +-
 hw/prep_pci.c           |    2 +-
 hw/q35.c                |    3 ++-
 hw/sh_pci.c             |    2 +-
 hw/spapr_pci.c          |    2 +-
 hw/unin_pci.c           |    4 ++--
 hw/versatile_pci.c      |    2 +-
 hw/xio3130_downstream.c |    2 +-
 hw/xio3130_upstream.c   |    2 +-
 26 files changed, 80 insertions(+), 42 deletions(-)

[Qemu-devel] [PATCH 1/7] pci: Create and register a new PCI Express TypeInfo

[Alex Williamson]

This will allow us to differentiate Express and Legacy buses.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/pci/pci.c     |    6 ++++++
 hw/pci/pci_bus.h |    1 +
 2 files changed, 7 insertions(+)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index f24c389..e74b43d 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -75,6 +75,11 @@ static const TypeInfo pci_bus_info = {
     .class_init = pci_bus_class_init,
 };
 
+static const TypeInfo pcie_bus_info = {
+    .name = TYPE_PCIE_BUS,
+    .parent = TYPE_PCI_BUS,
+};
+
 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
 static void pci_update_mappings(PCIDevice *d);
 static void pci_set_irq(void *opaque, int irq_num, int level);
@@ -2231,6 +2236,7 @@ static const TypeInfo pci_device_type_info = {
 static void pci_register_types(void)
 {
     type_register_static(&pci_bus_info);
+    type_register_static(&pcie_bus_info);
     type_register_static(&pci_device_type_info);
 }
 
diff --git a/hw/pci/pci_bus.h b/hw/pci/pci_bus.h
index aef559a..6d3155f 100644
--- a/hw/pci/pci_bus.h
+++ b/hw/pci/pci_bus.h
@@ -10,6 +10,7 @@
 
 #define TYPE_PCI_BUS "PCI"
 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
+#define TYPE_PCIE_BUS "PCIE"
 
 struct PCIBus {
     BusState qbus;

[Qemu-devel] [PATCH 2/7] pci: Move PCI and PCIE type defines

[Alex Williamson]

Move these so that we can reference them from a more common header
instead of including pci_bus.h everywhere.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/pci/pci.h     |    5 +++++
 hw/pci/pci_bus.h |    4 ----
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/pci/pci.h b/hw/pci/pci.h
index d837a65..37fb522 100644
--- a/hw/pci/pci.h
+++ b/hw/pci/pci.h
@@ -339,6 +339,11 @@ typedef enum {
 
 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
                               PCIHotplugState state);
+
+#define TYPE_PCI_BUS "PCI"
+#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
+#define TYPE_PCIE_BUS "PCIE"
+
 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
diff --git a/hw/pci/pci_bus.h b/hw/pci/pci_bus.h
index 6d3155f..6ee443c 100644
--- a/hw/pci/pci_bus.h
+++ b/hw/pci/pci_bus.h
@@ -8,10 +8,6 @@
  * use accessor functions in pci.h, pci_bridge.h
  */
 
-#define TYPE_PCI_BUS "PCI"
-#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
-#define TYPE_PCIE_BUS "PCIE"
-
 struct PCIBus {
     BusState qbus;
     PCIDMAContextFunc dma_context_fn;

[Qemu-devel] [PATCH 3/7] pci: Allow PCI bus creation interfaces to specify the type of bus

[Alex Williamson]

No change to any types.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/alpha_typhoon.c      |    2 +-
 hw/apb_pci.c            |    4 ++--
 hw/bonito.c             |    2 +-
 hw/dec_pci.c            |    7 ++++++-
 hw/grackle_pci.c        |    2 +-
 hw/gt64xxx.c            |    2 +-
 hw/i82801b11.c          |    2 +-
 hw/ioh3420.c            |    2 +-
 hw/pci/pci.c            |   12 ++++++------
 hw/pci/pci.h            |    6 +++---
 hw/pci/pci_bridge.c     |    5 ++---
 hw/pci/pci_bridge.h     |    2 +-
 hw/pci_bridge_dev.c     |    2 +-
 hw/piix_pci.c           |    2 +-
 hw/ppc4xx_pci.c         |    2 +-
 hw/ppce500_pci.c        |    2 +-
 hw/prep_pci.c           |    2 +-
 hw/q35.c                |    3 ++-
 hw/sh_pci.c             |    2 +-
 hw/spapr_pci.c          |    2 +-
 hw/unin_pci.c           |    4 ++--
 hw/versatile_pci.c      |    2 +-
 hw/xio3130_downstream.c |    2 +-
 hw/xio3130_upstream.c   |    2 +-
 24 files changed, 40 insertions(+), 35 deletions(-)

diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 95571ff..d8e7ef9 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -775,7 +775,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
 
     b = pci_register_bus(dev, "pci",
                          typhoon_set_irq, sys_map_irq, s,
-                         &s->pchip.reg_mem, addr_space_io, 0, 64);
+                         &s->pchip.reg_mem, addr_space_io, 0, 64, TYPE_PCI_BUS);
     phb->bus = b;
 
     /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB.  */
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 7992d6f..754ca6c 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -329,7 +329,7 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
 {
     int rc;
 
-    rc = pci_bridge_initfn(dev);
+    rc = pci_bridge_initfn(dev, TYPE_PCI_BUS);
     if (rc < 0) {
         return rc;
     }
@@ -381,7 +381,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
                               pci_apb_set_irq, pci_pbm_map_irq, d,
                               &d->pci_mmio,
                               get_system_io(),
-                              0, 32);
+                              0, 32, TYPE_PCI_BUS);
 
     *pbm_irqs = d->pbm_irqs;
     d->ivec_irqs = ivec_irqs;
diff --git a/hw/bonito.c b/hw/bonito.c
index 3456e78..e58655a 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -707,7 +707,7 @@ static int bonito_pcihost_initfn(SysBusDevice *dev)
     phb->bus = pci_register_bus(DEVICE(dev), "pci",
                                 pci_bonito_set_irq, pci_bonito_map_irq, dev,
                                 get_system_memory(), get_system_io(),
-                                0x28, 32);
+                                0x28, 32, TYPE_PCI_BUS);
 
     return 0;
 }
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index 64a5092..6ec3d22 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -51,12 +51,17 @@ static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
     return irq_num;
 }
 
+static int dec_pci_bridge_initfn(PCIDevice *pci_dev)
+{
+    return pci_bridge_initfn(pci_dev, TYPE_PCI_BUS);
+}
+
 static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 
-    k->init = pci_bridge_initfn;
+    k->init = dec_pci_bridge_initfn;
     k->exit = pci_bridge_exitfn;
     k->vendor_id = PCI_VENDOR_ID_DEC;
     k->device_id = PCI_DEVICE_ID_DEC_21154;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 11e47d5..69344d9 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -88,7 +88,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
                                 pic,
                                 &d->pci_mmio,
                                 address_space_io,
-                                0, 4);
+                                0, 4, TYPE_PCI_BUS);
 
     pci_create_simple(phb->bus, 0, "grackle");
 
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index c73a58a..37be9c2 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1107,7 +1107,7 @@ PCIBus *gt64120_register(qemu_irq *pic)
                                 pic,
                                 get_system_memory(),
                                 get_system_io(),
-                                PCI_DEVFN(18, 0), 4);
+                                PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
     memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
 
     pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
diff --git a/hw/i82801b11.c b/hw/i82801b11.c
index 992095c..8b4a9c6 100644
--- a/hw/i82801b11.c
+++ b/hw/i82801b11.c
@@ -59,7 +59,7 @@ static int i82801b11_bridge_initfn(PCIDevice *d)
 {
     int rc;
 
-    rc = pci_bridge_initfn(d);
+    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
     if (rc < 0) {
         return rc;
     }
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 43f8554..74d84d4 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -97,7 +97,7 @@ static int ioh3420_initfn(PCIDevice *d)
     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
     int rc;
 
-    rc = pci_bridge_initfn(d);
+    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
     if (rc < 0) {
         return rc;
     }
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index e74b43d..f18d3ea 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -301,9 +301,9 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
                          MemoryRegion *address_space_io,
-                         uint8_t devfn_min)
+                         uint8_t devfn_min, const char *typename)
 {
-    qbus_create_inplace(bus, TYPE_PCI_BUS, parent, name);
+    qbus_create_inplace(bus, typename, parent, name);
     pci_bus_init(bus, parent, name, address_space_mem,
                  address_space_io, devfn_min);
 }
@@ -311,11 +311,11 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
-                    uint8_t devfn_min)
+                    uint8_t devfn_min, const char *typename)
 {
     PCIBus *bus;
 
-    bus = PCI_BUS(qbus_create(TYPE_PCI_BUS, parent, name));
+    bus = PCI_BUS(qbus_create(typename, parent, name));
     pci_bus_init(bus, parent, name, address_space_mem,
                  address_space_io, devfn_min);
     return bus;
@@ -343,12 +343,12 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                          void *irq_opaque,
                          MemoryRegion *address_space_mem,
                          MemoryRegion *address_space_io,
-                         uint8_t devfn_min, int nirq)
+                         uint8_t devfn_min, int nirq, const char *typename)
 {
     PCIBus *bus;
 
     bus = pci_bus_new(parent, name, address_space_mem,
-                      address_space_io, devfn_min);
+                      address_space_io, devfn_min, typename);
     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
     return bus;
 }
diff --git a/hw/pci/pci.h b/hw/pci/pci.h
index 37fb522..10aeaf0 100644
--- a/hw/pci/pci.h
+++ b/hw/pci/pci.h
@@ -348,11 +348,11 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
                          MemoryRegion *address_space_io,
-                         uint8_t devfn_min);
+                         uint8_t devfn_min, const char *typename);
 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
-                    uint8_t devfn_min);
+                    uint8_t devfn_min, const char *typename);
 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                   void *irq_opaque, int nirq);
 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
@@ -364,7 +364,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                          void *irq_opaque,
                          MemoryRegion *address_space_mem,
                          MemoryRegion *address_space_io,
-                         uint8_t devfn_min, int nirq);
+                         uint8_t devfn_min, int nirq, const char *typename);
 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 5d27fa2..6d1ffc0 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -328,7 +328,7 @@ void pci_bridge_reset(DeviceState *qdev)
 }
 
 /* default qdev initialization function for PCI-to-PCI bridge */
-int pci_bridge_initfn(PCIDevice *dev)
+int pci_bridge_initfn(PCIDevice *dev, const char *typename)
 {
     PCIBus *parent = dev->bus;
     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
@@ -364,8 +364,7 @@ int pci_bridge_initfn(PCIDevice *dev)
 	    br->bus_name = dev->qdev.id;
     }
 
-    qbus_create_inplace(&sec_bus->qbus, TYPE_PCI_BUS, &dev->qdev,
-                        br->bus_name);
+    qbus_create_inplace(&sec_bus->qbus, typename, &dev->qdev, br->bus_name);
     sec_bus->parent_dev = dev;
     sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
     sec_bus->address_space_mem = &br->address_space_mem;
diff --git a/hw/pci/pci_bridge.h b/hw/pci/pci_bridge.h
index 9d25c1b..3cf6565 100644
--- a/hw/pci/pci_bridge.h
+++ b/hw/pci/pci_bridge.h
@@ -43,7 +43,7 @@ void pci_bridge_disable_base_limit(PCIDevice *dev);
 void pci_bridge_reset_reg(PCIDevice *dev);
 void pci_bridge_reset(DeviceState *qdev);
 
-int pci_bridge_initfn(PCIDevice *pci_dev);
+int pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
 void pci_bridge_exitfn(PCIDevice *pci_dev);
 
 
diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c
index 840ef43..971b432 100644
--- a/hw/pci_bridge_dev.c
+++ b/hw/pci_bridge_dev.c
@@ -42,7 +42,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
     PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
     int err;
 
-    err = pci_bridge_initfn(dev);
+    err = pci_bridge_initfn(dev, TYPE_PCI_BUS);
     if (err) {
         goto bridge_error;
     }
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index e10bc1c..ce39779 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -245,7 +245,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
     dev = qdev_create(NULL, "i440FX-pcihost");
     s = PCI_HOST_BRIDGE(dev);
     b = pci_bus_new(dev, NULL, pci_address_space,
-                    address_space_io, 0);
+                    address_space_io, 0, TYPE_PCI_BUS);
     s->bus = b;
     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
     qdev_init_nofail(dev);
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index f3bbe88..854e170 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -349,7 +349,7 @@ static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
 
     b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
                          ppc4xx_pci_map_irq, s->irq, get_system_memory(),
-                         get_system_io(), 0, 4);
+                         get_system_io(), 0, 4, TYPE_PCI_BUS);
     h->bus = b;
 
     pci_create_simple(b, 0, "ppc4xx-host-bridge");
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 310ae1c..abc7ebe 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -356,7 +356,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
 
     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
                          mpc85xx_pci_map_irq, s->irq, address_space_mem,
-                         &s->pio, PCI_DEVFN(s->first_slot, 0), 4);
+                         &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
     h->bus = b;
 
     pci_create_simple(b, 0, "e500-host-bridge");
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index d21e876..58df245 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -154,7 +154,7 @@ static void raven_pcihost_initfn(Object *obj)
     DeviceState *pci_dev;
 
     pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), NULL,
-                        address_space_mem, address_space_io, 0);
+                        address_space_mem, address_space_io, 0, TYPE_PCI_BUS);
     h->bus = &s->pci_bus;
 
     object_initialize(&s->pci_dev, TYPE_RAVEN_PCI_DEVICE);
diff --git a/hw/q35.c b/hw/q35.c
index 0a25b8b..37592bc 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -54,7 +54,8 @@ static int q35_host_init(SysBusDevice *dev)
         return -1;
     }
     b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
-                    s->mch.pci_address_space, s->mch.address_space_io, 0);
+                    s->mch.pci_address_space, s->mch.address_space_io,
+                    0, TYPE_PCI_BUS);
     s->host.pci.bus = b;
     qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
     qdev_init_nofail(DEVICE(&s->mch));
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index 96535db..e3e7550 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -124,7 +124,7 @@ static int sh_pci_device_init(SysBusDevice *dev)
                               s->irq,
                               get_system_memory(),
                               get_system_io(),
-                              PCI_DEVFN(0, 0), 4);
+                              PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
     memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s,
                           "sh_pci", 0x224);
     memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_p4,
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 36adbc5..20b9015 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -624,7 +624,7 @@ static int spapr_phb_init(SysBusDevice *s)
     bus = pci_register_bus(DEVICE(s), sphb->busname,
                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
                            &sphb->memspace, &sphb->iospace,
-                           PCI_DEVFN(0, 0), PCI_NUM_PINS);
+                           PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
     phb->bus = bus;
 
     sphb->dma_window_start = 0;
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index cb95ad1..fff235d 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -239,7 +239,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic,
                               pic,
                               &d->pci_mmio,
                               address_space_io,
-                              PCI_DEVFN(11, 0), 4);
+                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 
 #if 0
     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
@@ -305,7 +305,7 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                               pic,
                               &d->pci_mmio,
                               address_space_io,
-                              PCI_DEVFN(11, 0), 4);
+                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 
     sysbus_mmio_map(s, 0, 0xf0800000);
     sysbus_mmio_map(s, 1, 0xf0c00000);
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 0b97a40..d67ca79 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -70,7 +70,7 @@ static int pci_vpb_init(SysBusDevice *dev)
     bus = pci_register_bus(&dev->qdev, "pci",
                            pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
                            get_system_memory(), get_system_io(),
-                           PCI_DEVFN(11, 0), 4);
+                           PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 
     /* ??? Register memory space.  */
 
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index 4bccd0d..a76d89b 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -61,7 +61,7 @@ static int xio3130_downstream_initfn(PCIDevice *d)
     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
     int rc;
 
-    rc = pci_bridge_initfn(d);
+    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
     if (rc < 0) {
         return rc;
     }
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index 82556aa..d8fd19e 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -57,7 +57,7 @@ static int xio3130_upstream_initfn(PCIDevice *d)
     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
     int rc;
 
-    rc = pci_bridge_initfn(d);
+    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
     if (rc < 0) {
         return rc;
     }

[Qemu-devel] [PATCH 4/7] pci: Q35, Root Ports, and Switches create PCI Express buses

[Alex Williamson]

Convert q35, ioh3420, xio3130_upstream, and xio3130_downstream to
use the new TYPE_PCIE_BUS.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/ioh3420.c            |    2 +-
 hw/q35.c                |    2 +-
 hw/xio3130_downstream.c |    2 +-
 hw/xio3130_upstream.c   |    2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 74d84d4..5cff61e 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -97,7 +97,7 @@ static int ioh3420_initfn(PCIDevice *d)
     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
     int rc;
 
-    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
+    rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
     if (rc < 0) {
         return rc;
     }
diff --git a/hw/q35.c b/hw/q35.c
index 37592bc..6ea081a 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -55,7 +55,7 @@ static int q35_host_init(SysBusDevice *dev)
     }
     b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
                     s->mch.pci_address_space, s->mch.address_space_io,
-                    0, TYPE_PCI_BUS);
+                    0, TYPE_PCIE_BUS);
     s->host.pci.bus = b;
     qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
     qdev_init_nofail(DEVICE(&s->mch));
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index a76d89b..b868f56 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -61,7 +61,7 @@ static int xio3130_downstream_initfn(PCIDevice *d)
     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
     int rc;
 
-    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
+    rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
     if (rc < 0) {
         return rc;
     }
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index d8fd19e..cd5d97d 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -57,7 +57,7 @@ static int xio3130_upstream_initfn(PCIDevice *d)
     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
     int rc;
 
-    rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
+    rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
     if (rc < 0) {
         return rc;
     }

[Qemu-devel] [PATCH 5/7] pci: Create pci_bus_is_express helper

[Alex Williamson]

For testing the bus type.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/pci/pci.c |    5 +++++
 hw/pci/pci.h |    1 +
 2 files changed, 6 insertions(+)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index f18d3ea..9c394ab 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -297,6 +297,11 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 }
 
+bool pci_bus_is_express(PCIBus *bus)
+{
+    return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
+}
+
 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
diff --git a/hw/pci/pci.h b/hw/pci/pci.h
index 10aeaf0..d715e6f 100644
--- a/hw/pci/pci.h
+++ b/hw/pci/pci.h
@@ -344,6 +344,7 @@ typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 #define TYPE_PCIE_BUS "PCIE"
 
+bool pci_bus_is_express(PCIBus *bus);
 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,

[Qemu-devel] [PATCH 6/7] pci: Create and use API to determine root buses

[Alex Williamson]

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/pci/pci.c |   13 +++++++++----
 hw/pci/pci.h |    1 +
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 9c394ab..a023d9c 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -302,6 +302,11 @@ bool pci_bus_is_express(PCIBus *bus)
     return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
 }
 
+bool pci_bus_is_root(PCIBus *bus)
+{
+    return !bus->parent_dev;
+}
+
 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
@@ -360,7 +365,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 
 int pci_bus_num(PCIBus *s)
 {
-    if (!s->parent_dev)
+    if (pci_bus_is_root(s))
         return 0;       /* pci host bridge */
     return s->parent_dev->config[PCI_SECONDARY_BUS];
 }
@@ -1186,7 +1191,7 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
 /* Special hooks used by device assignment */
 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
 {
-    assert(!bus->parent_dev);
+    assert(pci_bus_is_root(bus));
     bus->route_intx_to_irq = route_intx_to_irq;
 }
 
@@ -1651,7 +1656,7 @@ static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
     }
 
     /* Consider all bus numbers in range for the host pci bridge. */
-    if (bus->parent_dev &&
+    if (!pci_bus_is_root(bus) &&
         !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
         return NULL;
     }
@@ -1659,7 +1664,7 @@ static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
     /* try child bus */
     for (; bus; bus = sec) {
         QLIST_FOREACH(sec, &bus->child, sibling) {
-            assert(sec->parent_dev);
+            assert(!pci_bus_is_root(sec));
             if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
                 return sec;
             }
diff --git a/hw/pci/pci.h b/hw/pci/pci.h
index d715e6f..774369c 100644
--- a/hw/pci/pci.h
+++ b/hw/pci/pci.h
@@ -345,6 +345,7 @@ typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 #define TYPE_PCIE_BUS "PCIE"
 
 bool pci_bus_is_express(PCIBus *bus);
+bool pci_bus_is_root(PCIBus *bus);
 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,

[Qemu-devel] [PATCH 7/7] pcie: Mangle types to match topology

[Alex Williamson]

Windows will fail to start drivers for devices with an Endpoint type
PCIe capability attached to a Root Complex (code 10 - Device cannot
start).  The proper type for such a device is Root Complex Integrated
Endpoint.  Devices don't care which they are, so do this conversion
automatically.

This allows the Windows driver to load for nec-usb-xhci when attached
to pcie.0 of a q35 machine.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/pci/pcie.c |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 485c94c..bcfbae4 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -48,6 +48,19 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
 
     assert(pci_is_express(dev));
 
+    /*
+     * Mangle type to convert Endpoints to Root Complex Integrated Endpoints.
+     * Windows will report Code 10 (device cannot start) for regular Endpoints
+     * on the Root Complex.
+     */
+    if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
+        switch (type) {
+        case PCI_EXP_TYPE_ENDPOINT:
+            type = PCI_EXP_TYPE_RC_END;
+            break;
+        }
+    }
+
     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
                                  PCI_EXP_VER2_SIZEOF);
     if (pos < 0) {

Re: [Qemu-devel] [PATCH 7/7] pcie: Mangle types to match topology

[Michael S. Tsirkin]

On Thu, Mar 14, 2013 at 04:01:35PM -0600, Alex Williamson wrote:
> Windows will fail to start drivers for devices with an Endpoint type
> PCIe capability attached to a Root Complex (code 10 - Device cannot
> start).  The proper type for such a device is Root Complex Integrated
> Endpoint.  Devices don't care which they are, so do this conversion
> automatically.
> 
> This allows the Windows driver to load for nec-usb-xhci when attached
> to pcie.0 of a q35 machine.
> 
> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>

I think it's a bit ugly from the API perspective,
in that an integrated endpoint is not converted to a regular one.

I think it would be cleaner to have pcie_cap_init do exactly
what it's told to do, maybe failing if you give it an
incorrect configuration. On top of this add
pcie_endpoint_cap_init which sets the type explicitly.
Hmm?

Not critical, so applied as is for now.

> ---
>  hw/pci/pcie.c |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> index 485c94c..bcfbae4 100644
> --- a/hw/pci/pcie.c
> +++ b/hw/pci/pcie.c
> @@ -48,6 +48,19 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
>  
>      assert(pci_is_express(dev));
>  
> +    /*
> +     * Mangle type to convert Endpoints to Root Complex Integrated Endpoints.
> +     * Windows will report Code 10 (device cannot start) for regular Endpoints
> +     * on the Root Complex.
> +     */
> +    if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
> +        switch (type) {
> +        case PCI_EXP_TYPE_ENDPOINT:
> +            type = PCI_EXP_TYPE_RC_END;
> +            break;
> +        }
> +    }
> +
>      pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
>                                   PCI_EXP_VER2_SIZEOF);
>      if (pos < 0) {

Re: [Qemu-devel] [PATCH 7/7] pcie: Mangle types to match topology

[Alex Williamson]

On Sun, 2013-03-17 at 14:19 +0200, Michael S. Tsirkin wrote:
> On Thu, Mar 14, 2013 at 04:01:35PM -0600, Alex Williamson wrote:
> > Windows will fail to start drivers for devices with an Endpoint type
> > PCIe capability attached to a Root Complex (code 10 - Device cannot
> > start).  The proper type for such a device is Root Complex Integrated
> > Endpoint.  Devices don't care which they are, so do this conversion
> > automatically.
> > 
> > This allows the Windows driver to load for nec-usb-xhci when attached
> > to pcie.0 of a q35 machine.
> > 
> > Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
> 
> I think it's a bit ugly from the API perspective,
> in that an integrated endpoint is not converted to a regular one.
> 
> I think it would be cleaner to have pcie_cap_init do exactly
> what it's told to do, maybe failing if you give it an
> incorrect configuration. On top of this add
> pcie_endpoint_cap_init which sets the type explicitly.
> Hmm?
> 
> Not critical, so applied as is for now.

Thanks!  I like the pcie_endpoint_cap_init idea, I'll make a wrapper
that adds that and selects the correct type for the bus.  Thanks,

Alex

Re: [Qemu-devel] [PATCH 0/7] pci: Create PCI Express bus type

[Michael S. Tsirkin]

On Thu, Mar 14, 2013 at 04:00:53PM -0600, Alex Williamson wrote:
> When setting PCIe capabilities we need to know the type of bus we
> have.  On secondary buses we could poke around on the parent bridge
> device to infer this data, but on root buses there's no parent device.
> By creating a new PCIE TypeInfo we can inherit everything about PCI
> buses while still allowing us to differentiate and potentially extend
> in the future.
> 
> The first benefactor of this change is included here, mangling
> Endpoints to Root Complex Integrated Endpoints, allowing nec-usb-xhci
> to work on the root bus of q35 with Windows.  I also plan to use this
> to drop link capabilities, control, and status on all Integrated
> Endpoints and for PCIe capability modifications on assigned devices.
> Thanks,
> 
> Alex

Applied, thanks!

> ---
> 
> Alex Williamson (7):
>       pci: Create and register a new PCI Express TypeInfo
>       pci: Move PCI and PCIE type defines
>       pci: Allow PCI bus creation interfaces to specify the type of bus
>       pci: Q35, Root Ports, and Switches create PCI Express buses
>       pci: Create pci_bus_is_express helper
>       pci: Create and use API to determine root buses
>       pcie: Mangle types to match topology
> 
> 
>  hw/alpha_typhoon.c      |    2 +-
>  hw/apb_pci.c            |    4 ++--
>  hw/bonito.c             |    2 +-
>  hw/dec_pci.c            |    7 ++++++-
>  hw/grackle_pci.c        |    2 +-
>  hw/gt64xxx.c            |    2 +-
>  hw/i82801b11.c          |    2 +-
>  hw/ioh3420.c            |    2 +-
>  hw/pci/pci.c            |   36 ++++++++++++++++++++++++++----------
>  hw/pci/pci.h            |   13 ++++++++++---
>  hw/pci/pci_bridge.c     |    5 ++---
>  hw/pci/pci_bridge.h     |    2 +-
>  hw/pci/pci_bus.h        |    3 ---
>  hw/pci/pcie.c           |   13 +++++++++++++
>  hw/pci_bridge_dev.c     |    2 +-
>  hw/piix_pci.c           |    2 +-
>  hw/ppc4xx_pci.c         |    2 +-
>  hw/ppce500_pci.c        |    2 +-
>  hw/prep_pci.c           |    2 +-
>  hw/q35.c                |    3 ++-
>  hw/sh_pci.c             |    2 +-
>  hw/spapr_pci.c          |    2 +-
>  hw/unin_pci.c           |    4 ++--
>  hw/versatile_pci.c      |    2 +-
>  hw/xio3130_downstream.c |    2 +-
>  hw/xio3130_upstream.c   |    2 +-
>  26 files changed, 80 insertions(+), 42 deletions(-)