From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UHkun-0008Tw-P2 for qemu-devel@nongnu.org; Mon, 18 Mar 2013 21:00:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UHkui-0008S7-DO for qemu-devel@nongnu.org; Mon, 18 Mar 2013 21:00:33 -0400 Date: Tue, 19 Mar 2013 12:00:24 +1100 From: David Gibson Message-ID: <20130319010024.GO9402@truffula.fritz.box> References: <1363226008-26639-1-git-send-email-david@gibson.dropbear.id.au> <1363226008-26639-4-git-send-email-david@gibson.dropbear.id.au> <5146F24D.7090003@suse.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="ugCSa1rMkiCAmd9S" Content-Disposition: inline In-Reply-To: <5146F24D.7090003@suse.de> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 3/5] pseries: Fixes and enhancements to L1 cache properties List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?iso-8859-1?Q?F=E4rber?= Cc: "qemu-ppc@nongnu.org" , Alexander Graf , qemu-devel qemu-devel --ugCSa1rMkiCAmd9S Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Mar 18, 2013 at 11:54:05AM +0100, Andreas F=E4rber wrote: > Am 15.03.2013 13:27, schrieb Alexander Graf: > >=20 > > On 14.03.2013, at 02:53, David Gibson wrote: > >=20 > >> PAPR requires that the device tree's CPU nodes have several properties > >> with information about the L1 cache. We already create two of these > >> properties, but with incorrect names - "[id]cache-block-size" instead > >> of "[id]-cache-block-size" (note the extra hyphen). > >> > >> We were also missing some of the required cache properties. This > >> patch adds the [id]-cache-line-size properties (which have the same > >> values as the block size properties in all current cases). We also > >> add the [id]-cache-size properties. > >> > >> Adding the cache sizes requires some extra infrastructure in the > >> general target-ppc code to (optionally) set the cache sizes for > >> various CPUs. The CPU family descriptions in translate_init.c can set > >> these sizes - this patch adds correct information for POWER7, I'm > >> leaving other CPU types to people who have a physical example to > >> verify against. In addition, for -cpu host we take the values > >> advertised by the host (if available) and use those to override the > >> information based on PVR. > >> > >> Signed-off-by: David Gibson > >> --- > >> hw/ppc/spapr.c | 20 ++++++++++++++++++-- > >> target-ppc/cpu.h | 1 + > >> target-ppc/kvm.c | 39 +++++++++++++++++++++++++++++++++++= ++++ > >> target-ppc/translate_init.c | 4 ++++ > >> 4 files changed, 62 insertions(+), 2 deletions(-) > >> > >> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > >> index 9a13697..7293082 100644 > >> --- a/hw/ppc/spapr.c > >> +++ b/hw/ppc/spapr.c > >> @@ -333,10 +333,26 @@ static void *spapr_create_fdt_skel(const char *c= pu_model, > >> _FDT((fdt_property_string(fdt, "device_type", "cpu"))); > >> > >> _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])= )); > >> - _FDT((fdt_property_cell(fdt, "dcache-block-size", > >> + _FDT((fdt_property_cell(fdt, "d-cache-block-size", > >> env->dcache_line_size))); > >> - _FDT((fdt_property_cell(fdt, "icache-block-size", > >> + _FDT((fdt_property_cell(fdt, "d-cache-line-size", > >> + env->dcache_line_size))); > >> + _FDT((fdt_property_cell(fdt, "i-cache-block-size", > >> + env->icache_line_size))); > >> + _FDT((fdt_property_cell(fdt, "i-cache-line-size", > >> env->icache_line_size))); > >> + > >> + if (env->l1_dcache_size) { > >> + _FDT((fdt_property_cell(fdt, "d-cache-size", env->l1_dcac= he_size))); > >> + } else { > >> + fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\= n"); > >> + } > >> + if (env->l1_icache_size) { > >> + _FDT((fdt_property_cell(fdt, "i-cache-size", env->l1_icac= he_size))); > >> + } else { > >> + fprintf(stderr, "Warning: Unknown L1 icache size for cpu\= n"); > >> + } > >=20 > > The L1 sizes should come from the class, not env, right? Andreas, any i= deas on this? >=20 > Generally speaking, >=20 > CPUPPCState: Only if this is used for TCG with an offset from AREG0 (or > for legacy grouping reasons). >=20 > PowerPCCPU: If you ever intend to let the user override this value > (per-instance) from the command line. >=20 > PowerPCCPUClass: If the value is always constant at runtime. >=20 > I can't tell from a brief look at this patch which may be the case here. Ok, on that rationale I'll rework to move it to the class. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --ugCSa1rMkiCAmd9S Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEARECAAYFAlFHuKgACgkQaILKxv3ab8beIgCeL8ab9dhMKtX8t9y1XRFlaPeM ibIAniCu9PVeCiFjIfHOGXGTd+2qXW4m =pJw5 -----END PGP SIGNATURE----- --ugCSa1rMkiCAmd9S--