[Qemu-devel] [PULL 00/58] ppc patch queue 2013-03-22

[Qemu-devel] [PULL 00/58] ppc patch queue 2013-03-22

[Alexander Graf]

Hi Blue / Aurelien,

This is my current patch queue for ppc.  Please pull.

Alex


The following changes since commit afed26082219b49443193b4ac32d113bbcf967fd:
  Edgar E. Iglesias (1):
        microblaze: Ignore non-cpu accesses to unmapped areas

are available in the git repository at:

  git://github.com/agraf/qemu.git ppc-for-upstream

David Gibson (52):
      pseries: Fix breakage in CPU QOM conversion
      pseries: Remove "busname" property for PCI host bridge
      target-ppc: Remove CONFIG_PSERIES dependency in kvm.c
      pseries: Move XICS initialization before cpu initialization
      target-ppc: Remove vestigial PowerPC 620 support
      target-ppc: Trivial cleanups in mmu_helper.c
      target-ppc: Remove address check for logging
      target-ppc: Move SLB handling into a mmu-hash64.c
      target-ppc: Disentangle pte_check()
      target-ppc: Disentangle find_pte()
      target-ppc: Disentangle get_segment()
      target-ppc: Rework get_physical_address()
      target-ppc: Disentangle get_physical_address() paths
      target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault
      target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug()
      target-ppc: Disentangle hash mmu helper functions
      target-ppc: Don't share get_pteg_offset() between 32 and 64-bit
      target-ppc: Disentangle BAT code for 32-bit hash MMUs
      target-ppc: mmu_ctx_t should not be a global type
      mmu-hash*: Add header file for definitions
      mmu-hash*: Add hash pte load/store helpers
      mmu-hash*: Reduce use of access_type
      mmu-hash64: Remove nx from mmu_ctx_hash64
      mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64}
      mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}()
      mmu-hash32: Split out handling of direct store segments
      mmu-hash32: Split direct store segment handling into a helper
      mmu-hash*: Cleanup segment-level NX check
      mmu-hash*: Don't keep looking for PTEs after we find a match
      mmu-hash*: Separate PTEG searching from permissions checking
      mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes
      mmu-hash*: Remove permission checking from find_pte{32, 64}()
      mmu-hash64: Clean up ppc_hash64_htab_lookup()
      mmu-hash*: Fold pte_check*() logic into caller
      mmu-hash32: Remove odd pointer usage from BAT code
      mmu-hash32: Split BAT size logic from permissions logic
      mmu-hash32: Clean up BAT matching logic
      mmu-hash32: Cleanup BAT lookup
      mmu-hash32: Don't look up page tables on BAT permission error
      mmu-hash*: Don't update PTE flags when permission is denied
      mmu-hash32: Remove nx from context structure
      mmu-hash*: Clean up permission checking
      mmu-hash64: Factor SLB N bit into permissions bits
      mmu-hash*: Clean up PTE flags update
      mmu-hash*: Clean up real address calculation
      mmu-hash*: Correctly mask RPN from hash PTE
      mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()
      mmu-hash*: Merge translate and fault handling functions
      mmu-hash64: Implement Virtual Page Class Key Protection
      target-ppc: Split user only code out of mmu_helper.c
      target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
      target-ppc: Use QOM method dispatch for MMU fault handling

Fabien Chouteau (1):
      PPC/GDB: handle read and write of fpscr

Richard Henderson (5):
      target-ppc: Fix add and subf carry generation in narrow mode
      target-ppc: Use NARROW_MODE macro for branches
      target-ppc: Use NARROW_MODE macro for comparisons
      target-ppc: Use NARROW_MODE macro for addresses
      target-ppc: Use NARROW_MODE macro for tlbie

 gdbstub.c                     |    3 +-
 hw/ppc/spapr.c                |   16 +-
 hw/ppc/spapr_hcall.c          |  102 ++----
 hw/ppc/xics.c                 |   57 ++--
 hw/spapr_pci.c                |   30 ++-
 hw/spapr_pci.h                |    4 +-
 hw/xics.h                     |    3 +-
 monitor.c                     |    4 -
 target-ppc/Makefile.objs      |    7 +-
 target-ppc/cpu-models.c       |    2 +-
 target-ppc/cpu-qom.h          |    4 +
 target-ppc/cpu.h              |   91 +----
 target-ppc/fpu_helper.c       |    5 +
 target-ppc/helper.h           |    1 -
 target-ppc/kvm.c              |    3 +-
 target-ppc/machine.c          |    4 +-
 target-ppc/mem_helper.c       |   38 --
 target-ppc/misc_helper.c      |    6 -
 target-ppc/mmu-hash32.c       |  560 +++++++++++++++++++++++++++
 target-ppc/mmu-hash32.h       |  102 +++++
 target-ppc/mmu-hash64.c       |  546 +++++++++++++++++++++++++++
 target-ppc/mmu-hash64.h       |  124 ++++++
 target-ppc/mmu_helper.c       |  835 ++++++++---------------------------------
 target-ppc/translate.c        |  226 ++++++------
 target-ppc/translate_init.c   |  360 +++++-------------
 target-ppc/user_only_helper.c |   44 +++
 26 files changed, 1873 insertions(+), 1304 deletions(-)
 create mode 100644 target-ppc/mmu-hash32.c
 create mode 100644 target-ppc/mmu-hash32.h
 create mode 100644 target-ppc/mmu-hash64.c
 create mode 100644 target-ppc/mmu-hash64.h
 create mode 100644 target-ppc/user_only_helper.c

[Qemu-devel] [PATCH 01/58] pseries: Fix breakage in CPU QOM conversion

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

Commit 259186a7d2f7184efc96ae99bc5658e6159f53ad "cpu: Move halted and
interrupt_request fields to CPUState" broke the pseries machine.  That's
because it uses CPU() instead of ENV_GET_CPU() to convert from the global
first_cpu pointer (still a CPUArchState) to a CPUState.  This patch fixes
the breakage.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/spapr.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f355a9b..d45098d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -629,7 +629,7 @@ static void ppc_spapr_reset(void)
                        spapr->rtas_size);
 
     /* Set up the entry state */
-    first_cpu_cpu = CPU(first_cpu);
+    first_cpu_cpu = ENV_GET_CPU(first_cpu);
     first_cpu->gpr[3] = spapr->fdt_addr;
     first_cpu->gpr[5] = 0;
     first_cpu_cpu->halted = 0;
-- 
1.6.0.2

[Qemu-devel] [PATCH 02/58] pseries: Remove "busname" property for PCI host bridge

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

Currently the "spapr-pci-host-bridge" device has a "busname" property which
can be used to override the default assignment of qbus names for the bus
subordinate to the PHB.  We use that for the default primary PCI bus, to
make libvirt happy, which expects there to be a bus named simply "pci".
The default qdev core logic would name the bus "pci.0", and the pseries
code would otherwise name it "pci@800000020000000" which is the name it
is given in the device tree based on its BUID.

The "busname" property is rather clunky though, so this patch simplifies
things by just using a special case hack for the default PHB, setting
busname to "pci" when index=0.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/spapr.c |    2 +-
 hw/spapr_pci.c |   30 ++++++++++++++++++++++--------
 hw/spapr_pci.h |    4 +---
 3 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d45098d..74ae83b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -856,7 +856,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
     /* Set up PCI */
     spapr_pci_rtas_init();
 
-    phb = spapr_create_phb(spapr, 0, "pci");
+    phb = spapr_create_phb(spapr, 0);
 
     for (i = 0; i < nb_nics; i++) {
         NICInfo *nd = &nd_table[i];
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 36adbc5..42c8b61 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -518,6 +518,7 @@ static int spapr_phb_init(SysBusDevice *s)
 {
     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
     PCIHostState *phb = PCI_HOST_BRIDGE(s);
+    const char *busname;
     char *namebuf;
     int i;
     PCIBus *bus;
@@ -575,9 +576,6 @@ static int spapr_phb_init(SysBusDevice *s)
     }
 
     sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
-    if (!sphb->busname) {
-        sphb->busname = sphb->dtbusname;
-    }
 
     namebuf = alloca(strlen(sphb->dtbusname) + 32);
 
@@ -621,7 +619,26 @@ static int spapr_phb_init(SysBusDevice *s)
                                     &sphb->msiwindow);
     }
 
-    bus = pci_register_bus(DEVICE(s), sphb->busname,
+    /*
+     * Selecting a busname is more complex than you'd think, due to
+     * interacting constraints.  If the user has specified an id
+     * explicitly for the phb , then we want to use the qdev default
+     * of naming the bus based on the bridge device (so the user can
+     * then assign devices to it in the way they expect).  For the
+     * first / default PCI bus (index=0) we want to use just "pci"
+     * because libvirt expects there to be a bus called, simply,
+     * "pci".  Otherwise, we use the same name as in the device tree,
+     * since it's unique by construction, and makes the guest visible
+     * BUID clear.
+     */
+    if (s->qdev.id) {
+        busname = NULL;
+    } else if (sphb->index == 0) {
+        busname = "pci";
+    } else {
+        busname = sphb->dtbusname;
+    }
+    bus = pci_register_bus(DEVICE(s), busname,
                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
                            &sphb->memspace, &sphb->iospace,
                            PCI_DEVFN(0, 0), PCI_NUM_PINS);
@@ -663,7 +680,6 @@ static void spapr_phb_reset(DeviceState *qdev)
 }
 
 static Property spapr_phb_properties[] = {
-    DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
     DEFINE_PROP_INT32("index", sPAPRPHBState, index, -1),
     DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, -1),
     DEFINE_PROP_HEX32("liobn", sPAPRPHBState, dma_liobn, -1),
@@ -694,14 +710,12 @@ static const TypeInfo spapr_phb_info = {
     .class_init    = spapr_phb_class_init,
 };
 
-PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
-                               const char *busname)
+PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index)
 {
     DeviceState *dev;
 
     dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
     qdev_prop_set_uint32(dev, "index", index);
-    qdev_prop_set_string(dev, "busname", busname);
     qdev_init_nofail(dev);
 
     return PCI_HOST_BRIDGE(dev);
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index 8bb3c62..8bd8a66 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -39,7 +39,6 @@ typedef struct sPAPRPHBState {
 
     int32_t index;
     uint64_t buid;
-    char *busname;
     char *dtbusname;
 
     MemoryRegion memspace, iospace;
@@ -82,8 +81,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
     return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
 }
 
-PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
-                               const char *busname);
+PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index);
 
 int spapr_populate_pci_dt(sPAPRPHBState *phb,
                           uint32_t xics_phandle,
-- 
1.6.0.2

[Qemu-devel] [PATCH 03/58] target-ppc: Remove CONFIG_PSERIES dependency in kvm.c

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

target-ppc/kvm.c has an #ifdef on CONFIG_PSERIES, for the handling of
KVM exits due to a PAPR hypercall from the guest.  However, since commit
e4c8b28cde12d01ada8fe869567dc5717a2dfcb7 "ppc: express FDT dependency of
pSeries and e500 boards via default-configs/", this hasn't worked properly.
That patch altered the configuration setup so that although CONFIG_PSERIES
is visible from the Makefiles, it is not visible from C files.  This broke
the pseries machine when KVM is in use.

This patch makes a quick and dirty fix, by removing the CONFIG_PSERIES
dependency, replacing it with TARGET_PPC64 (since removing it entirely
leads to type mismatch errors).  Technically this breaks the build when
configured with --disable-fdt, since that disables CONFIG_PSERIES on
TARGET_PPC64.  However, it turns out the build was already broken in that
case, so this fixes pseries kvm without breaking anything extra.  I'm
looking into how to fix that build breakage, but I don't think that need
delay applying this patch.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/kvm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index e663ff0..9870d60 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1077,7 +1077,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
         dprintf("handle halt\n");
         ret = kvmppc_handle_halt(cpu);
         break;
-#ifdef CONFIG_PSERIES
+#if defined(TARGET_PPC64)
     case KVM_EXIT_PAPR_HCALL:
         dprintf("handle PAPR hypercall\n");
         run->papr_hcall.ret = spapr_hypercall(cpu,
-- 
1.6.0.2

Re: [Qemu-devel] [PULL 00/58] ppc patch queue 2013-03-22

[Aurélien Jarno]

On Fri, Mar 22, 2013 at 03:28:34PM +0100, Alexander Graf wrote:
> Hi Blue / Aurelien,
> 
> This is my current patch queue for ppc.  Please pull.
> 
> Alex
> 
> 
> The following changes since commit afed26082219b49443193b4ac32d113bbcf967fd:
>   Edgar E. Iglesias (1):
>         microblaze: Ignore non-cpu accesses to unmapped areas
> 
> are available in the git repository at:
> 
>   git://github.com/agraf/qemu.git ppc-for-upstream
> 
> David Gibson (52):
>       pseries: Fix breakage in CPU QOM conversion
>       pseries: Remove "busname" property for PCI host bridge
>       target-ppc: Remove CONFIG_PSERIES dependency in kvm.c
>       pseries: Move XICS initialization before cpu initialization
>       target-ppc: Remove vestigial PowerPC 620 support
>       target-ppc: Trivial cleanups in mmu_helper.c
>       target-ppc: Remove address check for logging
>       target-ppc: Move SLB handling into a mmu-hash64.c
>       target-ppc: Disentangle pte_check()
>       target-ppc: Disentangle find_pte()
>       target-ppc: Disentangle get_segment()
>       target-ppc: Rework get_physical_address()
>       target-ppc: Disentangle get_physical_address() paths
>       target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault
>       target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug()
>       target-ppc: Disentangle hash mmu helper functions
>       target-ppc: Don't share get_pteg_offset() between 32 and 64-bit
>       target-ppc: Disentangle BAT code for 32-bit hash MMUs
>       target-ppc: mmu_ctx_t should not be a global type
>       mmu-hash*: Add header file for definitions
>       mmu-hash*: Add hash pte load/store helpers
>       mmu-hash*: Reduce use of access_type
>       mmu-hash64: Remove nx from mmu_ctx_hash64
>       mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64}
>       mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}()
>       mmu-hash32: Split out handling of direct store segments
>       mmu-hash32: Split direct store segment handling into a helper
>       mmu-hash*: Cleanup segment-level NX check
>       mmu-hash*: Don't keep looking for PTEs after we find a match
>       mmu-hash*: Separate PTEG searching from permissions checking
>       mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes
>       mmu-hash*: Remove permission checking from find_pte{32, 64}()
>       mmu-hash64: Clean up ppc_hash64_htab_lookup()
>       mmu-hash*: Fold pte_check*() logic into caller
>       mmu-hash32: Remove odd pointer usage from BAT code
>       mmu-hash32: Split BAT size logic from permissions logic
>       mmu-hash32: Clean up BAT matching logic
>       mmu-hash32: Cleanup BAT lookup
>       mmu-hash32: Don't look up page tables on BAT permission error
>       mmu-hash*: Don't update PTE flags when permission is denied
>       mmu-hash32: Remove nx from context structure
>       mmu-hash*: Clean up permission checking
>       mmu-hash64: Factor SLB N bit into permissions bits
>       mmu-hash*: Clean up PTE flags update
>       mmu-hash*: Clean up real address calculation
>       mmu-hash*: Correctly mask RPN from hash PTE
>       mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()
>       mmu-hash*: Merge translate and fault handling functions
>       mmu-hash64: Implement Virtual Page Class Key Protection
>       target-ppc: Split user only code out of mmu_helper.c
>       target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
>       target-ppc: Use QOM method dispatch for MMU fault handling
> 
> Fabien Chouteau (1):
>       PPC/GDB: handle read and write of fpscr
> 
> Richard Henderson (5):
>       target-ppc: Fix add and subf carry generation in narrow mode
>       target-ppc: Use NARROW_MODE macro for branches
>       target-ppc: Use NARROW_MODE macro for comparisons
>       target-ppc: Use NARROW_MODE macro for addresses
>       target-ppc: Use NARROW_MODE macro for tlbie
> 
>  gdbstub.c                     |    3 +-
>  hw/ppc/spapr.c                |   16 +-
>  hw/ppc/spapr_hcall.c          |  102 ++----
>  hw/ppc/xics.c                 |   57 ++--
>  hw/spapr_pci.c                |   30 ++-
>  hw/spapr_pci.h                |    4 +-
>  hw/xics.h                     |    3 +-
>  monitor.c                     |    4 -
>  target-ppc/Makefile.objs      |    7 +-
>  target-ppc/cpu-models.c       |    2 +-
>  target-ppc/cpu-qom.h          |    4 +
>  target-ppc/cpu.h              |   91 +----
>  target-ppc/fpu_helper.c       |    5 +
>  target-ppc/helper.h           |    1 -
>  target-ppc/kvm.c              |    3 +-
>  target-ppc/machine.c          |    4 +-
>  target-ppc/mem_helper.c       |   38 --
>  target-ppc/misc_helper.c      |    6 -
>  target-ppc/mmu-hash32.c       |  560 +++++++++++++++++++++++++++
>  target-ppc/mmu-hash32.h       |  102 +++++
>  target-ppc/mmu-hash64.c       |  546 +++++++++++++++++++++++++++
>  target-ppc/mmu-hash64.h       |  124 ++++++
>  target-ppc/mmu_helper.c       |  835 ++++++++---------------------------------
>  target-ppc/translate.c        |  226 ++++++------
>  target-ppc/translate_init.c   |  360 +++++-------------
>  target-ppc/user_only_helper.c |   44 +++
>  26 files changed, 1873 insertions(+), 1304 deletions(-)
>  create mode 100644 target-ppc/mmu-hash32.c
>  create mode 100644 target-ppc/mmu-hash32.h
>  create mode 100644 target-ppc/mmu-hash64.c
>  create mode 100644 target-ppc/mmu-hash64.h
>  create mode 100644 target-ppc/user_only_helper.c
> 

Thanks, pulled.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net