[Qemu-devel] [RFC PATCH 0/8] libqos support

[Qemu-devel] [RFC PATCH 0/8] libqos support

[Anthony Liguori]

This is a not completely polished version of libqos that includes PCI
support.  I haven't gone through the patches thoroughly yet so I've got
it marked as RFC.  It works and is functionally complete.  I know the
files are missing copyrights though and the commit messages need some
work.  I also haven't run checkpatch on the patches yet.

I've included a test of the i440fx but not a virtio-blk test.  There's a
lot more infrastructure (block and virtio) needed for that.  That has been
what's been holding up this series.  But since it's become a bottleneck
for other people, I decided to split these bits off and save the virtio
bits for another day.

Note that the pam test is pretty slow because it does a tremendous number
of byte memory accesses.  On my laptop, it comes in around two seconds
which isn't that bad.

Regards,

Anthony Liguori

[Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Anthony Liguori]

This includes basic PCI support.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 configure             |   2 +-
 tests/Makefile        |   2 +-
 tests/libqos/pci-pc.c | 219 ++++++++++++++++++++++++++++++++++++++++++++++++++
 tests/libqos/pci-pc.h |   8 ++
 tests/libqos/pci.c    | 108 +++++++++++++++++++++++++
 tests/libqos/pci.h    |  65 +++++++++++++++
 6 files changed, 402 insertions(+), 2 deletions(-)
 create mode 100644 tests/libqos/pci-pc.c
 create mode 100644 tests/libqos/pci-pc.h
 create mode 100644 tests/libqos/pci.c
 create mode 100644 tests/libqos/pci.h

diff --git a/configure b/configure
index 19738ac..5d3e49e 100755
--- a/configure
+++ b/configure
@@ -4354,7 +4354,7 @@ if [ "$pixman" = "internal" ]; then
 fi
 
 # build tree in object directory in case the source is not in the current directory
-DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"
+DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos"
 DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas"
 DIRS="$DIRS roms/seabios roms/vgabios"
 DIRS="$DIRS qapi-generated"
diff --git a/tests/Makefile b/tests/Makefile
index 567e36e..cbb4188 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -89,6 +89,7 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \
 test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o
 
 $(test-obj-y): QEMU_INCLUDES += -Itests
+QEMU_CFLAGS += -I$(SRC_PATH)/tests
 
 tests/test-x86-cpuid.o: QEMU_INCLUDES += -I$(SRC_PATH)/target-i386
 
@@ -117,7 +118,6 @@ tests/test-qmp-commands.h tests/test-qmp-marshal.c :\
 $(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py
 	$(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py $(gen-out-type) -o tests -p "test-" < $<, "  GEN   $@")
 
-
 tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
 tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
 tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
diff --git a/tests/libqos/pci-pc.c b/tests/libqos/pci-pc.c
new file mode 100644
index 0000000..da80f81
--- /dev/null
+++ b/tests/libqos/pci-pc.c
@@ -0,0 +1,219 @@
+#include "libqtest.h"
+#include "libqos/pci-pc.h"
+
+#include "hw/pci/pci_regs.h"
+
+#include "qemu-common.h"
+#include "qemu/host-utils.h"
+
+#include <glib.h>
+
+typedef struct QPCIBusPC
+{
+    QPCIBus bus;
+
+    uint32_t pci_hole_start;
+    uint32_t pci_hole_size;
+    uint32_t pci_hole_alloc;
+
+    uint16_t pci_iohole_start;
+    uint16_t pci_iohole_size;
+    uint16_t pci_iohole_alloc;
+} QPCIBusPC;
+
+static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
+{
+    uintptr_t port = (uintptr_t)addr;
+    uint8_t value;
+
+    if (port < 0x10000) {
+        value = inb(port);
+    } else {
+        memread(port, &value, sizeof(value));
+    }
+
+    return value;
+}
+
+static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
+{
+    uintptr_t port = (uintptr_t)addr;
+    uint16_t value;
+
+    if (port < 0x10000) {
+        value = inw(port);
+    } else {
+        memread(port, &value, sizeof(value));
+    }
+
+    return value;
+}
+
+static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
+{
+    uintptr_t port = (uintptr_t)addr;
+    uint32_t value;
+
+    if (port < 0x10000) {
+        value = inl(port);
+    } else {
+        memread(port, &value, sizeof(value));
+    }
+
+    return value;
+}
+
+static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
+{
+    uintptr_t port = (uintptr_t)addr;
+
+    if (port < 0x10000) {
+        outb(port, value);
+    } else {
+        memwrite(port, &value, sizeof(value));
+    }
+}
+
+static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
+{
+    uintptr_t port = (uintptr_t)addr;
+
+    if (port < 0x10000) {
+        outw(port, value);
+    } else {
+        memwrite(port, &value, sizeof(value));
+    }
+}
+
+static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
+{
+    uintptr_t port = (uintptr_t)addr;
+
+    if (port < 0x10000) {
+        outl(port, value);
+    } else {
+        memwrite(port, &value, sizeof(value));
+    }
+}
+
+static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    return inb(0xcfc);
+}
+
+static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    return inw(0xcfc);
+}
+
+static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    return inl(0xcfc);
+}
+
+static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    outb(0xcfc, value);
+}
+
+static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    outw(0xcfc, value);
+}
+
+static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    outl(0xcfc, value);
+}
+
+static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
+{
+    QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
+    static const int bar_reg_map[] = {
+        PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
+        PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
+    };
+    int bar_reg;
+    uint32_t addr;
+    uint64_t size;
+
+    g_assert(barno >= 0 && barno <= 5);
+    bar_reg = bar_reg_map[barno];
+
+    qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
+    addr = qpci_config_readl(dev, bar_reg);
+
+    size = (1ULL << ctol(addr));
+    if (size == 0) {
+        return NULL;
+    }
+
+    if (addr & PCI_BASE_ADDRESS_SPACE_IO) {
+        uint16_t loc;
+
+        g_assert((s->pci_iohole_alloc + size) <= s->pci_iohole_size);
+        loc = s->pci_iohole_start + s->pci_iohole_alloc;
+        s->pci_iohole_alloc += size;
+
+        qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
+
+        return (void *)(intptr_t)loc;
+    } else {
+        uint64_t loc;
+
+        g_assert((s->pci_hole_alloc + size) <= s->pci_hole_size);
+        loc = s->pci_hole_start + s->pci_hole_alloc;
+        s->pci_hole_alloc += size;
+
+        qpci_config_writel(dev, bar_reg, loc);
+
+        return (void *)(intptr_t)loc;
+    }
+}
+
+static void qpci_pc_iounmap(QPCIBus *bus, void *data)
+{
+    /* FIXME */
+}
+
+QPCIBus *qpci_init_pc(void)
+{
+    QPCIBusPC *ret;
+
+    ret = g_malloc(sizeof(*ret));
+
+    ret->bus.io_readb = qpci_pc_io_readb;
+    ret->bus.io_readw = qpci_pc_io_readw;
+    ret->bus.io_readl = qpci_pc_io_readl;
+
+    ret->bus.io_writeb = qpci_pc_io_writeb;
+    ret->bus.io_writew = qpci_pc_io_writew;
+    ret->bus.io_writel = qpci_pc_io_writel;
+
+    ret->bus.config_readb = qpci_pc_config_readb;
+    ret->bus.config_readw = qpci_pc_config_readw;
+    ret->bus.config_readl = qpci_pc_config_readl;
+
+    ret->bus.config_writeb = qpci_pc_config_writeb;
+    ret->bus.config_writew = qpci_pc_config_writew;
+    ret->bus.config_writel = qpci_pc_config_writel;
+
+    ret->bus.iomap = qpci_pc_iomap;
+    ret->bus.iounmap = qpci_pc_iounmap;
+
+    ret->pci_hole_start = 0xE0000000;
+    ret->pci_hole_size = 0x20000000;
+    ret->pci_hole_alloc = 0;
+
+    ret->pci_iohole_start = 0xc000;
+    ret->pci_iohole_size = 0x4000;
+    ret->pci_iohole_alloc = 0;
+
+    return &ret->bus;
+}
diff --git a/tests/libqos/pci-pc.h b/tests/libqos/pci-pc.h
new file mode 100644
index 0000000..bedd5c3
--- /dev/null
+++ b/tests/libqos/pci-pc.h
@@ -0,0 +1,8 @@
+#ifndef LIBQOS_PCI_PC_H
+#define LIBQOS_PCI_PC_H
+
+#include "libqos/pci.h"
+
+QPCIBus *qpci_init_pc(void);
+
+#endif
diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
new file mode 100644
index 0000000..78d0bc0
--- /dev/null
+++ b/tests/libqos/pci.c
@@ -0,0 +1,108 @@
+#include "libqos/pci.h"
+
+#include "hw/pci/pci_regs.h"
+#include <glib.h>
+
+#include <stdio.h>
+
+QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
+{
+    QPCIDevice *dev;
+
+    dev = g_malloc0(sizeof(*dev));
+    dev->bus = bus;
+    dev->devfn = devfn;
+
+    if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
+        printf("vendor id is %x\n", qpci_config_readw(dev, PCI_VENDOR_ID));
+        g_free(dev);
+        return NULL;
+    }
+
+    return dev;
+}
+
+void qpci_device_enable(QPCIDevice *dev)
+{
+    uint16_t cmd;
+
+    /* FIXME -- does this need to be a bus callout? */
+    cmd = qpci_config_readw(dev, PCI_COMMAND);
+    cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+    qpci_config_writew(dev, PCI_COMMAND, cmd);
+}
+
+uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
+{
+    return dev->bus->config_readb(dev->bus, dev->devfn, offset);
+}
+
+uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
+{
+    return dev->bus->config_readw(dev->bus, dev->devfn, offset);
+}
+
+uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
+{
+    return dev->bus->config_readl(dev->bus, dev->devfn, offset);
+}
+
+
+void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
+{
+    dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
+}
+
+void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
+{
+    dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
+}
+
+void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
+{
+    dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
+}
+
+
+uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
+{
+    return dev->bus->io_readb(dev->bus, data);
+}
+
+uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
+{
+    return dev->bus->io_readw(dev->bus, data);
+}
+
+uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
+{
+    return dev->bus->io_readl(dev->bus, data);
+}
+
+
+void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
+{
+    dev->bus->io_writeb(dev->bus, data, value);
+}
+
+void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
+{
+    dev->bus->io_writew(dev->bus, data, value);
+}
+
+void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
+{
+    dev->bus->io_writel(dev->bus, data, value);
+}
+
+void *qpci_iomap(QPCIDevice *dev, int barno)
+{
+    return dev->bus->iomap(dev->bus, dev, barno);
+}
+
+void qpci_iounmap(QPCIDevice *dev, void *data)
+{
+    dev->bus->iounmap(dev->bus, data);
+}
+
+
diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h
new file mode 100644
index 0000000..5162a79
--- /dev/null
+++ b/tests/libqos/pci.h
@@ -0,0 +1,65 @@
+#ifndef LIBQOS_PCI_H
+#define LIBQOS_PCI_H
+
+#include <stdint.h>
+
+#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
+
+typedef struct QPCIDevice QPCIDevice;
+typedef struct QPCIBus QPCIBus;
+
+struct QPCIBus
+{
+    uint8_t (*io_readb)(QPCIBus *bus, void *addr);
+    uint16_t (*io_readw)(QPCIBus *bus, void *addr);
+    uint32_t (*io_readl)(QPCIBus *bus, void *addr);
+
+    void (*io_writeb)(QPCIBus *bus, void *addr, uint8_t value);
+    void (*io_writew)(QPCIBus *bus, void *addr, uint16_t value);
+    void (*io_writel)(QPCIBus *bus, void *addr, uint32_t value);
+
+    uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
+    uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
+    uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset);
+
+    void (*config_writeb)(QPCIBus *bus, int devfn,
+                          uint8_t offset, uint8_t value);
+    void (*config_writew)(QPCIBus *bus, int devfn,
+                          uint8_t offset, uint16_t value);
+    void (*config_writel)(QPCIBus *bus, int devfn,
+                          uint8_t offset, uint32_t value);
+
+    void *(*iomap)(QPCIBus *bus, QPCIDevice *dev, int barno);
+    void (*iounmap)(QPCIBus *bus, void *data);
+};
+
+struct QPCIDevice
+{
+    QPCIBus *bus;
+    int devfn;
+};
+
+QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
+
+void qpci_device_enable(QPCIDevice *dev);
+
+uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
+uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset);
+uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset);
+
+void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value);
+void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value);
+void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value);
+
+uint8_t qpci_io_readb(QPCIDevice *dev, void *data);
+uint16_t qpci_io_readw(QPCIDevice *dev, void *data);
+uint32_t qpci_io_readl(QPCIDevice *dev, void *data);
+
+void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value);
+void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
+void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
+
+void *qpci_iomap(QPCIDevice *dev, int barno);
+void qpci_iounmap(QPCIDevice *dev, void *data);
+
+#endif
-- 
1.8.0

[Qemu-devel] [RFC PATCH 2/8] i440fx-test: add test to compare default register values against spec

[Anthony Liguori]

We currently don't do so well...

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/Makefile      |   2 +
 tests/i440fx-test.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 138 insertions(+)
 create mode 100644 tests/i440fx-test.c

diff --git a/tests/Makefile b/tests/Makefile
index cbb4188..8eae1b4 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -66,6 +66,7 @@ gcov-files-i386-y = hw/fdc.c
 check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
 gcov-files-i386-y += hw/hd-geometry.c
 check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/i440fx-test$(EXESUF)
 check-qtest-x86_64-y = $(check-qtest-i386-y)
 gcov-files-i386-y += i386-softmmu/hw/mc146818rtc.c
 gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y))
@@ -133,6 +134,7 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
 tests/fdc-test$(EXESUF): tests/fdc-test.o
 tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
 tests/tmp105-test$(EXESUF): tests/tmp105-test.o
+tests/i440fx-test$(EXESUF): tests/i440fx-test.o tests/libqos/pci.o tests/libqos/pci-pc.o
 
 # QTest rules
 
diff --git a/tests/i440fx-test.c b/tests/i440fx-test.c
new file mode 100644
index 0000000..577730d
--- /dev/null
+++ b/tests/i440fx-test.c
@@ -0,0 +1,136 @@
+#include "libqos/pci.h"
+#include "libqos/pci-pc.h"
+#include "libqtest.h"
+
+#include "hw/pci/pci_regs.h"
+
+#include <glib.h>
+#include <stdio.h>
+
+#define BROKEN 1
+
+typedef struct TestData
+{
+    int num_cpus;
+    QPCIBus *bus;
+} TestData;
+
+static void test_i440fx_defaults(gconstpointer opaque)
+{
+    const TestData *s = opaque;
+    QPCIDevice *dev;
+    uint32_t value;
+
+    dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
+    g_assert(dev != NULL);
+
+    /* 3.2.2 */
+    g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
+    /* 3.2.3 */
+    g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
+#ifndef BROKEN
+    /* 3.2.4 */
+    g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
+    /* 3.2.5 */
+    g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
+#endif
+    /* 3.2.7 */
+    g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
+    g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
+    /* 3.2.8 */
+    g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
+    /* 3.2.9 */
+    g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
+    /* 3.2.10 */
+    g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
+
+    /* 3.2.11 */
+    value = qpci_config_readw(dev, 0x50); /* PMCCFG */
+    if (s->num_cpus == 1) { /* WPE */
+        g_assert(!(value & (1 << 15)));
+    } else {
+        g_assert((value & (1 << 15)));
+    }
+
+    g_assert(!(value & (1 << 6))); /* EPTE */
+
+    /* 3.2.12 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
+    /* 3.2.13 */
+#ifndef BROKEN
+    g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
+#endif
+    /* 3.2.14 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
+    /* 3.2.15 */
+    g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
+#ifndef BROKEN
+    /* 3.2.16 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
+    /* 3.2.17 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
+#endif
+    /* 3.2.18 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
+#ifndef BROKEN
+    /* 3.2.19 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
+#endif
+    /* 3.2.20 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
+    /* 3.2.21 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
+#ifndef BROKEN
+    /* 3.2.22 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
+#endif
+    /* 3.2.23 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
+    /* 3.2.24 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
+    /* 3.2.25 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
+    /* 3.2.26 */
+    g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
+}
+
+int main(int argc, char **argv)
+{
+    QTestState *s = NULL;
+    TestData data;
+    char *cmdline;
+    int ret;
+
+    g_test_init(&argc, &argv, NULL);
+
+    data.num_cpus = 1;
+
+    cmdline = g_strdup_printf("-display none -smp %d", data.num_cpus);
+    qtest_start(cmdline);
+    g_free(cmdline);
+
+    data.bus = qpci_init_pc();
+
+    g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
+
+    ret = g_test_run();
+
+    if (s) {
+        qtest_quit(s);
+    }
+
+    return ret;
+}
-- 
1.8.0

[Qemu-devel] [RFC PATCH 3/8] i440fx-test: add test for PAM functionality

[Anthony Liguori]

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/i440fx-test.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 138 insertions(+), 1 deletion(-)

diff --git a/tests/i440fx-test.c b/tests/i440fx-test.c
index 577730d..d406375 100644
--- a/tests/i440fx-test.c
+++ b/tests/i440fx-test.c
@@ -5,10 +5,12 @@
 #include "hw/pci/pci_regs.h"
 
 #include <glib.h>
-#include <stdio.h>
+#include <string.h>
 
 #define BROKEN 1
 
+#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
+
 typedef struct TestData
 {
     int num_cpus;
@@ -107,6 +109,139 @@ static void test_i440fx_defaults(gconstpointer opaque)
     g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 }
 
+#define PAM_RE 1
+#define PAM_WE 2
+
+static void pam_set(QPCIDevice *dev, int index, int flags)
+{
+    int regno = 0x59 + (index / 2);
+    uint8_t reg;
+
+    reg = qpci_config_readb(dev, regno);
+    if (index & 1) {
+        reg = (reg & 0x0F) | (flags << 4);
+    } else {
+        reg = (reg & 0xF0) | flags;
+    }
+    qpci_config_writeb(dev, regno, reg);
+}
+
+static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
+{
+    uint32_t size = end - start + 1;
+    gboolean ret = TRUE;
+    uint8_t *data;
+    int i;
+
+    data = g_malloc0(size);
+    memread(start, data, size);
+
+    g_test_message("verify_area: data[0] = 0x%x", data[0]);
+
+    for (i = 0; i < size; i++) {
+        if (data[i] != value) {
+            ret = FALSE;
+            break;
+        }
+    }
+
+    g_free(data);
+
+    return ret;
+}
+
+static void write_area(uint32_t start, uint32_t end, uint8_t value)
+{
+    uint32_t size = end - start + 1;
+    uint8_t *data;
+
+    data = g_malloc0(size);
+    memset(data, value, size);
+    memwrite(start, data, size);
+
+    g_free(data);
+}
+
+static void test_i440fx_pam(gconstpointer opaque)
+{
+    const TestData *s = opaque;
+    QPCIDevice *dev;
+    int i;
+    static struct {
+        uint32_t start;
+        uint32_t end;
+    } pam_area[] = {
+        { 0, 0 },             /* Reserved */
+        { 0xF0000, 0xFFFFF }, /* BIOS Area */
+        { 0xC0000, 0xC3FFF }, /* Option ROM */
+        { 0xC4000, 0xC7FFF }, /* Option ROM */
+        { 0xC8000, 0xCBFFF }, /* Option ROM */
+        { 0xCC000, 0xCFFFF }, /* Option ROM */
+        { 0xD0000, 0xD3FFF }, /* Option ROM */
+        { 0xD4000, 0xD7FFF }, /* Option ROM */
+        { 0xD8000, 0xDBFFF }, /* Option ROM */
+        { 0xDC000, 0xDFFFF }, /* Option ROM */
+        { 0xE0000, 0xE3FFF }, /* BIOS Extension */
+        { 0xE4000, 0xE7FFF }, /* BIOS Extension */
+        { 0xE8000, 0xEBFFF }, /* BIOS Extension */
+        { 0xEC000, 0xEFFFF }, /* BIOS Extension */
+    };
+
+    dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
+    g_assert(dev != NULL);
+
+    for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
+        if (pam_area[i].start == pam_area[i].end) {
+            continue;
+        }
+
+        g_test_message("Checking area 0x%05x..0x%05x",
+                       pam_area[i].start, pam_area[i].end);
+        /* Switch to RE for the area */
+        pam_set(dev, i, PAM_RE);
+        /* Verify the RAM is all zeros */
+        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
+
+        /* Switch to WE for the area */
+        pam_set(dev, i, PAM_RE | PAM_WE);
+        /* Write out a non-zero mask to the full area */
+        write_area(pam_area[i].start, pam_area[i].end, 0x42);
+
+#ifndef BROKEN
+        /* QEMU only supports a limited form of PAM */
+
+        /* Switch to !RE for the area */
+        pam_set(dev, i, PAM_WE);
+        /* Verify the area is not our mask */
+        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
+#endif
+
+        /* Verify the area is our new mask */
+        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
+
+        /* Write out a new mask */
+        write_area(pam_area[i].start, pam_area[i].end, 0x82);
+
+#ifndef BROKEN
+        /* QEMU only supports a limited form of PAM */
+
+        /* Verify the area is not our mask */
+        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
+
+        /* Switch to RE for the area */
+        pam_set(dev, i, PAM_RE | PAM_WE);
+#endif
+        /* Verify the area is our new mask */
+        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
+
+        /* Reset area */
+        pam_set(dev, i, 0);
+
+        /* Verify the area is not our new mask */
+        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
+    }
+}
+
 int main(int argc, char **argv)
 {
     QTestState *s = NULL;
@@ -125,6 +260,8 @@ int main(int argc, char **argv)
     data.bus = qpci_init_pc();
 
     g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
+    g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
+    
 
     ret = g_test_run();
 
-- 
1.8.0

[Qemu-devel] [RFC PATCH 4/8] pci: foreach

[Anthony Liguori]

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/libqos/pci.c | 32 ++++++++++++++++++++++++++++++++
 tests/libqos/pci.h |  3 +++
 2 files changed, 35 insertions(+)

diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
index 78d0bc0..57caf3a 100644
--- a/tests/libqos/pci.c
+++ b/tests/libqos/pci.c
@@ -5,6 +5,38 @@
 
 #include <stdio.h>
 
+void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
+                         void (*func)(QPCIDevice *dev, int devfn, void *data),
+                         void *data)
+{
+    int slot;
+
+    for (slot = 0; slot < 32; slot++) {
+        int fn;
+
+        for (fn = 0; fn < 8; fn++) {
+            QPCIDevice *dev;
+
+            dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
+            if (!dev) {
+                continue;
+            }
+
+            if (vendor_id != -1 &&
+                qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
+                continue;
+            }
+
+            if (device_id != -1 &&
+                qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
+                continue;
+            }
+
+            func(dev, QPCI_DEVFN(slot, fn), data);
+        }
+    }
+}
+
 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
 {
     QPCIDevice *dev;
diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h
index 5162a79..355ef40 100644
--- a/tests/libqos/pci.h
+++ b/tests/libqos/pci.h
@@ -39,6 +39,9 @@ struct QPCIDevice
     int devfn;
 };
 
+void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
+                         void (*func)(QPCIDevice *dev, int devfn, void *data),
+                         void *data);
 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
 
 void qpci_device_enable(QPCIDevice *dev);
-- 
1.8.0

[Qemu-devel] [RFC PATCH 5/8] fw_cfg: add qtest test harness

[Anthony Liguori]

While it's limited to PC support right now, the abstraction is there to support
other platforms.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/Makefile      |   7 +-
 tests/fw_cfg-test.c | 202 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 208 insertions(+), 1 deletion(-)
 create mode 100644 tests/fw_cfg-test.c

diff --git a/tests/Makefile b/tests/Makefile
index 8eae1b4..7482297 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -67,6 +67,7 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
 gcov-files-i386-y += hw/hd-geometry.c
 check-qtest-i386-y += tests/rtc-test$(EXESUF)
 check-qtest-i386-y += tests/i440fx-test$(EXESUF)
+check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
 check-qtest-x86_64-y = $(check-qtest-i386-y)
 gcov-files-i386-y += i386-softmmu/hw/mc146818rtc.c
 gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y))
@@ -129,12 +130,16 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
 
 tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
 
+libqos-obj-y = tests/libqos/pci.o
+libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
+
 tests/rtc-test$(EXESUF): tests/rtc-test.o
 tests/m48t59-test$(EXESUF): tests/m48t59-test.o
 tests/fdc-test$(EXESUF): tests/fdc-test.o
 tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
 tests/tmp105-test$(EXESUF): tests/tmp105-test.o
-tests/i440fx-test$(EXESUF): tests/i440fx-test.o tests/libqos/pci.o tests/libqos/pci-pc.o
+tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
+tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
 
 # QTest rules
 
diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c
new file mode 100644
index 0000000..b784dc8
--- /dev/null
+++ b/tests/fw_cfg-test.c
@@ -0,0 +1,202 @@
+#define NO_QEMU_PROTOS
+
+#include "libqtest.h"
+#include "hw/fw_cfg.h"
+
+#include <string.h>
+#include <glib.h>
+
+typedef struct QFWCFG QFWCFG;
+
+struct QFWCFG
+{
+    void (*select)(QFWCFG *fw_cfg, uint16_t key);
+    void (*read)(QFWCFG *fw_cfg, void *data, size_t len);
+};
+
+/* PC specific */
+
+static void pc_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
+{
+    outw(0x510, key);
+}
+
+static void pc_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
+{
+    uint8_t *ptr = data;
+    int i;
+
+    for (i = 0; i < len; i++) {
+        ptr[i] = inb(0x511);
+    }
+}
+
+static QFWCFG *pc_fw_cfg_init(void)
+{
+    QFWCFG *fw_cfg = g_malloc0(sizeof(*fw_cfg));
+
+    fw_cfg->select = pc_fw_cfg_select;
+    fw_cfg->read = pc_fw_cfg_read;
+
+    return fw_cfg;
+}
+
+/* Generic code */
+
+static void qfw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
+{
+    fw_cfg->select(fw_cfg, key);
+}
+
+static void qfw_cfg_read_data(QFWCFG *fw_cfg, void *data, size_t len)
+{
+    fw_cfg->read(fw_cfg, data, len);
+}
+
+static void qfw_cfg_get(QFWCFG *fw_cfg, uint16_t key, void *data, size_t len)
+{
+    qfw_cfg_select(fw_cfg, key);
+    qfw_cfg_read_data(fw_cfg, data, len);
+}
+
+static uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key)
+{
+    uint16_t value;
+    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+    return value;
+}
+
+static uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key)
+{
+    uint32_t value;
+    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+    return value;
+}
+
+static uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key)
+{
+    uint64_t value;
+    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+    return value;
+}
+
+static uint64_t ram_size = 128 << 20;
+static uint16_t nb_cpus = 1;
+static uint16_t max_cpus = 1;
+static uint64_t nb_nodes = 0;
+static uint16_t boot_menu = 0;
+static QFWCFG *fw_cfg = NULL;
+
+static void test_fw_cfg_signature(void)
+{
+    char buf[5];
+
+    qfw_cfg_get(fw_cfg, FW_CFG_SIGNATURE, buf, 4);
+    buf[4] = 0;
+
+    g_assert_cmpstr(buf, ==, "QEMU");
+}
+
+static void test_fw_cfg_id(void)
+{
+    g_assert_cmpint(qfw_cfg_get_u32(fw_cfg, FW_CFG_ID), ==, 1);
+}
+
+static void test_fw_cfg_uuid(void)
+{
+    uint8_t buf[16];
+    static const uint8_t uuid[16] = {
+        0x46, 0x00, 0xcb, 0x32, 0x38, 0xec, 0x4b, 0x2f,
+        0x8a, 0xcb, 0x81, 0xc6, 0xea, 0x54, 0xf2, 0xd8,
+    };
+
+    qfw_cfg_get(fw_cfg, FW_CFG_UUID, buf, 16);
+    g_assert(memcmp(buf, uuid, sizeof(buf)) == 0);
+}
+
+static void test_fw_cfg_ram_size(void)
+{
+    g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE), ==, ram_size);
+}
+
+static void test_fw_cfg_nographic(void)
+{
+    g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NOGRAPHIC), ==, 0);
+}
+
+static void test_fw_cfg_nb_cpus(void)
+{
+    g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NB_CPUS), ==, nb_cpus);
+}
+
+static void test_fw_cfg_max_cpus(void)
+{
+    g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_MAX_CPUS), ==, max_cpus);
+}
+
+static void test_fw_cfg_numa(void)
+{
+    uint64_t *cpu_mask;
+    uint64_t *node_mask;
+
+    g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_NUMA), ==, nb_nodes);
+
+    cpu_mask = g_malloc0(sizeof(uint64_t) * max_cpus);
+    node_mask = g_malloc0(sizeof(uint64_t) * nb_nodes);
+
+    qfw_cfg_read_data(fw_cfg, cpu_mask, sizeof(uint64_t) * max_cpus);
+    qfw_cfg_read_data(fw_cfg, node_mask, sizeof(uint64_t) * nb_nodes);
+
+    if (nb_nodes) {
+        g_assert(cpu_mask[0] & 0x01);
+        g_assert_cmpint(node_mask[0], ==, ram_size);
+    }
+
+    g_free(node_mask);
+    g_free(cpu_mask);
+}
+
+static void test_fw_cfg_boot_menu(void)
+{
+    g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_MENU), ==, boot_menu);
+}
+
+int main(int argc, char **argv)
+{
+    QTestState *s = NULL;
+    char *cmdline;
+    int ret;
+
+    g_test_init(&argc, &argv, NULL);
+
+    fw_cfg = pc_fw_cfg_init();
+
+    g_test_add_func("/fw_cfg/signature", test_fw_cfg_signature);
+    g_test_add_func("/fw_cfg/id", test_fw_cfg_id);
+    g_test_add_func("/fw_cfg/uuid", test_fw_cfg_uuid);
+    g_test_add_func("/fw_cfg/ram_size", test_fw_cfg_ram_size);
+    g_test_add_func("/fw_cfg/nographic", test_fw_cfg_nographic);
+    g_test_add_func("/fw_cfg/nb_cpus", test_fw_cfg_nb_cpus);
+#if 0
+    g_test_add_func("/fw_cfg/machine_id", test_fw_cfg_machine_id);
+    g_test_add_func("/fw_cfg/kernel", test_fw_cfg_kernel);
+    g_test_add_func("/fw_cfg/initrd", test_fw_cfg_initrd);
+    g_test_add_func("/fw_cfg/boot_device", test_fw_cfg_boot_device);
+#endif
+    g_test_add_func("/fw_cfg/max_cpus", test_fw_cfg_max_cpus);
+    g_test_add_func("/fw_cfg/numa", test_fw_cfg_numa);
+    g_test_add_func("/fw_cfg/boot_menu", test_fw_cfg_boot_menu);
+
+    cmdline = g_strdup_printf("-display none "
+                              "-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8 ");
+    qtest_start(cmdline);
+    g_free(cmdline);
+
+    ret = g_test_run();
+
+    if (s) {
+        qtest_quit(s);
+    }
+
+    return ret;
+}
-- 
1.8.0

[Qemu-devel] [RFC PATCH 6/8] libqos: fw_cfg

[Anthony Liguori]

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/Makefile        |  2 +-
 tests/fw_cfg-test.c   | 48 +-----------------------------------------------
 tests/libqos/fw_cfg.c | 39 +++++++++++++++++++++++++++++++++++++++
 tests/libqos/fw_cfg.h | 22 ++++++++++++++++++++++
 4 files changed, 63 insertions(+), 48 deletions(-)
 create mode 100644 tests/libqos/fw_cfg.c
 create mode 100644 tests/libqos/fw_cfg.h

diff --git a/tests/Makefile b/tests/Makefile
index 7482297..7e436c0 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -130,7 +130,7 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
 
 tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
 
-libqos-obj-y = tests/libqos/pci.o
+libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o
 libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
 
 tests/rtc-test$(EXESUF): tests/rtc-test.o
diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c
index b784dc8..99643c0 100644
--- a/tests/fw_cfg-test.c
+++ b/tests/fw_cfg-test.c
@@ -2,18 +2,11 @@
 
 #include "libqtest.h"
 #include "hw/fw_cfg.h"
+#include "libqos/fw_cfg.h"
 
 #include <string.h>
 #include <glib.h>
 
-typedef struct QFWCFG QFWCFG;
-
-struct QFWCFG
-{
-    void (*select)(QFWCFG *fw_cfg, uint16_t key);
-    void (*read)(QFWCFG *fw_cfg, void *data, size_t len);
-};
-
 /* PC specific */
 
 static void pc_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
@@ -41,45 +34,6 @@ static QFWCFG *pc_fw_cfg_init(void)
     return fw_cfg;
 }
 
-/* Generic code */
-
-static void qfw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
-{
-    fw_cfg->select(fw_cfg, key);
-}
-
-static void qfw_cfg_read_data(QFWCFG *fw_cfg, void *data, size_t len)
-{
-    fw_cfg->read(fw_cfg, data, len);
-}
-
-static void qfw_cfg_get(QFWCFG *fw_cfg, uint16_t key, void *data, size_t len)
-{
-    qfw_cfg_select(fw_cfg, key);
-    qfw_cfg_read_data(fw_cfg, data, len);
-}
-
-static uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key)
-{
-    uint16_t value;
-    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
-    return value;
-}
-
-static uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key)
-{
-    uint32_t value;
-    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
-    return value;
-}
-
-static uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key)
-{
-    uint64_t value;
-    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
-    return value;
-}
-
 static uint64_t ram_size = 128 << 20;
 static uint16_t nb_cpus = 1;
 static uint16_t max_cpus = 1;
diff --git a/tests/libqos/fw_cfg.c b/tests/libqos/fw_cfg.c
new file mode 100644
index 0000000..f6f53c5
--- /dev/null
+++ b/tests/libqos/fw_cfg.c
@@ -0,0 +1,39 @@
+#include "libqos/fw_cfg.h"
+
+void qfw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
+{
+    fw_cfg->select(fw_cfg, key);
+}
+
+void qfw_cfg_read_data(QFWCFG *fw_cfg, void *data, size_t len)
+{
+    fw_cfg->read(fw_cfg, data, len);
+}
+
+void qfw_cfg_get(QFWCFG *fw_cfg, uint16_t key, void *data, size_t len)
+{
+    qfw_cfg_select(fw_cfg, key);
+    qfw_cfg_read_data(fw_cfg, data, len);
+}
+
+uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key)
+{
+    uint16_t value;
+    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+    return value;
+}
+
+uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key)
+{
+    uint32_t value;
+    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+    return value;
+}
+
+uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key)
+{
+    uint64_t value;
+    qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+    return value;
+}
+
diff --git a/tests/libqos/fw_cfg.h b/tests/libqos/fw_cfg.h
new file mode 100644
index 0000000..a82d2da
--- /dev/null
+++ b/tests/libqos/fw_cfg.h
@@ -0,0 +1,22 @@
+#ifndef LIBQOS_FW_CFG_H
+#define LIBQOS_FW_CFG_H
+
+#include <stdint.h>
+#include <sys/types.h>
+
+typedef struct QFWCFG QFWCFG;
+
+struct QFWCFG
+{
+    void (*select)(QFWCFG *fw_cfg, uint16_t key);
+    void (*read)(QFWCFG *fw_cfg, void *data, size_t len);
+};
+
+void qfw_cfg_select(QFWCFG *fw_cfg, uint16_t key);
+void qfw_cfg_read_data(QFWCFG *fw_cfg, void *data, size_t len);
+void qfw_cfg_get(QFWCFG *fw_cfg, uint16_t key, void *data, size_t len);
+uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key);
+uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key);
+uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key);
+
+#endif
-- 
1.8.0

[Qemu-devel] [RFC PATCH 7/8] libqos: add fw_cfg-pc

[Anthony Liguori]

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/Makefile           |  2 +-
 tests/fw_cfg-test.c      | 29 +----------------------------
 tests/libqos/fw_cfg-pc.c | 28 ++++++++++++++++++++++++++++
 tests/libqos/fw_cfg-pc.h |  8 ++++++++
 4 files changed, 38 insertions(+), 29 deletions(-)
 create mode 100644 tests/libqos/fw_cfg-pc.c
 create mode 100644 tests/libqos/fw_cfg-pc.h

diff --git a/tests/Makefile b/tests/Makefile
index 7e436c0..bfeee5e 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -131,7 +131,7 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
 tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
 
 libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o
-libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
+libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o tests/libqos/fw_cfg-pc.o
 
 tests/rtc-test$(EXESUF): tests/rtc-test.o
 tests/m48t59-test$(EXESUF): tests/m48t59-test.o
diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c
index 99643c0..03d62c8 100644
--- a/tests/fw_cfg-test.c
+++ b/tests/fw_cfg-test.c
@@ -2,38 +2,11 @@
 
 #include "libqtest.h"
 #include "hw/fw_cfg.h"
-#include "libqos/fw_cfg.h"
+#include "libqos/fw_cfg-pc.h"
 
 #include <string.h>
 #include <glib.h>
 
-/* PC specific */
-
-static void pc_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
-{
-    outw(0x510, key);
-}
-
-static void pc_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
-{
-    uint8_t *ptr = data;
-    int i;
-
-    for (i = 0; i < len; i++) {
-        ptr[i] = inb(0x511);
-    }
-}
-
-static QFWCFG *pc_fw_cfg_init(void)
-{
-    QFWCFG *fw_cfg = g_malloc0(sizeof(*fw_cfg));
-
-    fw_cfg->select = pc_fw_cfg_select;
-    fw_cfg->read = pc_fw_cfg_read;
-
-    return fw_cfg;
-}
-
 static uint64_t ram_size = 128 << 20;
 static uint16_t nb_cpus = 1;
 static uint16_t max_cpus = 1;
diff --git a/tests/libqos/fw_cfg-pc.c b/tests/libqos/fw_cfg-pc.c
new file mode 100644
index 0000000..9a5c1f8
--- /dev/null
+++ b/tests/libqos/fw_cfg-pc.c
@@ -0,0 +1,28 @@
+#include "libqos/fw_cfg-pc.h"
+#include "libqtest.h"
+#include <glib.h>
+
+static void pc_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
+{
+    outw(0x510, key);
+}
+
+static void pc_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
+{
+    uint8_t *ptr = data;
+    int i;
+
+    for (i = 0; i < len; i++) {
+        ptr[i] = inb(0x511);
+    }
+}
+
+QFWCFG *pc_fw_cfg_init(void)
+{
+    QFWCFG *fw_cfg = g_malloc0(sizeof(*fw_cfg));
+
+    fw_cfg->select = pc_fw_cfg_select;
+    fw_cfg->read = pc_fw_cfg_read;
+
+    return fw_cfg;
+}
diff --git a/tests/libqos/fw_cfg-pc.h b/tests/libqos/fw_cfg-pc.h
new file mode 100644
index 0000000..ba8c819
--- /dev/null
+++ b/tests/libqos/fw_cfg-pc.h
@@ -0,0 +1,8 @@
+#ifndef LIBQOS_FW_CFG_PC_H
+#define LIBQOS_FW_CFG_PC_H
+
+#include "libqos/fw_cfg.h"
+
+QFWCFG *pc_fw_cfg_init(void);
+
+#endif
-- 
1.8.0

[Qemu-devel] [RFC PATCH 8/8] libqos: add malloc

[Anthony Liguori]

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
 tests/Makefile           |  1 +
 tests/libqos/malloc-pc.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++
 tests/libqos/malloc-pc.h |  8 +++++++
 tests/libqos/malloc.h    | 26 +++++++++++++++++++++
 4 files changed, 94 insertions(+)
 create mode 100644 tests/libqos/malloc-pc.c
 create mode 100644 tests/libqos/malloc-pc.h
 create mode 100644 tests/libqos/malloc.h

diff --git a/tests/Makefile b/tests/Makefile
index bfeee5e..37442bf 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -132,6 +132,7 @@ tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
 
 libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o
 libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o tests/libqos/fw_cfg-pc.o
+libqos-pc-obj-y += tests/libqos/malloc-pc.o
 
 tests/rtc-test$(EXESUF): tests/rtc-test.o
 tests/m48t59-test$(EXESUF): tests/m48t59-test.o
diff --git a/tests/libqos/malloc-pc.c b/tests/libqos/malloc-pc.c
new file mode 100644
index 0000000..26868b7
--- /dev/null
+++ b/tests/libqos/malloc-pc.c
@@ -0,0 +1,59 @@
+#include "libqos/malloc-pc.h"
+#include "libqos/fw_cfg-pc.h"
+
+#define NO_QEMU_PROTOS
+#include "hw/fw_cfg.h"
+
+#include "qemu-common.h"
+#include <glib.h>
+
+#define PAGE_SIZE (4096)
+
+typedef struct PCAlloc
+{
+    QGuestAllocator alloc;
+
+    uint64_t start;
+    uint64_t end;
+} PCAlloc;
+
+static uint64_t pc_alloc(QGuestAllocator *allocator, size_t size)
+{
+    PCAlloc *s = container_of(allocator, PCAlloc, alloc);
+    uint64_t addr;
+
+
+    size += (PAGE_SIZE - 1);
+    size &= PAGE_SIZE;
+
+    g_assert_cmpint((s->start + size), <=, s->end);
+
+    addr = s->start;
+    s->start += size;
+
+    return addr;
+}
+
+static void pc_free(QGuestAllocator *allocator, uint64_t addr)
+{
+}
+
+QGuestAllocator *pc_alloc_init(void)
+{
+    PCAlloc *s = g_malloc0(sizeof(*s));
+    uint64_t ram_size;
+    QFWCFG *fw_cfg = pc_fw_cfg_init();
+
+    s->alloc.alloc = pc_alloc;
+    s->alloc.free = pc_free;
+
+    ram_size = qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE);
+
+    /* Start at 1MB */
+    s->start = 1 << 20;
+
+    /* Respect PCI hole */
+    s->end = MIN(ram_size, 0xE0000000);
+
+    return &s->alloc;
+}
diff --git a/tests/libqos/malloc-pc.h b/tests/libqos/malloc-pc.h
new file mode 100644
index 0000000..31f19eb
--- /dev/null
+++ b/tests/libqos/malloc-pc.h
@@ -0,0 +1,8 @@
+#ifndef LIBQOS_MALLOC_PC_H
+#define LIBQOS_MALLOC_PC_H
+
+#include "libqos/malloc.h"
+
+QGuestAllocator *pc_alloc_init(void);
+
+#endif
diff --git a/tests/libqos/malloc.h b/tests/libqos/malloc.h
new file mode 100644
index 0000000..5c06318
--- /dev/null
+++ b/tests/libqos/malloc.h
@@ -0,0 +1,26 @@
+#ifndef LIBQOS_MALLOC_H
+#define LIBQOS_MALLOC_H
+
+#include <stdint.h>
+#include <sys/types.h>
+
+typedef struct QGuestAllocator QGuestAllocator;
+
+struct QGuestAllocator
+{
+    uint64_t (*alloc)(QGuestAllocator *allocator, size_t size);
+    void (*free)(QGuestAllocator *allocator, uint64_t addr);
+};
+
+/* Always returns page aligned values */
+static inline uint64_t guest_alloc(QGuestAllocator *allocator, size_t size)
+{
+    return allocator->alloc(allocator, size);
+}
+
+static inline void guest_free(QGuestAllocator *allocator, uint64_t addr)
+{
+    allocator->alloc(allocator, addr);
+}
+
+#endif
-- 
1.8.0

Re: [Qemu-devel] [RFC PATCH 0/8] libqos support

[Stefan Hajnoczi]

On Tue, Mar 05, 2013 at 07:53:24AM -0600, Anthony Liguori wrote:
> This is a not completely polished version of libqos that includes PCI
> support.  I haven't gone through the patches thoroughly yet so I've got
> it marked as RFC.  It works and is functionally complete.  I know the
> files are missing copyrights though and the commit messages need some
> work.  I also haven't run checkpatch on the patches yet.

The PCI support looks pretty close.  The minimum functionality that
others can build on is the PCI support.  Merging the PCI support should
be uncontroversial.

The fw_cfg needs some patch reordering (best to introduce the fw_cfg pc
code in a separate source file from the start instead of moving it
later).

Stefan

Re: [Qemu-devel] [RFC PATCH 0/8] libqos support

[Anthony Liguori]

Stefan Hajnoczi <stefanha@redhat.com> writes:

> On Tue, Mar 05, 2013 at 07:53:24AM -0600, Anthony Liguori wrote:
>> This is a not completely polished version of libqos that includes PCI
>> support.  I haven't gone through the patches thoroughly yet so I've got
>> it marked as RFC.  It works and is functionally complete.  I know the
>> files are missing copyrights though and the commit messages need some
>> work.  I also haven't run checkpatch on the patches yet.
>
> The PCI support looks pretty close.  The minimum functionality that
> others can build on is the PCI support.  Merging the PCI support should
> be uncontroversial.
>
> The fw_cfg needs some patch reordering (best to introduce the fw_cfg pc
> code in a separate source file from the start instead of moving it
> later).

fw_cfg is needed in order to implement an alloc.  Alloc is needed in
order to do any form of DMA.

But I don't think it will be too hard to fix up this series into
something mergable.  The big issue was virtio support but now that
that's dropped, the rest is pretty easy.

Regards,

Anthony Liguori

>
> Stefan

Re: [Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Kevin Wolf]

Am 05.03.2013 um 14:53 hat Anthony Liguori geschrieben:
> This includes basic PCI support.
> 
> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

> +static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
> +{
> +    QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
> +    static const int bar_reg_map[] = {
> +        PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
> +        PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
> +    };
> +    int bar_reg;
> +    uint32_t addr;
> +    uint64_t size;
> +
> +    g_assert(barno >= 0 && barno <= 5);
> +    bar_reg = bar_reg_map[barno];
> +
> +    qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
> +    addr = qpci_config_readl(dev, bar_reg);
> +
> +    size = (1ULL << ctol(addr));

This doesn't look right. It should be something like:

    size = (1ULL << ctzl(addr & ~0x3));

In fact, what must be masked out differs for I/O (0x3) and memory (0xf).

> --- /dev/null
> +++ b/tests/libqos/pci.c
> @@ -0,0 +1,108 @@
> +#include "libqos/pci.h"
> +
> +#include "hw/pci/pci_regs.h"
> +#include <glib.h>
> +
> +#include <stdio.h>
> +
> +QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
> +{
> +    QPCIDevice *dev;
> +
> +    dev = g_malloc0(sizeof(*dev));

Where is the matching free? I can't seem to destroy a device I
once queried.

> +    dev->bus = bus;
> +    dev->devfn = devfn;
> +
> +    if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
> +        printf("vendor id is %x\n", qpci_config_readw(dev, PCI_VENDOR_ID));
> +        g_free(dev);
> +        return NULL;
> +    }
> +
> +    return dev;
> +}
> +
> +void qpci_device_enable(QPCIDevice *dev)
> +{
> +    uint16_t cmd;
> +
> +    /* FIXME -- does this need to be a bus callout? */
> +    cmd = qpci_config_readw(dev, PCI_COMMAND);
> +    cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
> +    qpci_config_writew(dev, PCI_COMMAND, cmd);
> +}

Wouldn't it make sense to enable bus mastering here as well? Forgetting
to do this manually is a trap that's easy to fall in...

Kevin

Re: [Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Andreas Färber]

Am 05.03.2013 14:53, schrieb Anthony Liguori:
> This includes basic PCI support.
> 
> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
> ---
>  configure             |   2 +-
>  tests/Makefile        |   2 +-
>  tests/libqos/pci-pc.c | 219 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  tests/libqos/pci-pc.h |   8 ++
>  tests/libqos/pci.c    | 108 +++++++++++++++++++++++++
>  tests/libqos/pci.h    |  65 +++++++++++++++
>  6 files changed, 402 insertions(+), 2 deletions(-)
>  create mode 100644 tests/libqos/pci-pc.c
>  create mode 100644 tests/libqos/pci-pc.h
>  create mode 100644 tests/libqos/pci.c
>  create mode 100644 tests/libqos/pci.h

This is missing a refactoring of existing I2C libqos:

tests/libi2c.[hc] -> tests/libqos/i2c.[hc]
tests/libi2c-omap.c -> tests/libqos/i2c-omap.c

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [RFC PATCH 8/8] libqos: add malloc

[Kevin Wolf]

Am 05.03.2013 um 14:53 hat Anthony Liguori geschrieben:
> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

> --- /dev/null
> +++ b/tests/libqos/malloc.h
> @@ -0,0 +1,26 @@
> +#ifndef LIBQOS_MALLOC_H
> +#define LIBQOS_MALLOC_H
> +
> +#include <stdint.h>
> +#include <sys/types.h>
> +
> +typedef struct QGuestAllocator QGuestAllocator;
> +
> +struct QGuestAllocator
> +{
> +    uint64_t (*alloc)(QGuestAllocator *allocator, size_t size);
> +    void (*free)(QGuestAllocator *allocator, uint64_t addr);
> +};
> +
> +/* Always returns page aligned values */
> +static inline uint64_t guest_alloc(QGuestAllocator *allocator, size_t size)
> +{
> +    return allocator->alloc(allocator, size);
> +}
> +
> +static inline void guest_free(QGuestAllocator *allocator, uint64_t addr)
> +{
> +    allocator->alloc(allocator, addr);
> +}

I think the common case is using exactly one global allocator. Maybe
worth convenience macros like in libqtest.h?

Kevin

Re: [Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Anthony Liguori]

Kevin Wolf <kwolf@redhat.com> writes:

> Am 05.03.2013 um 14:53 hat Anthony Liguori geschrieben:
>> This includes basic PCI support.
>> 
>> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
>
>> +static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
>> +{
>> +    QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
>> +    static const int bar_reg_map[] = {
>> +        PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
>> +        PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
>> +    };
>> +    int bar_reg;
>> +    uint32_t addr;
>> +    uint64_t size;
>> +
>> +    g_assert(barno >= 0 && barno <= 5);
>> +    bar_reg = bar_reg_map[barno];
>> +
>> +    qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
>> +    addr = qpci_config_readl(dev, bar_reg);
>> +
>> +    size = (1ULL << ctol(addr));
>
> This doesn't look right. It should be something like:
>
>     size = (1ULL << ctzl(addr & ~0x3));
>
> In fact, what must be masked out differs for I/O (0x3) and memory
> (0xf).

You are correct, it should look something like:

if (addr & PCI_BASE_ADDRESS_SPACE_IO) {
    size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_IO_MASK));
} else {
    size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_MEM_MASK));
}

This doesn't deal with 64-bit bars though.

I'll update in the next round.  I think this has worked for me because I
have only done single device testing.  I did switch from ffz when I
rebased but I think ffz would still have this problem.

>> +QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
>> +{
>> +    QPCIDevice *dev;
>> +
>> +    dev = g_malloc0(sizeof(*dev));
>
> Where is the matching free? I can't seem to destroy a device I
> once queried.

It's missing, I'll add it in the next round.

>> +    dev->bus = bus;
>> +    dev->devfn = devfn;
>> +
>> +    if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
>> +        printf("vendor id is %x\n", qpci_config_readw(dev, PCI_VENDOR_ID));
>> +        g_free(dev);
>> +        return NULL;
>> +    }
>> +
>> +    return dev;
>> +}
>> +
>> +void qpci_device_enable(QPCIDevice *dev)
>> +{
>> +    uint16_t cmd;
>> +
>> +    /* FIXME -- does this need to be a bus callout? */
>> +    cmd = qpci_config_readw(dev, PCI_COMMAND);
>> +    cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
>> +    qpci_config_writew(dev, PCI_COMMAND, cmd);
>> +}
>
> Wouldn't it make sense to enable bus mastering here as well? Forgetting
> to do this manually is a trap that's easy to fall in...

Indeed, thanks for pointing it out.

Regards,

Anthony Liguori

>
> Kevin

Re: [Qemu-devel] [RFC PATCH 8/8] libqos: add malloc

[Anthony Liguori]

Kevin Wolf <kwolf@redhat.com> writes:

> Am 05.03.2013 um 14:53 hat Anthony Liguori geschrieben:
>> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
>
>> --- /dev/null
>> +++ b/tests/libqos/malloc.h
>> @@ -0,0 +1,26 @@
>> +#ifndef LIBQOS_MALLOC_H
>> +#define LIBQOS_MALLOC_H
>> +
>> +#include <stdint.h>
>> +#include <sys/types.h>
>> +
>> +typedef struct QGuestAllocator QGuestAllocator;
>> +
>> +struct QGuestAllocator
>> +{
>> +    uint64_t (*alloc)(QGuestAllocator *allocator, size_t size);
>> +    void (*free)(QGuestAllocator *allocator, uint64_t addr);
>> +};
>> +
>> +/* Always returns page aligned values */
>> +static inline uint64_t guest_alloc(QGuestAllocator *allocator, size_t size)
>> +{
>> +    return allocator->alloc(allocator, size);
>> +}
>> +
>> +static inline void guest_free(QGuestAllocator *allocator, uint64_t addr)
>> +{
>> +    allocator->alloc(allocator, addr);
>> +}
>
> I think the common case is using exactly one global allocator. Maybe
> worth convenience macros like in libqtest.h?

Definitely.

Regard,

Anthony Liguori

>
> Kevin

Re: [Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Kevin Wolf]

Am 13.03.2013 um 15:03 hat Anthony Liguori geschrieben:
> You are correct, it should look something like:
> 
> if (addr & PCI_BASE_ADDRESS_SPACE_IO) {
>     size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_IO_MASK));
> } else {
>     size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_MEM_MASK));
> }
> 
> This doesn't deal with 64-bit bars though.
> 
> I'll update in the next round.  I think this has worked for me because I
> have only done single device testing.  I did switch from ffz when I
> rebased but I think ffz would still have this problem.

For when are you planning the next round? Will we get this in time to
make use of it in 1.5?

Kevin

Re: [Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Anthony Liguori]

Kevin Wolf <kwolf@redhat.com> writes:

> Am 13.03.2013 um 15:03 hat Anthony Liguori geschrieben:
>> You are correct, it should look something like:
>> 
>> if (addr & PCI_BASE_ADDRESS_SPACE_IO) {
>>     size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_IO_MASK));
>> } else {
>>     size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_MEM_MASK));
>> }
>> 
>> This doesn't deal with 64-bit bars though.
>> 
>> I'll update in the next round.  I think this has worked for me because I
>> have only done single device testing.  I did switch from ffz when I
>> rebased but I think ffz would still have this problem.
>
> For when are you planning the next round?

I'll send one out soon.  Perhaps tomorrow if all goes well.

Regards,

Anthony Liguori

> Will we get this in time to make use of it in 1.5?

>
> Kevin

Re: [Qemu-devel] [RFC PATCH 1/8] qtest: add libqos

[Kevin Wolf]

Am 29.03.2013 um 03:26 hat Anthony Liguori geschrieben:
> Kevin Wolf <kwolf@redhat.com> writes:
> 
> > Am 13.03.2013 um 15:03 hat Anthony Liguori geschrieben:
> >> You are correct, it should look something like:
> >> 
> >> if (addr & PCI_BASE_ADDRESS_SPACE_IO) {
> >>     size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_IO_MASK));
> >> } else {
> >>     size = (1ULL << ctzl(addr & PCI_BASE_ADDRESS_MEM_MASK));
> >> }
> >> 
> >> This doesn't deal with 64-bit bars though.
> >> 
> >> I'll update in the next round.  I think this has worked for me because I
> >> have only done single device testing.  I did switch from ffz when I
> >> rebased but I think ffz would still have this problem.
> >
> > For when are you planning the next round?
> 
> I'll send one out soon.  Perhaps tomorrow if all goes well.

I know, it's getting boring, but... which tomorrow?

Please just add the license headers and get the RFC committed. We'll get
the rest fixed up on top. We've been waiting for over a year now. This is
blocking any progress on the qtest coverage and probably already hurting
the quality of our releases.

Kevin

Re: [Qemu-devel] [RFC PATCH 0/8] libqos support

[Anthony Liguori]

Applied.  Thanks.

Regards,

Anthony Liguori