From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULcd4-0007m1-D4 for qemu-devel@nongnu.org; Fri, 29 Mar 2013 12:58:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULcd3-0007qe-27 for qemu-devel@nongnu.org; Fri, 29 Mar 2013 12:58:14 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:38359) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULcd2-0007qS-Rf for qemu-devel@nongnu.org; Fri, 29 Mar 2013 12:58:12 -0400 Date: Fri, 29 Mar 2013 17:58:03 +0100 From: Aurelien Jarno Message-ID: <20130329165803.GJ5000@ohm.aurel32.net> References: <1364484781-15561-1-git-send-email-rth@twiddle.net> <1364484781-15561-4-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1364484781-15561-4-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH v3 03/20] tcg-arm: Allow constant first argument to sub List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Peter Maydell , qemu-devel@nongnu.org On Thu, Mar 28, 2013 at 08:32:44AM -0700, Richard Henderson wrote: > This allows the generation of RSB instructions. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c > index f470caa..7475142 100644 > --- a/tcg/arm/tcg-target.c > +++ b/tcg/arm/tcg-target.c > @@ -1665,8 +1665,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > args[0], args[1], args[2], const_args[2]); > break; > case INDEX_op_sub_i32: > - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, > - args[0], args[1], args[2], const_args[2]); > + if (const_args[1]) { > + if (const_args[2]) { > + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); > + } else { > + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, > + args[0], args[2], args[1], 1); > + } > + } else { > + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, > + args[0], args[1], args[2], const_args[2]); > + } > break; > case INDEX_op_and_i32: > tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, > @@ -1859,7 +1868,7 @@ static const TCGTargetOpDef arm_op_defs[] = { > > /* TODO: "r", "r", "ri" */ > { INDEX_op_add_i32, { "r", "r", "rIN" } }, > - { INDEX_op_sub_i32, { "r", "r", "rIN" } }, > + { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, > { INDEX_op_mul_i32, { "r", "r", "r" } }, > { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, > { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net