From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 2/2] tcg-ia64: implement add2_i32/i64 and sub2_i32/i64
Date: Sat, 30 Mar 2013 23:05:11 +0100 [thread overview]
Message-ID: <20130330220511.GF22106@hall.aurel32.net> (raw)
In-Reply-To: <51570A9B.2040306@twiddle.net>
On Sat, Mar 30, 2013 at 08:54:03AM -0700, Richard Henderson wrote:
> On 03/30/2013 08:33 AM, Aurelien Jarno wrote:
> > +static inline void tcg_out_add2(TCGContext *s, TCGArg retl, TCGArg reth,
> > + TCGArg arg1l, TCGArg arg1h,
> > + TCGArg arg2l, TCGArg arg2h,
> > + int cmp4)
> > +{
> > + tcg_out_bundle(s, MmI,
> > + tcg_opc_a1(TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, arg1l, arg2l),
> > + tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
> > + tcg_opc_cmp_a(TCG_REG_P0, TCG_COND_LTU,
> > + TCG_REG_R2, arg1l, cmp4));
>
> I seem to recall a 1-cycle cross-unit delay, going between M to I units?
> Maybe that was just the itanic1, it's been so long...?
>
> Anyway, in this case it's easy to avoid by putting the nop first and using
> an mII bundle.
I'll do that in the next version, thanks for the review.
> That said, the code looks correct.
>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
>
>
> r~
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2013-03-30 22:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-30 15:33 [Qemu-devel] [PATCH 1/2] tcg-ia64: implement mulu2_i32/i64 and muls2_i32/i64 Aurelien Jarno
2013-03-30 15:33 ` [Qemu-devel] [PATCH 2/2] tcg-ia64: implement add2_i32/i64 and sub2_i32/i64 Aurelien Jarno
2013-03-30 15:54 ` Richard Henderson
2013-03-30 22:05 ` Aurelien Jarno [this message]
2013-03-30 16:00 ` [Qemu-devel] [PATCH 1/2] tcg-ia64: implement mulu2_i32/i64 and muls2_i32/i64 Richard Henderson
2013-03-30 22:04 ` Aurelien Jarno
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