From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM3th-00018L-NH for qemu-devel@nongnu.org; Sat, 30 Mar 2013 18:05:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UM3tf-0001uq-W9 for qemu-devel@nongnu.org; Sat, 30 Mar 2013 18:05:13 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:44227) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM3tf-0001ul-Q6 for qemu-devel@nongnu.org; Sat, 30 Mar 2013 18:05:11 -0400 Date: Sat, 30 Mar 2013 23:05:11 +0100 From: Aurelien Jarno Message-ID: <20130330220511.GF22106@hall.aurel32.net> References: <1364657589-16123-1-git-send-email-aurelien@aurel32.net> <1364657589-16123-2-git-send-email-aurelien@aurel32.net> <51570A9B.2040306@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <51570A9B.2040306@twiddle.net> Sender: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 2/2] tcg-ia64: implement add2_i32/i64 and sub2_i32/i64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Sat, Mar 30, 2013 at 08:54:03AM -0700, Richard Henderson wrote: > On 03/30/2013 08:33 AM, Aurelien Jarno wrote: > > +static inline void tcg_out_add2(TCGContext *s, TCGArg retl, TCGArg reth, > > + TCGArg arg1l, TCGArg arg1h, > > + TCGArg arg2l, TCGArg arg2h, > > + int cmp4) > > +{ > > + tcg_out_bundle(s, MmI, > > + tcg_opc_a1(TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, arg1l, arg2l), > > + tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), > > + tcg_opc_cmp_a(TCG_REG_P0, TCG_COND_LTU, > > + TCG_REG_R2, arg1l, cmp4)); > > I seem to recall a 1-cycle cross-unit delay, going between M to I units? > Maybe that was just the itanic1, it's been so long...? > > Anyway, in this case it's easy to avoid by putting the nop first and using > an mII bundle. I'll do that in the next version, thanks for the review. > That said, the code looks correct. > > Reviewed-by: Richard Henderson > > > r~ > > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net