From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: av1474@comtv.ru, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 14/27] tcg-ppc64: Streamline qemu_ld/st insn selection
Date: Mon, 1 Apr 2013 16:56:23 +0200 [thread overview]
Message-ID: <20130401145623.GA16663@ohm.aurel32.net> (raw)
In-Reply-To: <1362443590-28191-15-git-send-email-rth@twiddle.net>
On Mon, Mar 04, 2013 at 04:32:57PM -0800, Richard Henderson wrote:
> Using a table to look up insns of the right width and sign.
> Include support for the Power 2.05 LDBRX and STDBRX insns
> included in e.g. Power6.
These instructions have actually been added in the Power 2.06
specification. The documentation is a bit misleading, the 2.05 bit in
the PCR being set means these instrutions are *not* available.
Otherwise the patch looks fine.
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/ppc64/tcg-target.c | 166 +++++++++++++++++--------------------------------
> 1 file changed, 56 insertions(+), 110 deletions(-)
>
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 51a5545..4a55ae7 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -44,6 +44,8 @@ static uint8_t *tb_ret_addr;
> #define GUEST_BASE 0
> #endif
>
> +#define HAVE_ISA_2_05 0
> +
> #ifdef CONFIG_USE_GUEST_BASE
> #define TCG_GUEST_BASE_REG 30
> #else
> @@ -368,8 +370,10 @@ static int tcg_target_const_match (tcg_target_long val,
> #define CMPL XO31( 32)
> #define LHBRX XO31(790)
> #define LWBRX XO31(534)
> +#define LDBRX XO31(532)
> #define STHBRX XO31(918)
> #define STWBRX XO31(662)
> +#define STDBRX XO31(660)
> #define MFSPR XO31(339)
> #define MTSPR XO31(467)
> #define SRAWI XO31(824)
> @@ -759,22 +763,44 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
> }
> #endif
>
> +static const uint32_t qemu_ldx_opc[8] = {
> +#ifdef TARGET_WORDS_BIGENDIAN
> + LBZX, LHZX, LWZX, LDX,
> + 0, LHAX, LWAX, LDX
> +#else
> + LBZX, LHBRX, LWBRX, LDBRX,
> + 0, 0, 0, LDBRX,
> +#endif
> +};
> +
> +static const uint32_t qemu_stx_opc[4] = {
> +#ifdef TARGET_WORDS_BIGENDIAN
> + STBX, STHX, STWX, STDX
> +#else
> + STBX, STHBRX, STWBRX, STDBRX,
> +#endif
> +};
> +
> +static const uint32_t qemu_exts_opc[4] = {
> + EXTSB, EXTSH, EXTSW, 0
> +};
> +
> static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
> {
> TCGReg addr_reg, data_reg, r0, r1, rbase;
> - int bswap;
> + uint32_t insn, s_bits;
> #ifdef CONFIG_SOFTMMU
> TCGReg r2, ir;
> - int mem_index, s_bits;
> + int mem_index;
> void *label1_ptr, *label2_ptr;
> #endif
>
> data_reg = *args++;
> addr_reg = *args++;
> + s_bits = opc & 3;
>
> #ifdef CONFIG_SOFTMMU
> mem_index = *args;
> - s_bits = opc & 3;
>
> r0 = 3;
> r1 = 4;
> @@ -799,23 +825,11 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>
> tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
>
> - switch (opc) {
> - case 0|4:
> - tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
> - break;
> - case 1|4:
> - tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
> - break;
> - case 2|4:
> - tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
> - break;
> - case 0:
> - case 1:
> - case 2:
> - case 3:
> - if (data_reg != 3)
> - tcg_out_mov (s, TCG_TYPE_I64, data_reg, 3);
> - break;
> + if (opc & 4) {
> + insn = qemu_exts_opc[s_bits];
> + tcg_out32(s, insn | RA(data_reg) | RS(3));
> + } else if (data_reg != 3) {
> + tcg_out_mov(s, TCG_TYPE_I64, data_reg, 3);
> }
> label2_ptr = s->code_ptr;
> tcg_out32 (s, B);
> @@ -842,65 +856,19 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
> rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
> #endif
>
> -#ifdef TARGET_WORDS_BIGENDIAN
> - bswap = 0;
> -#else
> - bswap = 1;
> -#endif
> - switch (opc) {
> - default:
> - case 0:
> - tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
> - break;
> - case 0|4:
> - tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
> - tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
> - break;
> - case 1:
> - if (bswap)
> - tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
> - else
> - tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
> - break;
> - case 1|4:
> - if (bswap) {
> - tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
> - tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
> - }
> - else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
> - break;
> - case 2:
> - if (bswap)
> - tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
> - else
> - tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
> - break;
> - case 2|4:
> - if (bswap) {
> - tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
> - tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
> - }
> - else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
> - break;
> - case 3:
> -#ifdef CONFIG_USE_GUEST_BASE
> - if (bswap) {
> - tcg_out32(s, ADDI | TAI(r1, r0, 4));
> - tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
> - tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
> - tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
> - }
> - else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
> -#else
> - if (bswap) {
> - tcg_out_movi32 (s, 0, 4);
> - tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
> - tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
> - tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
> - }
> - else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
> -#endif
> - break;
> + insn = qemu_ldx_opc[opc];
> + if (!HAVE_ISA_2_05 && insn == LDBRX) {
> + tcg_out32(s, ADDI | TAI(r1, r0, 4));
> + tcg_out32(s, LWBRX | TAB(data_reg, rbase, r0));
> + tcg_out32(s, LWBRX | TAB( r1, rbase, r1));
> + tcg_out_rld(s, RLDIMI, data_reg, r1, 32, 0);
> + } else if (insn) {
> + tcg_out32(s, insn | TAB(data_reg, rbase, r0));
> + } else {
> + insn = qemu_ldx_opc[s_bits];
> + tcg_out32(s, insn | TAB(data_reg, rbase, r0));
> + insn = qemu_exts_opc[s_bits];
> + tcg_out32 (s, insn | RA(data_reg) | RS(data_reg));
> }
>
> #ifdef CONFIG_SOFTMMU
> @@ -911,7 +879,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
> static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
> {
> TCGReg addr_reg, r0, r1, rbase, data_reg;
> - int bswap;
> + uint32_t insn;
> #ifdef CONFIG_SOFTMMU
> TCGReg r2, ir;
> int mem_index;
> @@ -975,36 +943,14 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
> rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
> #endif
>
> -#ifdef TARGET_WORDS_BIGENDIAN
> - bswap = 0;
> -#else
> - bswap = 1;
> -#endif
> - switch (opc) {
> - case 0:
> - tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
> - break;
> - case 1:
> - if (bswap)
> - tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
> - else
> - tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
> - break;
> - case 2:
> - if (bswap)
> - tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
> - else
> - tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
> - break;
> - case 3:
> - if (bswap) {
> - tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
> - tcg_out32(s, ADDI | TAI(r1, r0, 4));
> - tcg_out_shri64(s, 0, data_reg, 32);
> - tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
> - }
> - else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
> - break;
> + insn = qemu_stx_opc[opc];
> + if (!HAVE_ISA_2_05 && insn == STDBRX) {
> + tcg_out32(s, STWBRX | SAB(data_reg, rbase, r0));
> + tcg_out32(s, ADDI | TAI(r1, r0, 4));
> + tcg_out_shri64(s, 0, data_reg, 32);
> + tcg_out32(s, STWBRX | SAB(0, rbase, r1));
> + } else {
> + tcg_out32(s, insn | SAB(data_reg, rbase, r0));
> }
>
> #ifdef CONFIG_SOFTMMU
> --
> 1.8.1.2
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2013-04-01 14:56 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-05 0:32 [Qemu-devel] [PATCH v2 00/27] Modernize tcg/ppc64 Richard Henderson
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 01/27] disas: Disassemble all ppc insns for the host Richard Henderson
2013-04-01 14:51 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 02/27] tcg-ppc64: Use TCGReg everywhere Richard Henderson
2013-04-01 14:51 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 03/27] tcg-ppc64: Introduce and use tcg_out_rlw Richard Henderson
2013-04-01 14:51 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 04/27] tcg-ppc64: Introduce and use tcg_out_ext32u Richard Henderson
2013-04-01 14:51 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 05/27] tcg-ppc64: Introduce and use tcg_out_shli64 Richard Henderson
2013-04-01 14:52 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 06/27] tcg-ppc64: Introduce and use tcg_out_shri64 Richard Henderson
2013-04-01 14:52 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 07/27] tcg-ppc64: Cleanup tcg_out_movi Richard Henderson
2013-04-01 14:52 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 08/27] tcg-ppc64: Introduce and use TAI and SAI Richard Henderson
2013-04-01 14:52 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 09/27] tcg-ppc64: Rearrange integer constant constraints Richard Henderson
2013-04-01 14:53 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 10/27] tcg-ppc64: Improve constant add and sub ops Richard Henderson
2013-04-01 14:54 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 11/27] tcg-ppc64: Tidy or and xor patterns Richard Henderson
2013-04-01 14:55 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 12/27] tcg-ppc64: Improve and_i32 with constant Richard Henderson
2013-04-01 14:55 ` Aurelien Jarno
2013-04-01 15:43 ` Richard Henderson
2013-04-01 15:58 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 13/27] tcg-ppc64: Improve and_i64 " Richard Henderson
2013-04-01 14:56 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 14/27] tcg-ppc64: Streamline qemu_ld/st insn selection Richard Henderson
2013-04-01 14:56 ` Aurelien Jarno [this message]
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 15/27] tcg-ppc64: Implement rotates Richard Henderson
2013-04-01 14:58 ` Aurelien Jarno
2013-03-05 0:32 ` [Qemu-devel] [PATCH v2 16/27] tcg-ppc64: Implement bswap16 and bswap32 Richard Henderson
2013-04-01 14:57 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 17/27] tcg-ppc64: Implement bswap64 Richard Henderson
2013-04-01 14:58 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 18/27] tcg-ppc64: Implement compound logicals Richard Henderson
2013-04-01 14:58 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 19/27] tcg-ppc64: Handle constant inputs for some " Richard Henderson
2013-04-01 14:58 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 20/27] tcg-ppc64: Implement deposit Richard Henderson
2013-04-01 14:58 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 21/27] tcg-ppc64: Use I constraint for mul Richard Henderson
2013-04-01 14:59 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 22/27] tcg-ppc64: Use TCGType throughout compares Richard Henderson
2013-04-01 14:59 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 23/27] tcg-ppc64: Rewrite setcond Richard Henderson
2013-04-01 14:59 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 24/27] tcg-ppc64: Implement movcond Richard Henderson
2013-04-01 14:59 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 25/27] tcg-ppc64: Use getauxval for ISA detection Richard Henderson
2013-04-01 15:00 ` Aurelien Jarno
2013-04-01 16:07 ` Richard Henderson
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 26/27] tcg-ppc64: Implement add2/sub2_i64 Richard Henderson
2013-04-01 15:00 ` Aurelien Jarno
2013-03-05 0:33 ` [Qemu-devel] [PATCH v2 27/27] tcg-ppc64: Implement mulu2/muls2_i64 Richard Henderson
2013-04-01 15:00 ` Aurelien Jarno
2013-03-12 6:41 ` [Qemu-devel] [PATCH v2 00/27] Modernize tcg/ppc64 Richard Henderson
2013-03-20 0:17 ` Richard Henderson
2013-03-30 16:54 ` Richard Henderson
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