From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UPqwA-0002YK-8O for qemu-devel@nongnu.org; Wed, 10 Apr 2013 05:03:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UPqw9-00073r-0I for qemu-devel@nongnu.org; Wed, 10 Apr 2013 05:03:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:11944) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UPqw8-00073h-Ol for qemu-devel@nongnu.org; Wed, 10 Apr 2013 05:03:24 -0400 Date: Wed, 10 Apr 2013 11:03:18 +0200 From: Igor Mammedov Message-ID: <20130410110318.4d8602f0@nial.usersys.redhat.com> In-Reply-To: <1365583921.9553.101.camel@liguang.fnst.cn.fujitsu.com> References: <1365580949-32467-1-git-send-email-lig.fnst@cn.fujitsu.com> <20130410103415.60c53beb@nial.usersys.redhat.com> <1365583921.9553.101.camel@liguang.fnst.cn.fujitsu.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 1/2] target-i386: remove cpu reset callback List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: li guang Cc: afaerber@suse.de, qemu-devel@nongnu.org On Wed, 10 Apr 2013 16:52:01 +0800 li guang wrote: > =E5=9C=A8 2013-04-10=E4=B8=89=E7=9A=84 10:34 +0200=EF=BC=8CIgor Mammedov= =E5=86=99=E9=81=93=EF=BC=9A > > On Wed, 10 Apr 2013 16:02:28 +0800 > > liguang wrote: > >=20 > > > we should remove it now, if not, cpu reset > > > will do 2 times. > > Currently CPU is bus-less device so there isn't anything to reset it > > during reboot except callback.=20 > > This patch will break reboot path, just try guest reboot from inside > > guest. >=20 > Yes, thanks! > and, should we care as I found > cpu reset will do more than 1 times > during boot? reset in realize() is fro the sake of hot-plug and it doesn't hurt. Removing callback could be considered once CPU is attached to ICC bus, but I haven't looked in that direction yet. > >=20 > >=20 > > > Signed-off-by: liguang > > > --- > > > target-i386/cpu.c | 9 --------- > > > 1 files changed, 0 insertions(+), 9 deletions(-) > > >=20 > > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > > > index 356378c..6e13053 100644 > > > --- a/target-i386/cpu.c > > > +++ b/target-i386/cpu.c > > > @@ -2024,13 +2024,6 @@ bool cpu_is_bsp(X86CPU *cpu) > > > { > > > return cpu_get_apic_base(cpu->env.apic_state) & > > > MSR_IA32_APICBASE_BSP; } > > > - > > > -/* TODO: remove me, when reset over QOM tree is implemented */ > > > -static void x86_cpu_machine_reset_cb(void *opaque) > > > -{ > > > - X86CPU *cpu =3D opaque; > > > - cpu_reset(CPU(cpu)); > > > -} > > > #endif > > > =20 > > > static void mce_init(X86CPU *cpu) > > > @@ -2140,8 +2133,6 @@ static void x86_cpu_realizefn(DeviceState *dev, > > > Error **errp) } > > > =20 > > > #ifndef CONFIG_USER_ONLY > > > - qemu_register_reset(x86_cpu_machine_reset_cb, cpu); > > > - > > > if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) { > > > x86_cpu_apic_init(cpu, &local_err); > > > if (local_err !=3D NULL) { > >=20 >=20 >=20