[Qemu-devel] [PATCH 1/2] target-i386: remove cpu reset callback

[Qemu-devel] [PATCH 1/2] target-i386: remove cpu reset callback

[liguang]

we should remove it now, if not, cpu reset
will do 2 times.

Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
 target-i386/cpu.c |    9 ---------
 1 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 356378c..6e13053 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2024,13 +2024,6 @@ bool cpu_is_bsp(X86CPU *cpu)
 {
     return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
 }
-
-/* TODO: remove me, when reset over QOM tree is implemented */
-static void x86_cpu_machine_reset_cb(void *opaque)
-{
-    X86CPU *cpu = opaque;
-    cpu_reset(CPU(cpu));
-}
 #endif
 
 static void mce_init(X86CPU *cpu)
@@ -2140,8 +2133,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
 #ifndef CONFIG_USER_ONLY
-    qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
-
     if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
         x86_cpu_apic_init(cpu, &local_err);
         if (local_err != NULL) {
-- 
1.7.2.5

[Qemu-devel] [PATCH 2/2] target-i386: fix 2 malformed indents

[liguang]

Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
 target-i386/cpu.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 6e13053..9806a60 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2108,7 +2108,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
         env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
         env->cpuid_ext2_features |= (env->cpuid_features
-           & CPUID_EXT2_AMD_ALIASES);
+                                     & CPUID_EXT2_AMD_ALIASES);
     }
 
     if (!kvm_enabled()) {
@@ -2116,7 +2116,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
         env->cpuid_ext_features &= TCG_EXT_FEATURES;
         env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
 #ifdef TARGET_X86_64
-            | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
+                                     | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
 #endif
             );
         env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
-- 
1.7.2.5

Re: [Qemu-devel] [PATCH 1/2] target-i386: remove cpu reset callback

[Igor Mammedov]

On Wed, 10 Apr 2013 16:02:28 +0800
liguang <lig.fnst@cn.fujitsu.com> wrote:

> we should remove it now, if not, cpu reset
> will do 2 times.
Currently CPU is bus-less device so there isn't anything to reset it during
reboot except callback. 
This patch will break reboot path, just try guest reboot from inside guest.


> Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
> ---
>  target-i386/cpu.c |    9 ---------
>  1 files changed, 0 insertions(+), 9 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 356378c..6e13053 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2024,13 +2024,6 @@ bool cpu_is_bsp(X86CPU *cpu)
>  {
>      return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
>  }
> -
> -/* TODO: remove me, when reset over QOM tree is implemented */
> -static void x86_cpu_machine_reset_cb(void *opaque)
> -{
> -    X86CPU *cpu = opaque;
> -    cpu_reset(CPU(cpu));
> -}
>  #endif
>  
>  static void mce_init(X86CPU *cpu)
> @@ -2140,8 +2133,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
> **errp) }
>  
>  #ifndef CONFIG_USER_ONLY
> -    qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
> -
>      if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
>          x86_cpu_apic_init(cpu, &local_err);
>          if (local_err != NULL) {

Re: [Qemu-devel] [PATCH 1/2] target-i386: remove cpu reset callback

[li guang]

在 2013-04-10三的 10:34 +0200，Igor Mammedov写道：
> On Wed, 10 Apr 2013 16:02:28 +0800
> liguang <lig.fnst@cn.fujitsu.com> wrote:
> 
> > we should remove it now, if not, cpu reset
> > will do 2 times.
> Currently CPU is bus-less device so there isn't anything to reset it during
> reboot except callback. 
> This patch will break reboot path, just try guest reboot from inside guest.

Yes, thanks!
and, should we care as I found
cpu reset will do more than 1 times
during boot?

> 
> 
> > Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
> > ---
> >  target-i386/cpu.c |    9 ---------
> >  1 files changed, 0 insertions(+), 9 deletions(-)
> > 
> > diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> > index 356378c..6e13053 100644
> > --- a/target-i386/cpu.c
> > +++ b/target-i386/cpu.c
> > @@ -2024,13 +2024,6 @@ bool cpu_is_bsp(X86CPU *cpu)
> >  {
> >      return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
> >  }
> > -
> > -/* TODO: remove me, when reset over QOM tree is implemented */
> > -static void x86_cpu_machine_reset_cb(void *opaque)
> > -{
> > -    X86CPU *cpu = opaque;
> > -    cpu_reset(CPU(cpu));
> > -}
> >  #endif
> >  
> >  static void mce_init(X86CPU *cpu)
> > @@ -2140,8 +2133,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
> > **errp) }
> >  
> >  #ifndef CONFIG_USER_ONLY
> > -    qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
> > -
> >      if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
> >          x86_cpu_apic_init(cpu, &local_err);
> >          if (local_err != NULL) {
> 

Re: [Qemu-devel] [PATCH 1/2] target-i386: remove cpu reset callback

[Igor Mammedov]

On Wed, 10 Apr 2013 16:52:01 +0800
li guang <lig.fnst@cn.fujitsu.com> wrote:

> 在 2013-04-10三的 10:34 +0200，Igor Mammedov写道：
> > On Wed, 10 Apr 2013 16:02:28 +0800
> > liguang <lig.fnst@cn.fujitsu.com> wrote:
> > 
> > > we should remove it now, if not, cpu reset
> > > will do 2 times.
> > Currently CPU is bus-less device so there isn't anything to reset it
> > during reboot except callback. 
> > This patch will break reboot path, just try guest reboot from inside
> > guest.
> 
> Yes, thanks!
> and, should we care as I found
> cpu reset will do more than 1 times
> during boot?

reset in realize() is fro the sake of hot-plug and it doesn't hurt.
Removing callback could be considered once CPU is attached to
ICC bus, but I haven't looked in that direction yet.

> > 
> > 
> > > Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
> > > ---
> > >  target-i386/cpu.c |    9 ---------
> > >  1 files changed, 0 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> > > index 356378c..6e13053 100644
> > > --- a/target-i386/cpu.c
> > > +++ b/target-i386/cpu.c
> > > @@ -2024,13 +2024,6 @@ bool cpu_is_bsp(X86CPU *cpu)
> > >  {
> > >      return cpu_get_apic_base(cpu->env.apic_state) &
> > > MSR_IA32_APICBASE_BSP; }
> > > -
> > > -/* TODO: remove me, when reset over QOM tree is implemented */
> > > -static void x86_cpu_machine_reset_cb(void *opaque)
> > > -{
> > > -    X86CPU *cpu = opaque;
> > > -    cpu_reset(CPU(cpu));
> > > -}
> > >  #endif
> > >  
> > >  static void mce_init(X86CPU *cpu)
> > > @@ -2140,8 +2133,6 @@ static void x86_cpu_realizefn(DeviceState *dev,
> > > Error **errp) }
> > >  
> > >  #ifndef CONFIG_USER_ONLY
> > > -    qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
> > > -
> > >      if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
> > >          x86_cpu_apic_init(cpu, &local_err);
> > >          if (local_err != NULL) {
> > 
> 
>