From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UReFL-0007W0-1z for qemu-devel@nongnu.org; Mon, 15 Apr 2013 03:54:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UReFI-0004ET-W2 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 03:54:38 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:48866) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UReFI-0004EM-QC for qemu-devel@nongnu.org; Mon, 15 Apr 2013 03:54:36 -0400 Date: Mon, 15 Apr 2013 09:54:30 +0200 From: Aurelien Jarno Message-ID: <20130415075430.GA11433@ohm.aurel32.net> References: <1365116186-19382-1-git-send-email-rth@twiddle.net> <1365116186-19382-9-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1365116186-19382-9-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH v4 08/33] tcg-ppc64: Fix setcond_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: av1474@comtv.ru, qemu-devel@nongnu.org On Thu, Apr 04, 2013 at 05:56:01PM -0500, Richard Henderson wrote: > We weren't ignoring the high 32 bits during a NE comparison. > > Signed-off-by: Richard Henderson > --- > tcg/ppc64/tcg-target.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c > index b12cbec..822eb07 100644 > --- a/tcg/ppc64/tcg-target.c > +++ b/tcg/ppc64/tcg-target.c > @@ -1129,6 +1129,12 @@ static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond, > tcg_out32 (s, XOR | SAB (arg1, 0, arg2)); > } > > + /* Make sure and discard the high 32-bits of the input. */ > + if (type == TCG_TYPE_I32) { > + tcg_out32(s, EXTSW | RA(TCG_REG_R0) | RS(arg)); > + arg = TCG_REG_R0; > + } > + > if (arg == arg1 && arg1 == arg0) { > tcg_out32(s, ADDIC | TAI(0, arg, -1)); > tcg_out32(s, SUBFE | TAB(arg0, 0, arg)); Given that it adds one more instruction, I do wonder if we still need a different implementation than the EQ one and XORI 1. The latter is what GCC choses. That said the fix is correct so: Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net