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From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: av1474@comtv.ru, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 33/33] tcg-ppc64: Handle deposit of zero
Date: Mon, 15 Apr 2013 10:14:03 +0200	[thread overview]
Message-ID: <20130415081403.GA11917@ohm.aurel32.net> (raw)
In-Reply-To: <1365116186-19382-34-git-send-email-rth@twiddle.net>

On Thu, Apr 04, 2013 at 05:56:26PM -0500, Richard Henderson wrote:
> The TCG optimizer does great work when inserting constants, being able
> to fold the open-coded deposit expansion to just an AND or an OR.  Avoid
> a bit the regression caused by having the deposit opcode by expanding
> deposit of zero as an AND.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/ppc64/tcg-target.c | 22 ++++++++++++++++------
>  1 file changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 9583cf9..772f4ac 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1928,12 +1928,22 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>          break;
>  
>      case INDEX_op_deposit_i32:
> -        tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
> -                    32 - args[3] - args[4], 31 - args[3]);
> +        if (const_args[2]) {
> +            uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
> +            tcg_out_andi32(s, args[0], args[0], ~mask);
> +        } else {
> +            tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
> +                        32 - args[3] - args[4], 31 - args[3]);
> +        }
>          break;
>      case INDEX_op_deposit_i64:
> -        tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
> -                    64 - args[3] - args[4]);
> +        if (const_args[2]) {
> +            uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
> +            tcg_out_andi64(s, args[0], args[0], ~mask);
> +        } else {
> +            tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
> +                        64 - args[3] - args[4]);
> +        }
>          break;
>  
>      case INDEX_op_movcond_i32:
> @@ -2136,8 +2146,8 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_bswap32_i64, { "r", "r" } },
>      { INDEX_op_bswap64_i64, { "r", "r" } },
>  
> -    { INDEX_op_deposit_i32, { "r", "0", "r" } },
> -    { INDEX_op_deposit_i64, { "r", "0", "r" } },
> +    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
> +    { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
>  
>      { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } },
>      { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },

I first thought this should go into the middle end, but OTOH it will
de-optimize some TCG targets which have a zero register like MIPS.

In the long term I think we should allow the middle end to query the
backend for constraints, and take the right decision (which would also
improve constant propagation on some hosts). In the meantime it looks
like the right thing to do, so:

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

  reply	other threads:[~2013-04-15  8:14 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-04 22:55 [Qemu-devel] [PATCH v4 00/33] Modernize tcg/ppc64 Richard Henderson
2013-04-04 22:55 ` [Qemu-devel] [PATCH v4 01/33] disas: Disassemble all ppc insns for the host Richard Henderson
2013-04-04 22:55 ` [Qemu-devel] [PATCH v4 02/33] tcg-ppc64: Use TCGReg everywhere Richard Henderson
2013-04-04 22:55 ` [Qemu-devel] [PATCH v4 03/33] tcg-ppc64: Introduce and use tcg_out_rlw Richard Henderson
2013-04-04 22:55 ` [Qemu-devel] [PATCH v4 04/33] tcg-ppc64: Introduce and use tcg_out_ext32u Richard Henderson
2013-04-04 22:55 ` [Qemu-devel] [PATCH v4 05/33] tcg-ppc64: Introduce and use tcg_out_shli64 Richard Henderson
2013-04-04 22:55 ` [Qemu-devel] [PATCH v4 06/33] tcg-ppc64: Introduce and use tcg_out_shri64 Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 07/33] tcg-ppc64: Introduce and use TAI and SAI Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 08/33] tcg-ppc64: Fix setcond_i32 Richard Henderson
2013-04-15  7:54   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 09/33] tcg-ppc64: Cleanup tcg_out_movi Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 10/33] tcg-ppc64: Rearrange integer constant constraints Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 11/33] tcg-ppc64: Improve constant add and sub ops Richard Henderson
2013-04-15  7:54   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 12/33] tcg-ppc64: Allow constant first argument to sub Richard Henderson
2013-04-15  7:59   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 13/33] tcg-ppc64: Tidy or and xor patterns Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 14/33] tcg-ppc64: Improve and_i32 with constant Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 15/33] tcg-ppc64: Improve and_i64 " Richard Henderson
2013-04-13 12:24   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 16/33] tcg-ppc64: Use automatic implementation of ext32u_i64 Richard Henderson
2013-04-13 12:25   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection Richard Henderson
2013-04-13 12:25   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 18/33] tcg-ppc64: Implement rotates Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 19/33] tcg-ppc64: Implement bswap16 and bswap32 Richard Henderson
2013-04-15  7:59   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 20/33] tcg-ppc64: Implement bswap64 Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 21/33] tcg-ppc64: Implement compound logicals Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 22/33] tcg-ppc64: Handle constant inputs for some " Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 23/33] tcg-ppc64: Implement deposit Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 24/33] tcg-ppc64: Use I constraint for mul Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 25/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp Richard Henderson
2013-04-15  8:01   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 26/33] tcg-ppc64: Use TCGType throughout compares Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 27/33] tcg-ppc64: Use MFOCRF instead of MFCR Richard Henderson
2013-04-15  8:02   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 28/33] tcg-ppc64: Use ISEL for setcond Richard Henderson
2013-04-15  8:13   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 29/33] tcg-ppc64: Implement movcond Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 30/33] tcg-ppc64: Use getauxval for ISA detection Richard Henderson
2013-04-05 16:59   ` Richard Henderson
2013-04-15  8:13   ` Aurelien Jarno
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 31/33] tcg-ppc64: Implement add2/sub2_i64 Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 32/33] tcg-ppc64: Implement mulu2/muls2_i64 Richard Henderson
2013-04-04 22:56 ` [Qemu-devel] [PATCH v4 33/33] tcg-ppc64: Handle deposit of zero Richard Henderson
2013-04-15  8:14   ` Aurelien Jarno [this message]
2013-04-13 12:24 ` [Qemu-devel] [PATCH v4 00/33] Modernize tcg/ppc64 Aurelien Jarno

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