From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URkLl-0001E8-B6 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 10:25:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URkLg-0003hp-Eg for qemu-devel@nongnu.org; Mon, 15 Apr 2013 10:25:41 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:50913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URkLg-0003hY-86 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 10:25:36 -0400 Date: Mon, 15 Apr 2013 16:25:26 +0200 From: Aurelien Jarno Message-ID: <20130415142526.GV5000@ohm.aurel32.net> References: <1365781072-24979-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1365781072-24979-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH] fpu: Correct edgecase in float64_muladd List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Blue Swirl , Anthony Liguori , qemu-devel@nongnu.org, patches@linaro.org On Fri, Apr 12, 2013 at 04:37:52PM +0100, Peter Maydell wrote: > In handling float64_muladd, if we end up doing a subtraction of the > product and c, and the 128 bit result of this subtraction happens to > have its most significant bit in bit 63, we weren't handling this > correctly when attempting to normalize to put the most significant > bit into bit 126. We would end up doing a right shift by a negative > number (undefined behaviour in C) so at best we would return an > incorrect result to the guest. MSB in bit 63 has to be handled as a > special case separately from MSB in 0..62 and MSB in 63..126. (MSB > in 127 is not possible.) > > Signed-off-by: Peter Maydell > --- > Specific test vector which triggers this: > a = 3fffffffffe00000 b = 3fffffffffe00000 c = c00fffffffc00000 > > Also tested with my usual set of random test vectors. > > fpu/softfloat.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/fpu/softfloat.c b/fpu/softfloat.c > index 83ccc4b..7ba51b6 100644 > --- a/fpu/softfloat.c > +++ b/fpu/softfloat.c > @@ -3898,9 +3898,15 @@ float64 float64_muladd(float64 a, float64 b, float64 c, int flags STATUS_PARAM) > } > zExp -= shiftcount; > } else { > - shiftcount = countLeadingZeros64(zSig1) - 1; > - zSig0 = zSig1 << shiftcount; > - zExp -= (shiftcount + 64); > + shiftcount = countLeadingZeros64(zSig1); > + if (shiftcount == 0) { > + zSig0 = (zSig1 >> 1) | (zSig1 & 1); > + zExp -= 63; > + } else { > + shiftcount--; > + zSig0 = zSig1 << shiftcount; > + zExp -= (shiftcount + 64); > + } > } > return roundAndPackFloat64(zSign, zExp, zSig0 STATUS_VAR); > } Thanks, applied. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net