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Date: Mon, 15 Apr 2013 17:42:12 +0200
From: Aurelien Jarno <aurelien@aurel32.net>
Message-ID: <20130415154212.GW5000@ohm.aurel32.net>
References: <002401ce39a6$be6900f0$3b3b02d0$@Dovgaluk@ispras.ru>
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In-Reply-To: <002401ce39a6$be6900f0$3b3b02d0$@Dovgaluk@ispras.ru>
Subject: Re: [Qemu-devel] [PATCH] i386 ROR r8/r16 instruction fix
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To: Pavel Dovgaluk <Pavel.Dovgaluk@ispras.ru>
Cc: 'qemu-devel' <qemu-devel@nongnu.org>, Richard Henderson <rth@twiddle.net>

On Mon, Apr 15, 2013 at 10:59:15AM +0400, Pavel Dovgaluk wrote:
> Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the TB.
> 
> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@gmail.com>
> ---
>  target-i386/translate.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 233f24f..40f891d 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -1775,6 +1775,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
>      if (is_right) {
>          tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
>          tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
> +        tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
>      } else {
>          tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
>          tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);

This looks correct to me, though I haven't tested.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

The corresponding code seems to have been changed in commit
34d80a55ff8517fd37bcfea5063b9797e2bd9132. I therefore added
Richard in Cc: for him to comment.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net