From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTGS1-0001Gm-2G for qemu-devel@nongnu.org; Fri, 19 Apr 2013 14:54:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UTGRz-0005Yh-HB for qemu-devel@nongnu.org; Fri, 19 Apr 2013 14:54:25 -0400 Date: Fri, 19 Apr 2013 20:54:12 +0200 From: Aurelien Jarno Message-ID: <20130419185412.GF17205@hall.aurel32.net> References: <1365857251-28173-1-git-send-email-aurelien@aurel32.net> <1365857251-28173-10-git-send-email-aurelien@aurel32.net> <516EB124.2010701@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <516EB124.2010701@twiddle.net> Sender: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 09/10] target-ppc: emulate store doubleword pair instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Alexander Graf On Wed, Apr 17, 2013 at 04:26:44PM +0200, Richard Henderson wrote: > On 2013-04-13 14:47, Aurelien Jarno wrote: > >+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); > > Actually, for both this and ldfp, don't you need to check for > odd rD and raise sigill or whatever? > This indeed needs to be checked, but it's already done using the invalid bits: +GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), +GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), The 2 there correspond to the last bit of the register pair, which thus should be 0, otherwise the instruction generates an invalid exception. I'll add that to the description when doing the respin. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net