From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUDTH-0006Jv-3O for qemu-devel@nongnu.org; Mon, 22 Apr 2013 05:55:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUDTF-0002yk-QE for qemu-devel@nongnu.org; Mon, 22 Apr 2013 05:55:39 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:57107) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUDTF-0002ya-Ix for qemu-devel@nongnu.org; Mon, 22 Apr 2013 05:55:37 -0400 Date: Mon, 22 Apr 2013 11:55:31 +0200 From: Aurelien Jarno Message-ID: <20130422095531.GN16361@ohm.aurel32.net> References: <1364769305-3687-1-git-send-email-rth@twiddle.net> <1364769305-3687-18-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1364769305-3687-18-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH v5 17/19] tcg-arm: Use movi32 + blx for calls on v7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Sun, Mar 31, 2013 at 03:35:03PM -0700, Richard Henderson wrote: > Work better with branch predition when we have movw+movt, > as the size of the code is the same. Perhaps re-evaluate > when we have a proper constant pool. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c > index 35598a8..ff6dc90 100644 > --- a/tcg/arm/tcg-target.c > +++ b/tcg/arm/tcg-target.c > @@ -1019,6 +1019,9 @@ static inline void tcg_out_call(TCGContext *s, uint32_t addr) > } else { > tcg_out_bl(s, COND_AL, val); > } > + } else if (use_armv7_instructions) { > + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addr); > + tcg_out_blx(s, COND_AL, TCG_REG_TMP); > } else { > tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4); > tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net