From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVhNI-0007cK-C3 for qemu-devel@nongnu.org; Fri, 26 Apr 2013 08:03:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UVhNC-0008F4-4a for qemu-devel@nongnu.org; Fri, 26 Apr 2013 08:03:36 -0400 Date: Fri, 26 Apr 2013 21:58:23 +1000 From: David Gibson Message-ID: <20130426115823.GC4360@truffula.fritz.box> References: <1366957045-21133-1-git-send-email-Bharat.Bhushan@freescale.com> <3D84FDF7-EBD3-4FBC-9E9B-1DE56CD76546@suse.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="WplhKdTI2c8ulnbP" Content-Disposition: inline In-Reply-To: <3D84FDF7-EBD3-4FBC-9E9B-1DE56CD76546@suse.de> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH] ppc: initialize GPRs as per epapr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Stuart Yoder , qemu-devel@nongnu.org, Bharat Bhushan , qemu-ppc@nongnu.org, Bharat Bhushan , scottwood@freescale.com --WplhKdTI2c8ulnbP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Apr 26, 2013 at 08:21:24AM +0200, Alexander Graf wrote: >=20 > On 26.04.2013, at 08:17, Bharat Bhushan wrote: >=20 > > ePAPR defines the initial values of cpu registers. This patch initialize > > the GPRs as per ePAPR specification. > >=20 > > This resolves the issue of guest reboot/reset (guest hang on reboot). >=20 > Why does it hang only on reboot, not on initial bootup? >=20 > >=20 > > Signed-off-by: Bharat Bhushan > > Signed-off-by: Stuart Yoder > > --- > > hw/ppc/e500.c | 7 +++++++ > > 1 files changed, 7 insertions(+), 0 deletions(-) > >=20 > > diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c > > index c1bdb6b..a47f976 100644 > > --- a/hw/ppc/e500.c > > +++ b/hw/ppc/e500.c > > @@ -37,6 +37,7 @@ > > #include "qemu/host-utils.h" > > #include "hw/pci-host/ppce500.h" > >=20 > > +#define EPAPR_MAGIC (0x45504150) > > #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" > > #define UIMAGE_LOAD_BASE 0 > > #define DTC_LOAD_PAD 0x1800000 > > @@ -444,6 +445,12 @@ static void ppce500_cpu_reset(void *opaque) >=20 > Does ePAPR mention anything wrt GPR state of secondary CPUs? Yes and no. The entry point state for secondary CPUs depends on the "enable-method" used to start the CPU. The spin-table enable method defined in ePAPR gives some information on GPR state, although the constraints are much weaker than for the boot cpu. Platform specific enable-methods would have to define their own entry point requirements. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --WplhKdTI2c8ulnbP Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEARECAAYFAlF6a98ACgkQaILKxv3ab8ZHcwCfXLSKMS2WDB7TLNheh5PzsWwA nH0AnRnE9Ttzsm3EnAOqVfBsh1L4QKE6 =Bqut -----END PGP SIGNATURE----- --WplhKdTI2c8ulnbP--