From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UYHDb-0002Zj-P8 for qemu-devel@nongnu.org; Fri, 03 May 2013 10:44:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UYHDW-00070J-BA for qemu-devel@nongnu.org; Fri, 03 May 2013 10:44:15 -0400 Date: Sat, 4 May 2013 00:26:49 +1000 From: David Gibson Message-ID: <20130503142649.GX13041@truffula.fritz.box> References: <1367545092-19980-1-git-send-email-david@gibson.dropbear.id.au> <1367545092-19980-3-git-send-email-david@gibson.dropbear.id.au> <51839F98.8070105@suse.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="2MC+DK0smzICZJ/6" Content-Disposition: inline In-Reply-To: <51839F98.8070105@suse.de> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/8] target-ppc: Convert ppc cpu savevm to VMStateDescription List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?iso-8859-1?Q?F=E4rber?= Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, quintela@redhat.com --2MC+DK0smzICZJ/6 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 03, 2013 at 01:29:28PM +0200, Andreas F=E4rber wrote: > Am 03.05.2013 03:38, schrieb David Gibson: > > The savevm code for the powerpc cpu emulation is currently based around > > the old register_savevm() rather than register_vmstate() method. It's = also > > rather broken, missing some important state on some CPU models. > >=20 > > This patch completely rewrites the savevm for target-ppc, using the new > > VMStateDescription approach. Exactly what needs to be saved in what > > configurations has been more carefully examined, too. This introduces a > > new version (5) of the cpu save format. The old load function is retai= ned > > to support version 4 images. > >=20 > > Signed-off-by: David Gibson > > --- > > target-ppc/cpu.h | 9 +- > > target-ppc/machine.c | 542 ++++++++++++++++++++++++++++++++++++++++++= -------- > > 2 files changed, 460 insertions(+), 91 deletions(-) > [...] > > diff --git a/target-ppc/machine.c b/target-ppc/machine.c > > index 2d10adb..594fe6a 100644 > > --- a/target-ppc/machine.c > > +++ b/target-ppc/machine.c > [...] > > +void cpu_save(QEMUFile *f, void *opaque) > > +{ > > + vmstate_save_state(f, &vmstate_cpu, opaque); > > + > > +} > > + > > +int cpu_load(QEMUFile *f, void *opaque, int version_id) > > +{ > > + return vmstate_load_state(f, &vmstate_cpu, opaque, version_id); > > +} >=20 > Please drop cpu_{save,load}() and use the VMStateDescription-based > registration mechanism cpu_class_set_vmsd() from PowerPCCPU's > instance_init in translate_init.c. > I'm pretty certain I CC'ed you on that series... Very likely. But I initially wrote this patch before that, and didn't notice the relevance of the update. Revised version below: =46rom 84125649c8b299e4c56c9c28abd5f0b5aafee40a Mon Sep 17 00:00:00 2001 =46rom: David Gibson Date: Fri, 22 Feb 2013 09:47:00 +1100 Subject: [PATCH] target-ppc: Convert ppc cpu savevm to VMStateDescription The savevm code for the powerpc cpu emulation is currently based around the old register_savevm() rather than register_vmstate() method. It's also rather broken, missing some important state on some CPU models. This patch completely rewrites the savevm for target-ppc, using the new VMStateDescription approach. Exactly what needs to be saved in what configurations has been more carefully examined, too. This introduces a new version (5) of the cpu save format. The old load function is retained to support version 4 images. Signed-off-by: David Gibson --- target-ppc/cpu-qom.h | 4 + target-ppc/cpu.h | 9 +- target-ppc/machine.c | 531 ++++++++++++++++++++++++++++++++++++---= ---- target-ppc/translate_init.c | 2 + 4 files changed, 454 insertions(+), 92 deletions(-) diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index eb03a00..2b96b04 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -102,4 +102,8 @@ PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); =20 void ppc_cpu_do_interrupt(CPUState *cpu); =20 +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_ppc_cpu; +#endif + #endif diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7cacb56..1809cb3 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -943,7 +943,7 @@ struct CPUPPCState { #if defined(TARGET_PPC64) /* PowerPC 64 SLB area */ ppc_slb_t slb[64]; - int slb_nr; + int32_t slb_nr; #endif /* segment registers */ hwaddr htab_base; @@ -952,11 +952,11 @@ struct CPUPPCState { /* externally stored hash table */ uint8_t *external_htab; /* BATs */ - int nb_BATs; + uint32_t nb_BATs; target_ulong DBAT[2][8]; target_ulong IBAT[2][8]; /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) = */ - int nb_tlb; /* Total number of TLB = */ + int32_t nb_tlb; /* Total number of TLB = */ int tlb_per_way; /* Speed-up helper: used to avoid divisions at run ti= me */ int nb_ways; /* Number of ways in the TLB set = */ int last_way; /* Last used way used to allocate TLB in a LRU way = */ @@ -973,6 +973,7 @@ struct CPUPPCState { /* Other registers */ /* Special purpose registers */ target_ulong spr[1024]; + uint32_t cr; /* Full CR value used during vmsave/load */ ppc_spr_t spr_cb[1024]; /* Altivec registers */ ppc_avr_t avr[32]; @@ -1171,8 +1172,6 @@ static inline CPUPPCState *cpu_init(const char *cpu_m= odel) #define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list =20 -#define CPU_SAVE_VERSION 4 - /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _user #define MMU_MODE1_SUFFIX _kernel diff --git a/target-ppc/machine.c b/target-ppc/machine.c index 2d10adb..b6be2a7 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -1,94 +1,9 @@ #include "hw/hw.h" #include "hw/boards.h" #include "sysemu/kvm.h" +#include "helper_regs.h" =20 -void cpu_save(QEMUFile *f, void *opaque) -{ - CPUPPCState *env =3D (CPUPPCState *)opaque; - unsigned int i, j; - uint32_t fpscr; - target_ulong xer; - - for (i =3D 0; i < 32; i++) - qemu_put_betls(f, &env->gpr[i]); -#if !defined(TARGET_PPC64) - for (i =3D 0; i < 32; i++) - qemu_put_betls(f, &env->gprh[i]); -#endif - qemu_put_betls(f, &env->lr); - qemu_put_betls(f, &env->ctr); - for (i =3D 0; i < 8; i++) - qemu_put_be32s(f, &env->crf[i]); - xer =3D cpu_read_xer(env); - qemu_put_betls(f, &xer); - qemu_put_betls(f, &env->reserve_addr); - qemu_put_betls(f, &env->msr); - for (i =3D 0; i < 4; i++) - qemu_put_betls(f, &env->tgpr[i]); - for (i =3D 0; i < 32; i++) { - union { - float64 d; - uint64_t l; - } u; - u.d =3D env->fpr[i]; - qemu_put_be64(f, u.l); - } - fpscr =3D env->fpscr; - qemu_put_be32s(f, &fpscr); - qemu_put_sbe32s(f, &env->access_type); -#if defined(TARGET_PPC64) - qemu_put_betls(f, &env->spr[SPR_ASR]); - qemu_put_sbe32s(f, &env->slb_nr); -#endif - qemu_put_betls(f, &env->spr[SPR_SDR1]); - for (i =3D 0; i < 32; i++) - qemu_put_betls(f, &env->sr[i]); - for (i =3D 0; i < 2; i++) - for (j =3D 0; j < 8; j++) - qemu_put_betls(f, &env->DBAT[i][j]); - for (i =3D 0; i < 2; i++) - for (j =3D 0; j < 8; j++) - qemu_put_betls(f, &env->IBAT[i][j]); - qemu_put_sbe32s(f, &env->nb_tlb); - qemu_put_sbe32s(f, &env->tlb_per_way); - qemu_put_sbe32s(f, &env->nb_ways); - qemu_put_sbe32s(f, &env->last_way); - qemu_put_sbe32s(f, &env->id_tlbs); - qemu_put_sbe32s(f, &env->nb_pids); - if (env->tlb.tlb6) { - // XXX assumes 6xx - for (i =3D 0; i < env->nb_tlb; i++) { - qemu_put_betls(f, &env->tlb.tlb6[i].pte0); - qemu_put_betls(f, &env->tlb.tlb6[i].pte1); - qemu_put_betls(f, &env->tlb.tlb6[i].EPN); - } - } - for (i =3D 0; i < 4; i++) - qemu_put_betls(f, &env->pb[i]); - for (i =3D 0; i < 1024; i++) - qemu_put_betls(f, &env->spr[i]); - qemu_put_be32s(f, &env->vscr); - qemu_put_be64s(f, &env->spe_acc); - qemu_put_be32s(f, &env->spe_fscr); - qemu_put_betls(f, &env->msr_mask); - qemu_put_be32s(f, &env->flags); - qemu_put_sbe32s(f, &env->error_code); - qemu_put_be32s(f, &env->pending_interrupts); - qemu_put_be32s(f, &env->irq_input_state); - for (i =3D 0; i < POWERPC_EXCP_NB; i++) - qemu_put_betls(f, &env->excp_vectors[i]); - qemu_put_betls(f, &env->excp_prefix); - qemu_put_betls(f, &env->ivor_mask); - qemu_put_betls(f, &env->ivpr_mask); - qemu_put_betls(f, &env->hreset_vector); - qemu_put_betls(f, &env->nip); - qemu_put_betls(f, &env->hflags); - qemu_put_betls(f, &env->hflags_nmsr); - qemu_put_sbe32s(f, &env->mmu_idx); - qemu_put_sbe32(f, 0); -} - -int cpu_load(QEMUFile *f, void *opaque, int version_id) +static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) { CPUPPCState *env =3D (CPUPPCState *)opaque; unsigned int i, j; @@ -177,3 +92,445 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) =20 return 0; } + +static int get_avr(QEMUFile *f, void *pv, size_t size) +{ + ppc_avr_t *v =3D pv; + + v->u64[0] =3D qemu_get_be64(f); + v->u64[1] =3D qemu_get_be64(f); + + return 0; +} + +static void put_avr(QEMUFile *f, void *pv, size_t size) +{ + ppc_avr_t *v =3D pv; + + qemu_put_be64(f, v->u64[0]); + qemu_put_be64(f, v->u64[1]); +} + +const VMStateInfo vmstate_info_avr =3D { + .name =3D "avr", + .get =3D get_avr, + .put =3D put_avr, +}; + +#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) + +#define VMSTATE_AVR_ARRAY(_f, _s, _n) \ + VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) + +static void cpu_pre_save(void *opaque) +{ + CPUPPCState *env =3D opaque; + int i; + + env->spr[SPR_LR] =3D env->lr; + env->spr[SPR_CTR] =3D env->ctr; + env->spr[SPR_XER] =3D env->xer; +#if defined(TARGET_PPC64) + env->spr[SPR_CFAR] =3D env->cfar; +#endif + env->spr[SPR_BOOKE_SPEFSCR] =3D env->spe_fscr; + + env->cr =3D 0; + for (i =3D 0; i < 8; i++) { + env->cr =3D (env->cr << 4) | (env->crf[i] & 0xf); + } + + for (i =3D 0; (i < 4) && (i < env->nb_BATs); i++) { + env->spr[SPR_DBAT0U + 2*i] =3D env->DBAT[0][i]; + env->spr[SPR_DBAT0U + 2*i + 1] =3D env->DBAT[1][i]; + env->spr[SPR_IBAT0U + 2*i] =3D env->IBAT[0][i]; + env->spr[SPR_IBAT0U + 2*i + 1] =3D env->IBAT[1][i]; + } + for (i =3D 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { + env->spr[SPR_DBAT4U + 2*i] =3D env->DBAT[0][i+4]; + env->spr[SPR_DBAT4U + 2*i + 1] =3D env->DBAT[1][i+4]; + env->spr[SPR_IBAT4U + 2*i] =3D env->IBAT[0][i+4]; + env->spr[SPR_IBAT4U + 2*i + 1] =3D env->IBAT[1][i+4]; + } +} + +static int cpu_post_load(void *opaque, int version_id) +{ + CPUPPCState *env =3D opaque; + int i; + + env->lr =3D env->spr[SPR_LR]; + env->ctr =3D env->spr[SPR_CTR]; + env->xer =3D env->spr[SPR_XER]; +#if defined(TARGET_PPC64) + env->cfar =3D env->spr[SPR_CFAR]; +#endif + env->spe_fscr =3D env->spr[SPR_BOOKE_SPEFSCR]; + + for (i =3D 0; i < 8; i++) { + env->crf[i] =3D env->cr >> (4*(7-i)) & 0xf; + } + + for (i =3D 0; (i < 4) && (i < env->nb_BATs); i++) { + env->DBAT[0][i] =3D env->spr[SPR_DBAT0U + 2*i]; + env->DBAT[1][i] =3D env->spr[SPR_DBAT0U + 2*i + 1]; + env->IBAT[0][i] =3D env->spr[SPR_IBAT0U + 2*i]; + env->IBAT[1][i] =3D env->spr[SPR_IBAT0U + 2*i + 1]; + } + for (i =3D 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { + env->DBAT[0][i+4] =3D env->spr[SPR_DBAT4U + 2*i]; + env->DBAT[1][i+4] =3D env->spr[SPR_DBAT4U + 2*i + 1]; + env->IBAT[0][i+4] =3D env->spr[SPR_IBAT4U + 2*i]; + env->IBAT[1][i+4] =3D env->spr[SPR_IBAT4U + 2*i + 1]; + } + + /* Restore htab_base and htab_mask variables */ + ppc_store_sdr1(env, env->spr[SPR_SDR1]); + + hreg_compute_hflags(env); + hreg_compute_mem_idx(env); + + return 0; +} + +static bool fpu_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + return (env->insns_flags & PPC_FLOAT); +} + +static const VMStateDescription vmstate_fpu =3D { + .name =3D "cpu/fpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_FLOAT64_ARRAY(fpr, CPUPPCState, 32), + VMSTATE_UINTTL(fpscr, CPUPPCState), + VMSTATE_END_OF_LIST() + }, +}; + +static bool altivec_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + return (env->insns_flags & PPC_ALTIVEC); +} + +static const VMStateDescription vmstate_altivec =3D { + .name =3D "cpu/altivec", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_AVR_ARRAY(avr, CPUPPCState, 32), + VMSTATE_UINT32(vscr, CPUPPCState), + VMSTATE_END_OF_LIST() + }, +}; + +static bool vsx_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + return (env->insns_flags2 & PPC2_VSX); +} + +static const VMStateDescription vmstate_vsx =3D { + .name =3D "cpu/vsx", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_UINT64_ARRAY(vsr, CPUPPCState, 32), + VMSTATE_END_OF_LIST() + }, +}; + +static bool sr_needed(void *opaque) +{ +#ifdef TARGET_PPC64 + CPUPPCState *env =3D opaque; + + return !(env->mmu_model & POWERPC_MMU_64); +#else + return true; +#endif +} + +static const VMStateDescription vmstate_sr =3D { + .name =3D "cpu/sr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_UINTTL_ARRAY(sr, CPUPPCState, 32), + VMSTATE_END_OF_LIST() + }, +}; + +#ifdef TARGET_PPC64 +static int get_slbe(QEMUFile *f, void *pv, size_t size) +{ + ppc_slb_t *v =3D pv; + + v->esid =3D qemu_get_be64(f); + v->vsid =3D qemu_get_be64(f); + + return 0; +} + +static void put_slbe(QEMUFile *f, void *pv, size_t size) +{ + ppc_slb_t *v =3D pv; + + qemu_put_be64(f, v->esid); + qemu_put_be64(f, v->vsid); +} + +const VMStateInfo vmstate_info_slbe =3D { + .name =3D "slbe", + .get =3D get_slbe, + .put =3D put_slbe, +}; + +#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) + +#define VMSTATE_SLB_ARRAY(_f, _s, _n) \ + VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) + +static bool slb_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + /* We don't support any of the old segment table based 64-bit CPUs */ + return (env->mmu_model & POWERPC_MMU_64); +} + +static const VMStateDescription vmstate_slb =3D { + .name =3D "cpu/slb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_INT32_EQUAL(slb_nr, CPUPPCState), + VMSTATE_SLB_ARRAY(slb, CPUPPCState, 64), + VMSTATE_END_OF_LIST() + } +}; +#endif /* TARGET_PPC64 */ + +static const VMStateDescription vmstate_tlb6xx_entry =3D { + .name =3D "cpu/tlb6xx_entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), + VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), + VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), + VMSTATE_END_OF_LIST() + }, +}; + +static bool tlb6xx_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + return env->nb_tlb && (env->tlb_type =3D=3D TLB_6XX); +} + +static const VMStateDescription vmstate_tlb6xx =3D { + .name =3D "cpu/tlb6xx", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_INT32_EQUAL(nb_tlb, CPUPPCState), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(tlb.tlb6, CPUPPCState, nb_tlb, + vmstate_tlb6xx_entry, + ppc6xx_tlb_t), + VMSTATE_UINTTL_ARRAY(tgpr, CPUPPCState, 4), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_tlbemb_entry =3D { + .name =3D "cpu/tlbemb_entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_UINT64(RPN, ppcemb_tlb_t), + VMSTATE_UINTTL(EPN, ppcemb_tlb_t), + VMSTATE_UINTTL(PID, ppcemb_tlb_t), + VMSTATE_UINTTL(size, ppcemb_tlb_t), + VMSTATE_UINT32(prot, ppcemb_tlb_t), + VMSTATE_UINT32(attr, ppcemb_tlb_t), + VMSTATE_END_OF_LIST() + }, +}; + +static bool tlbemb_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + return env->nb_tlb && (env->tlb_type =3D=3D TLB_EMB); +} + +static bool pbr403_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + uint32_t pvr =3D env->spr[SPR_PVR]; + + return (pvr & 0xffff0000) =3D=3D 0x00200000; +} + +static const VMStateDescription vmstate_pbr403 =3D { + .name =3D "cpu/pbr403", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_UINTTL_ARRAY(pb, CPUPPCState, 4), + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription vmstate_tlbemb =3D { + .name =3D "cpu/tlb6xx", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_INT32_EQUAL(nb_tlb, CPUPPCState), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(tlb.tlbe, CPUPPCState, nb_tlb, + vmstate_tlbemb_entry, + ppcemb_tlb_t), + /* 403 protection registers */ + VMSTATE_END_OF_LIST() + }, + .subsections =3D (VMStateSubsection []) { + { + .vmsd =3D &vmstate_pbr403, + .needed =3D pbr403_needed, + } , { + /* empty */ + } + } +}; + +static const VMStateDescription vmstate_tlbmas_entry =3D { + .name =3D "cpu/tlbmas_entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_UINT32(mas8, ppcmas_tlb_t), + VMSTATE_UINT32(mas1, ppcmas_tlb_t), + VMSTATE_UINT64(mas2, ppcmas_tlb_t), + VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), + VMSTATE_END_OF_LIST() + }, +}; + +static bool tlbmas_needed(void *opaque) +{ + CPUPPCState *env =3D opaque; + + return env->nb_tlb && (env->tlb_type =3D=3D TLB_MAS); +} + +static const VMStateDescription vmstate_tlbmas =3D { + .name =3D "cpu/tlbmas", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField []) { + VMSTATE_INT32_EQUAL(nb_tlb, CPUPPCState), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(tlb.tlbm, CPUPPCState, nb_tlb, + vmstate_tlbmas_entry, + ppcmas_tlb_t), + VMSTATE_END_OF_LIST() + } +}; + +const VMStateDescription vmstate_ppc_cpu =3D { + .name =3D "cpu", + .version_id =3D 5, + .minimum_version_id =3D 5, + .minimum_version_id_old =3D 4, + .load_state_old =3D cpu_load_old, + .pre_save =3D cpu_pre_save, + .post_load =3D cpu_post_load, + .fields =3D (VMStateField []) { + /* Verify we haven't changed the pvr */ + VMSTATE_UINTTL_EQUAL(spr[SPR_PVR], CPUPPCState), + + /* User mode architected state */ + VMSTATE_UINTTL_ARRAY(gpr, CPUPPCState, 32), +#if !defined(TARGET_PPC64) + VMSTATE_UINTTL_ARRAY(gprh, CPUPPCState, 32), +#endif + VMSTATE_UINT32(cr, CPUPPCState), + VMSTATE_UINTTL(nip, CPUPPCState), + + /* SPRs */ + VMSTATE_UINTTL_ARRAY(spr, CPUPPCState, 1024), + VMSTATE_UINT64(spe_acc, CPUPPCState), + + /* Reservation */ + VMSTATE_UINTTL(reserve_addr, CPUPPCState), + + /* Supervisor mode architected state */ + VMSTATE_UINTTL(msr, CPUPPCState), + + /* Internal state */ + VMSTATE_UINTTL(hflags_nmsr, CPUPPCState), + /* FIXME: access_type? */ + + /* Sanity checking */ + VMSTATE_UINTTL_EQUAL(msr_mask, CPUPPCState), + VMSTATE_UINT64_EQUAL(insns_flags, CPUPPCState), + VMSTATE_UINT64_EQUAL(insns_flags2, CPUPPCState), + VMSTATE_UINT32_EQUAL(nb_BATs, CPUPPCState), + VMSTATE_END_OF_LIST() + }, + .subsections =3D (VMStateSubsection []) { + { + .vmsd =3D &vmstate_fpu, + .needed =3D fpu_needed, + } , { + .vmsd =3D &vmstate_altivec, + .needed =3D altivec_needed, + } , { + .vmsd =3D &vmstate_vsx, + .needed =3D vsx_needed, + } , { + .vmsd =3D &vmstate_sr, + .needed =3D sr_needed, + } , { +#ifdef TARGET_PPC64 + .vmsd =3D &vmstate_slb, + .needed =3D slb_needed, + } , { +#endif /* TARGET_PPC64 */ + .vmsd =3D &vmstate_tlb6xx, + .needed =3D tlb6xx_needed, + } , { + .vmsd =3D &vmstate_tlbemb, + .needed =3D tlbemb_needed, + } , { + .vmsd =3D &vmstate_tlbmas, + .needed =3D tlbmas_needed, + } , { + /* FIXME: DCRs? */ + /* FIXME: timebase? */ + /* empty */ + } + } +}; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 6feb62a..df84f1b 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8305,6 +8305,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D ppc_cpu_class_by_name; cc->do_interrupt =3D ppc_cpu_do_interrupt; + + cpu_class_set_vmsd(cc, &vmstate_ppc_cpu); } =20 static const TypeInfo ppc_cpu_type_info =3D { --=20 1.7.10.4 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --2MC+DK0smzICZJ/6 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEARECAAYFAlGDySkACgkQaILKxv3ab8ZZwwCeLcFeRy6zw3WLbzxuN7Zp+mLU zt0AnjIU/ha30fv1f1Mblc/YPyPXJAC2 =NZBp -----END PGP SIGNATURE----- --2MC+DK0smzICZJ/6--