* [Qemu-devel] [PATCH] PPC: Fix cmp on 32bit only targets @ 2013-05-08 10:06 Alexander Graf 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Add 32bit instruction flag Alexander Graf 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops Alexander Graf 0 siblings, 2 replies; 8+ messages in thread From: Alexander Graf @ 2013-05-08 10:06 UTC (permalink / raw) To: qemu-ppc; +Cc: Richard Henderson, qemu-devel, Torbjorn Granlund When running 32bit cmp instructions on a TARGET_PPC without 64bit support, we generate incorrect comparisons. This patch set fixes this issue. Alex Alexander Graf (2): PPC: Add 32bit instruction flag PPC: Introduce 32bit only cmp ops target-ppc/cpu.h | 5 ++- target-ppc/translate.c | 48 +++++++++++++++++++---- target-ppc/translate_init.c | 88 +++++++++++++++++++++--------------------- 3 files changed, 88 insertions(+), 53 deletions(-) ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH] PPC: Add 32bit instruction flag 2013-05-08 10:06 [Qemu-devel] [PATCH] PPC: Fix cmp on 32bit only targets Alexander Graf @ 2013-05-08 10:06 ` Alexander Graf 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops Alexander Graf 1 sibling, 0 replies; 8+ messages in thread From: Alexander Graf @ 2013-05-08 10:06 UTC (permalink / raw) To: qemu-ppc; +Cc: Richard Henderson, qemu-devel, Torbjorn Granlund Some instructions behave differently depending on whether the CPU is 64bit capable or not, regardless of the mode the CPU is in. Add a new instruction flag that indicates that we're running on a CPU that can not execute 64bit code. Signed-off-by: Alexander Graf <agraf@suse.de> --- target-ppc/cpu.h | 5 ++- target-ppc/translate_init.c | 88 +++++++++++++++++++++--------------------- 2 files changed, 48 insertions(+), 45 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index aa1d013..09a28e1 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1875,8 +1875,11 @@ enum { PPC2_DBRX = 0x0000000000000010ULL, /* Book I 2.05 PowerPC specification */ PPC2_ISA205 = 0x0000000000000020ULL, + /* 32bit instructions (!PPC_64B && PPC_INTEGER) */ + PPC2_32B = 0x0000000000000040ULL, -#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205) +#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205 \ + | PPC2_32B) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 021a31e..dece4c5 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -3147,7 +3147,7 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data) PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x00000000000FD201ULL; pcc->mmu_model = POWERPC_MMU_REAL; pcc->excp_model = POWERPC_EXCP_40x; @@ -3195,7 +3195,7 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x00000000001FD231ULL; pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; pcc->excp_model = POWERPC_EXCP_40x; @@ -3237,7 +3237,7 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x00000000001FD631ULL; pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; pcc->excp_model = POWERPC_EXCP_40x; @@ -3285,7 +3285,7 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x00000000001FD231ULL; pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; pcc->excp_model = POWERPC_EXCP_40x; @@ -3325,7 +3325,7 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data) PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000007D00DULL; pcc->mmu_model = POWERPC_MMU_REAL; pcc->excp_model = POWERPC_EXCP_40x; @@ -3385,7 +3385,7 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000007D00DULL; pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; pcc->excp_model = POWERPC_EXCP_40x; @@ -3444,7 +3444,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006E630ULL; pcc->mmu_model = POWERPC_MMU_SOFT_4xx; pcc->excp_model = POWERPC_EXCP_40x; @@ -3538,7 +3538,7 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -3611,7 +3611,7 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -3684,7 +3684,7 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -3775,7 +3775,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -3872,7 +3872,7 @@ POWERPC_FAMILY(460)(ObjectClass *oc, void *data) PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -3972,7 +3972,7 @@ POWERPC_FAMILY(460F)(ObjectClass *oc, void *data) PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -4006,7 +4006,7 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | PPC_MFTB; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000001FF43ULL; pcc->mmu_model = POWERPC_MMU_REAL; pcc->excp_model = POWERPC_EXCP_603; @@ -4039,7 +4039,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_MFTB; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000001F673ULL; pcc->mmu_model = POWERPC_MMU_MPC8xx; pcc->excp_model = POWERPC_EXCP_603; @@ -4106,7 +4106,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000006FFF2ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_G2; @@ -4198,7 +4198,7 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000007FFF3ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_G2; @@ -4339,7 +4339,7 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_BOOKE; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000606FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE206; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -4398,7 +4398,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000007FFF3ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_603; @@ -4636,7 +4636,7 @@ POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; - pcc->insns_flags2 = PPC2_BOOKE206; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000606FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE206; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -4666,7 +4666,7 @@ POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; - pcc->insns_flags2 = PPC2_BOOKE206; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000606FF30ULL; pcc->mmu_model = POWERPC_MMU_BOOKE206; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -4698,7 +4698,7 @@ POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | PPC_WAIT | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; - pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; + pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_32B; pcc->msr_mask = 0x000000001402FB36ULL; pcc->mmu_model = POWERPC_MMU_BOOKE206; pcc->excp_model = POWERPC_EXCP_BOOKE; @@ -4810,7 +4810,7 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data) PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000000FD70ULL; pcc->mmu_model = POWERPC_MMU_601; #if defined(CONFIG_SOFTMMU) @@ -4847,7 +4847,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000000FD70ULL; pcc->mmu_model = POWERPC_MMU_601; #if defined(CONFIG_SOFTMMU) @@ -4900,7 +4900,7 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_602_SPEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x0000000000C7FF73ULL; /* XXX: 602 MMU is quite specific. Should add a special case */ pcc->mmu_model = POWERPC_MMU_SOFT_6xx; @@ -4953,7 +4953,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000007FF73ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_603; @@ -5010,7 +5010,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000007FF73ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_603E; @@ -5056,7 +5056,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5125,7 +5125,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5181,7 +5181,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5245,7 +5245,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5432,7 +5432,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5500,7 +5500,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5573,7 +5573,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5646,7 +5646,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5710,7 +5710,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_7x5; @@ -5782,7 +5782,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | PPC_SEGMENT | PPC_EXTERN; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000005FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_6xx; pcc->excp_model = POWERPC_EXCP_7x5; @@ -5841,7 +5841,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -5910,7 +5910,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_32B; #if defined(CONFIG_SOFTMMU) @@ -6005,7 +6005,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_74xx; pcc->excp_model = POWERPC_EXCP_74xx; @@ -6123,7 +6123,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_74xx; pcc->excp_model = POWERPC_EXCP_74xx; @@ -6244,7 +6244,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_74xx; pcc->excp_model = POWERPC_EXCP_74xx; @@ -6367,7 +6367,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_74xx; pcc->excp_model = POWERPC_EXCP_74xx; @@ -6514,7 +6514,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; + pcc->insns_flags2 = PPC2_32B; pcc->msr_mask = 0x000000000205FF77ULL; pcc->mmu_model = POWERPC_MMU_SOFT_74xx; pcc->excp_model = POWERPC_EXCP_74xx; -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops 2013-05-08 10:06 [Qemu-devel] [PATCH] PPC: Fix cmp on 32bit only targets Alexander Graf 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Add 32bit instruction flag Alexander Graf @ 2013-05-08 10:06 ` Alexander Graf 2013-05-08 10:29 ` Aurelien Jarno 1 sibling, 1 reply; 8+ messages in thread From: Alexander Graf @ 2013-05-08 10:06 UTC (permalink / raw) To: qemu-ppc; +Cc: Richard Henderson, qemu-devel, Torbjorn Granlund When running a 32bit target CPU with qemu-(system-)-ppc, NARROW_MODE is not set, so we never get to leverage the "32bit only" code path in the compare op handlers. Introduce new handlers based on the 32bit only flag. That way we can have 2 separate functions for 32bit mode and 64bit mode, which can handle NARROW_MODE. Reported-by: Torbjorn Granlund <tg@gmplib.org> Signed-off-by: Alexander Graf <agraf@suse.de> --- target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 40 insertions(+), 8 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a018616..002f9ae 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -675,7 +675,7 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) /* cmp */ static void gen_cmp(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { + if (!(ctx->opcode & 0x00200000)) { gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1, crfD(ctx->opcode)); } else { @@ -684,10 +684,17 @@ static void gen_cmp(DisasContext *ctx) } } +/* cmp 32bit only */ +static void gen_cmp32(DisasContext *ctx) +{ + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], + 1, crfD(ctx->opcode)); +} + /* cmpi */ static void gen_cmpi(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { + if (!(ctx->opcode & 0x00200000)) { gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1, crfD(ctx->opcode)); } else { @@ -696,10 +703,17 @@ static void gen_cmpi(DisasContext *ctx) } } +/* cmpi 32bit only */ +static void gen_cmpi32(DisasContext *ctx) +{ + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), + 1, crfD(ctx->opcode)); +} + /* cmpl */ static void gen_cmpl(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { + if (!(ctx->opcode & 0x00200000)) { gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 0, crfD(ctx->opcode)); } else { @@ -708,10 +722,17 @@ static void gen_cmpl(DisasContext *ctx) } } +/* cmpl 32bit only */ +static void gen_cmpl32(DisasContext *ctx) +{ + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], + 0, crfD(ctx->opcode)); +} + /* cmpli */ static void gen_cmpli(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { + if (!(ctx->opcode & 0x00200000)) { gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 0, crfD(ctx->opcode)); } else { @@ -720,6 +741,13 @@ static void gen_cmpli(DisasContext *ctx) } } +/* cmpli 32bit only */ +static void gen_cmpli32(DisasContext *ctx) +{ + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), + 0, crfD(ctx->opcode)); +} + /* isel (PowerPC 2.03 specification) */ static void gen_isel(DisasContext *ctx) { @@ -8638,10 +8666,14 @@ GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE static opcode_t opcodes[] = { GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), -GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), -GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), -GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), -GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), +GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_64B), +GEN_HANDLER_E(cmp32, 0x1F, 0x00, 0x00, 0x00400000, PPC_NONE, PPC2_32B), +GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_64B), +GEN_HANDLER_E(cmpi32, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_NONE, PPC2_32B), +GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_64B), +GEN_HANDLER_E(cmpl32, 0x1F, 0x00, 0x01, 0x00400000, PPC_NONE, PPC2_32B), +GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_64B), +GEN_HANDLER_E(cmpli32, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_NONE, PPC2_32B), GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops Alexander Graf @ 2013-05-08 10:29 ` Aurelien Jarno 2013-05-08 10:33 ` Alexander Graf 2013-05-08 10:34 ` Torbjorn Granlund 0 siblings, 2 replies; 8+ messages in thread From: Aurelien Jarno @ 2013-05-08 10:29 UTC (permalink / raw) To: Alexander Graf; +Cc: Torbjorn Granlund, qemu-ppc, qemu-devel, Richard Henderson On Wed, May 08, 2013 at 12:06:52PM +0200, Alexander Graf wrote: > When running a 32bit target CPU with qemu-(system-)-ppc, NARROW_MODE > is not set, so we never get to leverage the "32bit only" code path in > the compare op handlers. > > Introduce new handlers based on the 32bit only flag. That way we can > have 2 separate functions for 32bit mode and 64bit mode, which can > handle NARROW_MODE. > > Reported-by: Torbjorn Granlund <tg@gmplib.org> > Signed-off-by: Alexander Graf <agraf@suse.de> > --- > target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++-------- > 1 files changed, 40 insertions(+), 8 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index a018616..002f9ae 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -675,7 +675,7 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) > /* cmp */ > static void gen_cmp(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > + if (!(ctx->opcode & 0x00200000)) { > gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > 1, crfD(ctx->opcode)); > } else { > @@ -684,10 +684,17 @@ static void gen_cmp(DisasContext *ctx) > } > } > > +/* cmp 32bit only */ > +static void gen_cmp32(DisasContext *ctx) > +{ > + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > + 1, crfD(ctx->opcode)); > +} > + > /* cmpi */ > static void gen_cmpi(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > + if (!(ctx->opcode & 0x00200000)) { > gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), > 1, crfD(ctx->opcode)); > } else { > @@ -696,10 +703,17 @@ static void gen_cmpi(DisasContext *ctx) > } > } > > +/* cmpi 32bit only */ > +static void gen_cmpi32(DisasContext *ctx) > +{ > + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), > + 1, crfD(ctx->opcode)); > +} > + > /* cmpl */ > static void gen_cmpl(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > + if (!(ctx->opcode & 0x00200000)) { > gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > 0, crfD(ctx->opcode)); > } else { > @@ -708,10 +722,17 @@ static void gen_cmpl(DisasContext *ctx) > } > } > > +/* cmpl 32bit only */ > +static void gen_cmpl32(DisasContext *ctx) > +{ > + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > + 0, crfD(ctx->opcode)); > +} > + > /* cmpli */ > static void gen_cmpli(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > + if (!(ctx->opcode & 0x00200000)) { > gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), > 0, crfD(ctx->opcode)); > } else { > @@ -720,6 +741,13 @@ static void gen_cmpli(DisasContext *ctx) > } > } > > +/* cmpli 32bit only */ > +static void gen_cmpli32(DisasContext *ctx) > +{ > + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), > + 0, crfD(ctx->opcode)); > +} > + > /* isel (PowerPC 2.03 specification) */ > static void gen_isel(DisasContext *ctx) > { > @@ -8638,10 +8666,14 @@ GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE > > static opcode_t opcodes[] = { > GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), > -GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), > -GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), > -GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), > -GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), > +GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_64B), > +GEN_HANDLER_E(cmp32, 0x1F, 0x00, 0x00, 0x00400000, PPC_NONE, PPC2_32B), You have to declare the L bit as invalid, so that trying to execute a 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction exception. > +GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_64B), > +GEN_HANDLER_E(cmpi32, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_NONE, PPC2_32B), > +GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_64B), > +GEN_HANDLER_E(cmpl32, 0x1F, 0x00, 0x01, 0x00400000, PPC_NONE, PPC2_32B), > +GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_64B), > +GEN_HANDLER_E(cmpli32, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_NONE, PPC2_32B), > GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), > GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), > GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > -- > 1.6.0.2 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops 2013-05-08 10:29 ` Aurelien Jarno @ 2013-05-08 10:33 ` Alexander Graf 2013-05-08 10:34 ` Torbjorn Granlund 1 sibling, 0 replies; 8+ messages in thread From: Alexander Graf @ 2013-05-08 10:33 UTC (permalink / raw) To: Aurelien Jarno; +Cc: Torbjorn Granlund, qemu-ppc, qemu-devel, Richard Henderson On 08.05.2013, at 12:29, Aurelien Jarno wrote: > On Wed, May 08, 2013 at 12:06:52PM +0200, Alexander Graf wrote: >> When running a 32bit target CPU with qemu-(system-)-ppc, NARROW_MODE >> is not set, so we never get to leverage the "32bit only" code path in >> the compare op handlers. >> >> Introduce new handlers based on the 32bit only flag. That way we can >> have 2 separate functions for 32bit mode and 64bit mode, which can >> handle NARROW_MODE. >> >> Reported-by: Torbjorn Granlund <tg@gmplib.org> >> Signed-off-by: Alexander Graf <agraf@suse.de> >> --- >> target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++-------- >> 1 files changed, 40 insertions(+), 8 deletions(-) >> >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index a018616..002f9ae 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -675,7 +675,7 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) >> /* cmp */ >> static void gen_cmp(DisasContext *ctx) >> { >> - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { >> + if (!(ctx->opcode & 0x00200000)) { >> gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], >> 1, crfD(ctx->opcode)); >> } else { >> @@ -684,10 +684,17 @@ static void gen_cmp(DisasContext *ctx) >> } >> } >> >> +/* cmp 32bit only */ >> +static void gen_cmp32(DisasContext *ctx) >> +{ >> + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], >> + 1, crfD(ctx->opcode)); >> +} >> + >> /* cmpi */ >> static void gen_cmpi(DisasContext *ctx) >> { >> - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { >> + if (!(ctx->opcode & 0x00200000)) { >> gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), >> 1, crfD(ctx->opcode)); >> } else { >> @@ -696,10 +703,17 @@ static void gen_cmpi(DisasContext *ctx) >> } >> } >> >> +/* cmpi 32bit only */ >> +static void gen_cmpi32(DisasContext *ctx) >> +{ >> + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), >> + 1, crfD(ctx->opcode)); >> +} >> + >> /* cmpl */ >> static void gen_cmpl(DisasContext *ctx) >> { >> - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { >> + if (!(ctx->opcode & 0x00200000)) { >> gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], >> 0, crfD(ctx->opcode)); >> } else { >> @@ -708,10 +722,17 @@ static void gen_cmpl(DisasContext *ctx) >> } >> } >> >> +/* cmpl 32bit only */ >> +static void gen_cmpl32(DisasContext *ctx) >> +{ >> + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], >> + 0, crfD(ctx->opcode)); >> +} >> + >> /* cmpli */ >> static void gen_cmpli(DisasContext *ctx) >> { >> - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { >> + if (!(ctx->opcode & 0x00200000)) { >> gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), >> 0, crfD(ctx->opcode)); >> } else { >> @@ -720,6 +741,13 @@ static void gen_cmpli(DisasContext *ctx) >> } >> } >> >> +/* cmpli 32bit only */ >> +static void gen_cmpli32(DisasContext *ctx) >> +{ >> + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), >> + 0, crfD(ctx->opcode)); >> +} >> + >> /* isel (PowerPC 2.03 specification) */ >> static void gen_isel(DisasContext *ctx) >> { >> @@ -8638,10 +8666,14 @@ GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE >> >> static opcode_t opcodes[] = { >> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), >> -GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), >> -GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), >> -GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), >> -GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), >> +GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_64B), >> +GEN_HANDLER_E(cmp32, 0x1F, 0x00, 0x00, 0x00400000, PPC_NONE, PPC2_32B), > > You have to declare the L bit as invalid, so that trying to execute a > 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction > exception. You're right. I wanted to verify it against a real 32bit system first. It does indeed treat the L bit as reserved. Then we can simply remove the 32bit only variant handlers and only use the opcode table for the reserved bits. Alex ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops 2013-05-08 10:29 ` Aurelien Jarno 2013-05-08 10:33 ` Alexander Graf @ 2013-05-08 10:34 ` Torbjorn Granlund 2013-05-08 10:38 ` Alexander Graf 2013-05-08 11:16 ` Aurelien Jarno 1 sibling, 2 replies; 8+ messages in thread From: Torbjorn Granlund @ 2013-05-08 10:34 UTC (permalink / raw) To: Aurelien Jarno Cc: qemu-devel, Torbjorn Granlund, qemu-ppc, Alexander Graf, Richard Henderson Aurelien Jarno <aurelien@aurel32.net> writes: You have to declare the L bit as invalid, so that trying to execute a 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction exception. Don't people read what I write? I give up. Goodbye. -- Torbjörn ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops 2013-05-08 10:34 ` Torbjorn Granlund @ 2013-05-08 10:38 ` Alexander Graf 2013-05-08 11:16 ` Aurelien Jarno 1 sibling, 0 replies; 8+ messages in thread From: Alexander Graf @ 2013-05-08 10:38 UTC (permalink / raw) To: Torbjorn Granlund; +Cc: qemu-ppc, qemu-devel, Aurelien Jarno, Richard Henderson On 08.05.2013, at 12:34, Torbjorn Granlund wrote: > Aurelien Jarno <aurelien@aurel32.net> writes: > > You have to declare the L bit as invalid, so that trying to execute a > 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction > exception. > > Don't people read what I write? At least on my e500mc machine I happen to have handy, the following instruction gives me an illegal instruction exception: 10000320: 2f a0 00 00 cmpi cr7,1,r0,0 So for 32bit CPU types we have to mark the L bit invalid which means we always get into the branches that take us to cmp32. For 64bit capable CPUs we obviously want to honor the L bit even when running in 32bit mode (MSR.SF=0), as that's what real CPUs do. Alex ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops 2013-05-08 10:34 ` Torbjorn Granlund 2013-05-08 10:38 ` Alexander Graf @ 2013-05-08 11:16 ` Aurelien Jarno 1 sibling, 0 replies; 8+ messages in thread From: Aurelien Jarno @ 2013-05-08 11:16 UTC (permalink / raw) To: Torbjorn Granlund; +Cc: qemu-devel, qemu-ppc, Alexander Graf, Richard Henderson On Wed, May 08, 2013 at 12:34:26PM +0200, Torbjorn Granlund wrote: > Aurelien Jarno <aurelien@aurel32.net> writes: > > You have to declare the L bit as invalid, so that trying to execute a > 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction > exception. > > Don't people read what I write? > Quoting the "IBM PowerPC Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors": | Note: In 32-bit implementations, if L = 1 the instruction form is invalid. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2013-05-08 11:17 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-05-08 10:06 [Qemu-devel] [PATCH] PPC: Fix cmp on 32bit only targets Alexander Graf 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Add 32bit instruction flag Alexander Graf 2013-05-08 10:06 ` [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops Alexander Graf 2013-05-08 10:29 ` Aurelien Jarno 2013-05-08 10:33 ` Alexander Graf 2013-05-08 10:34 ` Torbjorn Granlund 2013-05-08 10:38 ` Alexander Graf 2013-05-08 11:16 ` Aurelien Jarno
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