From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ua73N-0005Aq-6t for qemu-devel@nongnu.org; Wed, 08 May 2013 12:17:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ua73K-0005ya-SR for qemu-devel@nongnu.org; Wed, 08 May 2013 12:17:17 -0400 Date: Wed, 8 May 2013 18:16:54 +0200 From: Aurelien Jarno Message-ID: <20130508161654.GT5000@ohm.aurel32.net> References: <1368019560-25218-1-git-send-email-agraf@suse.de> <20130508142515.GS5000@ohm.aurel32.net> <86sj1xv87d.fsf@shell.gmplib.org> <20130508150412.GB31148@hall.aurel32.net> <86d2t1v558.fsf@shell.gmplib.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <86d2t1v558.fsf@shell.gmplib.org> Subject: Re: [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instructions only on instruction encoding List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Torbjorn Granlund Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Wed, May 08, 2013 at 05:54:27PM +0200, Torbjorn Granlund wrote: > Aurelien Jarno writes: > > As it seems you have good contact with IBM, could you please ask them > to fix their manuals? > > What flaw have your found? Don't people read what I write? From one of my previous email: Quoting the "IBM PowerPC Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors": | Note: In 32-bit implementations, if L = 1 the instruction form is invalid. This doesn't match what your contact says. > At least Freescale CPUs match what IBM documentation says. > > Which ones? Freescale 7447 and Freescale e500 disagree. (Or at least > some versions of these chips, perhaps newer e500 steppings ignore the L > bit.) The e500 CPU doesn't ignore the L bit, like the IBM manual says. > IBM CPUs don't. > > Which ones? The one from your contact saying that reserved fields should be ignored by hardware. > No it's not correct, it doesn't match neither Freescale nor IBM > behaviour. It also means the same code executed on a 32-bit emulated CPU > run with qemu-system-ppc will behave differently than when run with > qemu-system-ppc64. This is fine for now as we are in freeze period, but > should be fixed afterwards. > > I think one should check if it is a 64-bit CPU vs 32-bit CPU, as your > patch did. (If I read it correctly; while I am an expert in the area, I > am very little familiar with qemu's innards.) Except that it should > probably not cast an exception (but I think either way there is no > calamity). > Looking more into details about the issue. Old *PowerPC* manuals (the one from the 7447 era) clearly states that the L bit must trigger an invalid instruction exception. *POWER* manuals states that reserved fields in instructions are ignored by on Server environment, but not on Embedded environment, though it is now phased-in on the latter. In short everybody is correct, it only depends on the CPU. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net