From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52653) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ua9Nk-0005EK-9M for qemu-devel@nongnu.org; Wed, 08 May 2013 14:46:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ua9Ni-0003q3-AA for qemu-devel@nongnu.org; Wed, 08 May 2013 14:46:28 -0400 Date: Wed, 8 May 2013 20:46:11 +0200 From: Aurelien Jarno Message-ID: <20130508184611.GU5000@ohm.aurel32.net> References: <1368037316-11138-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1368037316-11138-1-git-send-email-agraf@suse.de> Subject: Re: [Qemu-devel] [PATCH v2] PPC: Depend behavior of cmp instructions only on instruction encoding List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Torbjorn Granlund , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Richard Henderson On Wed, May 08, 2013 at 08:21:56PM +0200, Alexander Graf wrote: > When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, it > still behaves identical to what it does when SF is on. Remove the implicit > difference in the code. > > Also, on most 32bit CPUs we should always treat the compare as 32bit > compare, as the CPU will ignore the L bit. This is not true for e500mc, > but that's up for a different patch. > > Reported-by: Torbjorn Granlund > Reviewed-by: Richard Henderson > Signed-off-by: Alexander Graf > > --- > > v1 -> v2: > > - ignore L bit > --- > target-ppc/translate.c | 32 ++++++++++++++++---------------- > 1 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index a018616..4590c6f 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -675,48 +675,48 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) > /* cmp */ > static void gen_cmp(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > - 1, crfD(ctx->opcode)); > - } else { > + if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { > gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > 1, crfD(ctx->opcode)); > + } else { > + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > + 1, crfD(ctx->opcode)); > } > } > > /* cmpi */ > static void gen_cmpi(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), > - 1, crfD(ctx->opcode)); > - } else { > + if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { > gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), > 1, crfD(ctx->opcode)); > + } else { > + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), > + 1, crfD(ctx->opcode)); > } > } > > /* cmpl */ > static void gen_cmpl(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > - 0, crfD(ctx->opcode)); > - } else { > + if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { > gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > 0, crfD(ctx->opcode)); > + } else { > + gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], > + 0, crfD(ctx->opcode)); > } > } > > /* cmpli */ > static void gen_cmpli(DisasContext *ctx) > { > - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { > - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), > - 0, crfD(ctx->opcode)); > - } else { > + if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { > gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), > 0, crfD(ctx->opcode)); > + } else { > + gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), > + 0, crfD(ctx->opcode)); > } > } > Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net