From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([208.118.235.92]:41678)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <aurelien@aurel32.net>) id 1Ue48y-0003eE-Ni
	for qemu-devel@nongnu.org; Sun, 19 May 2013 09:59:30 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <aurelien@aurel32.net>) id 1Ue48t-0001EM-FH
	for qemu-devel@nongnu.org; Sun, 19 May 2013 09:59:24 -0400
Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:33814)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <aurelien@aurel32.net>) id 1Ue48t-0001EB-7C
	for qemu-devel@nongnu.org; Sun, 19 May 2013 09:59:19 -0400
Date: Sun, 19 May 2013 15:59:16 +0200
From: Aurelien Jarno <aurelien@aurel32.net>
Message-ID: <20130519135916.GC5144@ohm.aurel32.net>
References: <1368458075-18819-1-git-send-email-petar.jovanovic@rt-rk.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-15
Content-Disposition: inline
In-Reply-To: <1368458075-18819-1-git-send-email-petar.jovanovic@rt-rk.com>
Subject: Re: [Qemu-devel] [PATCH] target-mips: set carry bit correctly in
 DSPControl register
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Petar Jovanovic <petar.jovanovic@rt-rk.com>
Cc: qemu-devel@nongnu.org, petar.jovanovic@imgtec.com

On Mon, May 13, 2013 at 05:14:35PM +0200, Petar Jovanovic wrote:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
> 
> First we need to clear the bit and then we set the given value.
> Instruction ADDSC sets the bit and instruction ADDWC uses this bit.
> 
> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
> ---
>  target-mips/dsp_helper.c |    7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index 9212789..e98bac8 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -53,9 +53,10 @@ static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
>      env->active_tc.DSPControl |= (target_ulong)flag << position;
>  }
>  
> -static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
> +static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env)
>  {
> -    env->active_tc.DSPControl |= (target_ulong)flag << 13;
> +    env->active_tc.DSPControl &= ~(1 << 13);
> +    env->active_tc.DSPControl |= flag << 13;
>  }
>  
>  static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
> @@ -1266,7 +1267,7 @@ SUBUH_QB(subuh_r, 1);
>  target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
>  {
>      uint64_t temp, tempRs, tempRt;
> -    int32_t flag;
> +    bool flag;
>  
>      tempRs = (uint64_t)rs & MIPSDSP_LLO;
>      tempRt = (uint64_t)rt & MIPSDSP_LLO;

Thanks, applied.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net