From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UeTaw-0002IM-Hr for qemu-devel@nongnu.org; Mon, 20 May 2013 13:10:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UeTaq-0003pr-5b for qemu-devel@nongnu.org; Mon, 20 May 2013 13:09:58 -0400 Received: from mail-ia0-x22a.google.com ([2607:f8b0:4001:c02::22a]:46941) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UeTaq-0003pg-0f for qemu-devel@nongnu.org; Mon, 20 May 2013 13:09:52 -0400 Received: by mail-ia0-f170.google.com with SMTP id l29so7882663iag.15 for ; Mon, 20 May 2013 10:09:51 -0700 (PDT) From: Bjorn Helgaas Date: Mon, 20 May 2013 11:09:49 -0600 Message-ID: <20130520170949.29259.99889.stgit@bhelgaas-glaptop> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 1/2] pcie: Use same Link Capabilities defines as Linux kernel List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org Linux actually doesn't have definitions for the individual L0s and L1 bits in Link Capabilities, but if/when it does, it will use these names, which follow the Link Control naming pattern. Signed-off-by: Bjorn Helgaas --- hw/pci/pcie.c | 2 +- include/hw/pci/pcie_regs.h | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 62bd0b8..54fcac8 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -73,7 +73,7 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) pci_set_long(exp_cap + PCI_EXP_LNKCAP, (port << PCI_EXP_LNKCAP_PN_SHIFT) | - PCI_EXP_LNKCAP_ASPMS_0S | + PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 4d123d9..109f2f4 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -39,8 +39,7 @@ #define PCI_EXP_LNK_MLW_1 (1 << PCI_EXP_LNK_MLW_SHIFT) /* PCI_EXP_LINKCAP */ -#define PCI_EXP_LNKCAP_ASPMS_SHIFT (ffs(PCI_EXP_LNKCAP_ASPMS) - 1) -#define PCI_EXP_LNKCAP_ASPMS_0S (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT) +#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* L0s supported */ #define PCI_EXP_LNKCAP_PN_SHIFT (ffs(PCI_EXP_LNKCAP_PN) - 1)