From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui2NO-0002hC-7l for qemu-devel@nongnu.org; Thu, 30 May 2013 08:54:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ui2NI-0005NH-4o for qemu-devel@nongnu.org; Thu, 30 May 2013 08:54:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:63187) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui2NH-0005ND-S8 for qemu-devel@nongnu.org; Thu, 30 May 2013 08:54:36 -0400 Date: Thu, 30 May 2013 15:55:03 +0300 From: "Michael S. Tsirkin" Message-ID: <20130530125503.GE12791@redhat.com> References: <1369911913-10934-1-git-send-email-mst@redhat.com> <1369911913-10934-3-git-send-email-mst@redhat.com> <51A7430D.7060102@redhat.com> <20130530121950.GA12791@redhat.com> <51A746C1.5050902@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51A746C1.5050902@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 2/5] pci: store PCI hole ranges in guestinfo structure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: Anthony Liguori , qemu-devel@nongnu.org On Thu, May 30, 2013 at 02:32:01PM +0200, Gerd Hoffmann wrote: > On 05/30/13 14:19, Michael S. Tsirkin wrote: > > On Thu, May 30, 2013 at 02:16:13PM +0200, Gerd Hoffmann wrote: > >> Hi, > >> > >>> + } else { > >>> + guest_info->pci_info.w64.begin = 0x100000000ULL + above_4g_mem_size; > >>> + guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin + > >>> + (0x1ULL << 62); > >> > >> Doesn't this give unaligned windows? > > > > PCI Bridge windows do not need to be size aligned. > > > > In any case, the windows are *exactly* as calculated > > by seabios - apparently it does not size-align windows either. > > Surely not. SeaBIOS sizes the 64bit window according to the space > needed by the 64bit bars it wants to map there. Ah, it's 64 bit. True. That's a seabios bug by the way: if we add more devices by hotplug later, we want more pci memory. > >>> + /* Set PCI window size the way seabios has always done it. */ > >>> + /* TODO: consider just starting at below_4g_mem_size */ > >> > >> Used to be that way. Was changed for alignment reasons (i.e. 1G window > >> starts at 1G border etc). > > > > Where's the alignment requirement coming from? > > seabios creates a mtrr entry for the window, which doesn't work in case > it isn't aligned (at least not with a single entry). > > Also real hardware tends to do it this way. > > cheers, > Gerd I see. I'll figure out the details and add a comment to this end. But that's for the 32 bit window - I don't see it playing with mtrrs for the 64 bit ranges. So I'm guessing alignment isn't needed there, right? -- MST