From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54651) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UiB6f-0007NC-Ae for qemu-devel@nongnu.org; Thu, 30 May 2013 18:14:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UiB6c-0000u0-Kp for qemu-devel@nongnu.org; Thu, 30 May 2013 18:14:01 -0400 Received: from mail-pb0-x22b.google.com ([2607:f8b0:400e:c01::22b]:57979) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UiB6c-0000s2-Dp for qemu-devel@nongnu.org; Thu, 30 May 2013 18:13:58 -0400 Received: by mail-pb0-f43.google.com with SMTP id ma3so1124298pbc.30 for ; Thu, 30 May 2013 15:13:57 -0700 (PDT) Date: Thu, 30 May 2013 15:13:54 -0700 From: Christoffer Dall Message-ID: <20130530221354.GA57588@ubuntu> References: <1368797037-26976-1-git-send-email-peter.maydell@linaro.org> <1368797037-26976-4-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1368797037-26976-4-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 3/7] target-arm: mark up cpregs for no-migrate or raw access List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , j@ubuntu Cc: patches@linaro.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, Juan Quintela On Fri, May 17, 2013 at 02:23:53PM +0100, Peter Maydell wrote: > Mark up coprocessor register definitions to add raw access > functions or mark the register as non-migratable where necessary. > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 94 ++++++++++++++++++++++++++++++++++----------------- > 1 file changed, 63 insertions(+), 31 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 2585d59..e5e4ed2 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -155,13 +155,17 @@ static const ARMCPRegInfo cp_reginfo[] = { > * the unified TLB ops but also the dside/iside/inner-shareable variants. > */ > { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, > - .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, }, > + .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, > + .type = ARM_CP_NO_MIGRATE }, [...] What happens with registers which don't have the raw_write function set (even though the write function imposes some access checks or has side effects) and also is not marked as ARM_CP_NO_MIGRATE, CONTEXTIDR seems to be such an example. ? -Christoffer