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From: Anton Blanchard <anton@samba.org>
To: david@gibson.dropbear.id.au, agraf@suse.de, rth@twiddle.net,
	aurelien@aurel32.net
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 1/4] tcg-ppc64: Fix RLDCL opcode
Date: Sun, 2 Jun 2013 22:27:23 +1000	[thread overview]
Message-ID: <20130602222723.1e006760@kryten> (raw)
In-Reply-To: <20130602222452.1b0fdbd1@kryten>


The rldcl instruction doesn't have an sh field, so the minor opcode
of 8 is actually 4 when using the XO30 macro.

Cc: qemu-stable@nongnu.org
Signed-off-by: Anton Blanchard <anton@samba.org>
---

Index: b/tcg/ppc64/tcg-target.c
===================================================================
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -357,7 +357,7 @@ static int tcg_target_const_match (tcg_t
 #define RLDICL XO30(  0)
 #define RLDICR XO30(  1)
 #define RLDIMI XO30(  3)
-#define RLDCL  XO30(  8)
+#define RLDCL  XO30(  4)
 
 #define BCLR   XO19( 16)
 #define BCCTR  XO19(528)

  reply	other threads:[~2013-06-02 12:51 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-02 12:24 [Qemu-devel] [PATCH 0/4] Fix ppc64 tcg issues Anton Blanchard
2013-06-02 12:27 ` Anton Blanchard [this message]
2013-06-03 14:28   ` [Qemu-devel] [PATCH 1/4] tcg-ppc64: Fix RLDCL opcode Richard Henderson
2013-06-11 11:19     ` Anton Blanchard
2013-06-11 13:49       ` Richard Henderson
2013-06-02 12:28 ` [Qemu-devel] [PATCH 2/4] tcg-ppc64: bswap64 rotates output 32 bits Anton Blanchard
2013-06-03 14:31   ` Richard Henderson
2013-06-02 12:29 ` [Qemu-devel] [PATCH 3/4] tcg-ppc64: Fix add2_i64 Anton Blanchard
2013-06-03 14:32   ` Richard Henderson
2013-06-02 12:30 ` [Qemu-devel] [PATCH 4/4] tcg-ppc64: rotr_i32 rotates wrong amount Anton Blanchard
2013-06-03 14:33   ` Richard Henderson

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