From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uj7kx-0007cc-W8 for qemu-devel@nongnu.org; Sun, 02 Jun 2013 08:51:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uj7kw-0002BW-Em for qemu-devel@nongnu.org; Sun, 02 Jun 2013 08:51:31 -0400 Received: from ozlabs.org ([203.10.76.45]:49371) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uj7Ne-0003an-Vm for qemu-devel@nongnu.org; Sun, 02 Jun 2013 08:27:27 -0400 Date: Sun, 2 Jun 2013 22:27:23 +1000 From: Anton Blanchard Message-ID: <20130602222723.1e006760@kryten> In-Reply-To: <20130602222452.1b0fdbd1@kryten> References: <20130602222452.1b0fdbd1@kryten> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 1/4] tcg-ppc64: Fix RLDCL opcode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: david@gibson.dropbear.id.au, agraf@suse.de, rth@twiddle.net, aurelien@aurel32.net Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org The rldcl instruction doesn't have an sh field, so the minor opcode of 8 is actually 4 when using the XO30 macro. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard --- Index: b/tcg/ppc64/tcg-target.c =================================================================== --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -357,7 +357,7 @@ static int tcg_target_const_match (tcg_t #define RLDICL XO30( 0) #define RLDICR XO30( 1) #define RLDIMI XO30( 3) -#define RLDCL XO30( 8) +#define RLDCL XO30( 4) #define BCLR XO19( 16) #define BCCTR XO19(528)