From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uphxt-0000CF-JU for qemu-devel@nongnu.org; Thu, 20 Jun 2013 12:44:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uphxq-0005yK-Ql for qemu-devel@nongnu.org; Thu, 20 Jun 2013 12:44:05 -0400 Received: from e39.co.us.ibm.com ([32.97.110.160]:39819) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uphxq-0005tw-HJ for qemu-devel@nongnu.org; Thu, 20 Jun 2013 12:44:02 -0400 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 20 Jun 2013 09:19:43 -0600 Received: from d03relay03.boulder.ibm.com (d03relay03.boulder.ibm.com [9.17.195.228]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 92D0C1FF0020 for ; Thu, 20 Jun 2013 09:14:17 -0600 (MDT) Received: from d03av06.boulder.ibm.com (d03av06.boulder.ibm.com [9.17.195.245]) by d03relay03.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r5KFJT9K127812 for ; Thu, 20 Jun 2013 09:19:29 -0600 Received: from d03av06.boulder.ibm.com (loopback [127.0.0.1]) by d03av06.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r5KFKjiI014594 for ; Thu, 20 Jun 2013 09:20:46 -0600 Date: Thu, 20 Jun 2013 08:18:17 -0700 From: "Paul E. McKenney" Message-ID: <20130620151817.GC4082@linux.vnet.ibm.com> References: <1371381681-14252-1-git-send-email-pingfanl@linux.vnet.ibm.com> <1371381681-14252-2-git-send-email-pingfanl@linux.vnet.ibm.com> <51BF5C0F.6020209@twiddle.net> <51C05F88.2090308@redhat.com> <20130618145033.GN5146@linux.vnet.ibm.com> <1371569862.16968.23402.camel@triegel.csb> <20130619015307.GY5146@linux.vnet.ibm.com> <1371625896.16968.24243.camel@triegel.csb> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1371625896.16968.24243.camel@triegel.csb> Subject: Re: [Qemu-devel] Java volatile vs. C11 seq_cst (was Re: [PATCH v2 1/2] add a header file for atomic operations) Reply-To: paulmck@linux.vnet.ibm.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Torvald Riegel Cc: Susmit.Sarkar@cl.cam.ac.uk, Andrew Haley , qemu-devel@nongnu.org, Liu Ping Fan , Anthony Liguori , luc.maranget@inria.fr, Paolo Bonzini , Peter.Sewell@cl.cam.ac.uk, Richard Henderson On Wed, Jun 19, 2013 at 09:11:36AM +0200, Torvald Riegel wrote: > On Tue, 2013-06-18 at 18:53 -0700, Paul E. McKenney wrote: > > On Tue, Jun 18, 2013 at 05:37:42PM +0200, Torvald Riegel wrote: > > > On Tue, 2013-06-18 at 07:50 -0700, Paul E. McKenney wrote: > > > > First, I am not a fan of SC, mostly because there don't seem to be many > > > > (any?) production-quality algorithms that need SC. But if you really > > > > want to take a parallel-programming trip back to the 1980s, let's go! ;-) > > > > > > Dekker-style mutual exclusion is useful for things like read-mostly > > > multiple-reader single-writer locks, or similar "asymmetric" cases of > > > synchronization. SC fences are needed for this. > > > > They definitely need Power hwsync rather than lwsync, but they need > > fewer fences than would be emitted by slavishly following either of the > > SC recipes for Power. (Another example needing store-to-load ordering > > is hazard pointers.) > > The C++11 seq-cst fence expands to hwsync; combined with a relaxed > store / load, that should be minimal. Or are you saying that on Power, > there is a weaker HW barrier available that still constrains store-load > reordering sufficiently? Your example use of seq-cst fence is a very good one for this example. But most people I have talked to think of C++11 SC as being SC atomic accesses, and SC atomics would get you a bunch of redundant fences in this example -- some but not all of which could be easily optimized away. Thanx, Paul