From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxDTs-00013b-3u for qemu-devel@nongnu.org; Thu, 11 Jul 2013 05:48:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UxDTq-0004pH-P4 for qemu-devel@nongnu.org; Thu, 11 Jul 2013 05:48:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:13646) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxDTq-0004oN-HR for qemu-devel@nongnu.org; Thu, 11 Jul 2013 05:48:06 -0400 Date: Thu, 11 Jul 2013 11:47:59 +0200 From: Igor Mammedov Message-ID: <20130711114759.191f9ed0@nial.usersys.redhat.com> In-Reply-To: References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH qom-next v2 3/5] target-arm: Use parent classes for reset + realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.crosthwaite@xilinx.com Cc: hutao@cn.fujitsu.com, aliguori@us.ibm.com, mst@redhat.com, afaerber@suse.de, qemu-devel@nongnu.org On Thu, 11 Jul 2013 11:47:16 +1000 peter.crosthwaite@xilinx.com wrote: > From: Peter Crosthwaite > > ARMCPUClass is only needed for parent-class abstract function access. > Just use parent classes for reset and realize access and remove > ARMCPUClass completely. > > Signed-off-by: Peter Crosthwaite > --- > > target-arm/cpu-qom.h | 20 -------------------- > target-arm/cpu.c | 16 +++++++--------- > 2 files changed, 7 insertions(+), 29 deletions(-) > > diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h > index ef6261f..bdad93a 100644 > --- a/target-arm/cpu-qom.h > +++ b/target-arm/cpu-qom.h > @@ -24,28 +24,8 @@ > > #define TYPE_ARM_CPU "arm-cpu" > > -#define ARM_CPU_CLASS(klass) \ > - OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) > #define ARM_CPU(obj) \ > OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) > -#define ARM_CPU_GET_CLASS(obj) \ > - OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) > - > -/** > - * ARMCPUClass: > - * @parent_realize: The parent class' realize handler. > - * @parent_reset: The parent class' reset handler. > - * > - * An ARM CPU model. > - */ > -typedef struct ARMCPUClass { > - /*< private >*/ > - CPUClass parent_class; > - /*< public >*/ > - > - DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > -} ARMCPUClass; > > /** > * ARMCPU: > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index ed53df8..ad5ec7b 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -60,7 +60,8 @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) > static void arm_cpu_reset(CPUState *s) > { > ARMCPU *cpu = ARM_CPU(s); > - ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); > + CPUClass *cc_parent = > + CPU_CLASS(object_class_get_parent_by_name(TYPE_ARM_CPU)); Maybe object_class_get_parent_of_type() would be less confusing? This usage assumes that parent of TYPE_ARM_CPU is TYPE_CPU and if another TYPE_X added between them, it might break if TYPE_X doesn't re-implement this logic in its reset. Could reset be modeled like DEVICE.instance_init() instead? Then no explicit access to parent from child would be needed and it still leaves possibility to override resets if parent->child propagation order is not desirable for a particular device. > CPUARMState *env = &cpu->env; > > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > @@ -68,7 +69,7 @@ static void arm_cpu_reset(CPUState *s) > log_cpu_state(env, 0); > } > > - acc->parent_reset(s); > + cc_parent->reset(s); > > memset(env, 0, offsetof(CPUARMState, breakpoints)); > g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); > @@ -158,7 +159,8 @@ static void arm_cpu_finalizefn(Object *obj) > static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > { > ARMCPU *cpu = ARM_CPU(dev); > - ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); > + DeviceClass *dc_parent = > + DEVICE_CLASS(object_class_get_parent_by_name(TYPE_ARM_CPU)); > CPUARMState *env = &cpu->env; > > /* Some features automatically imply others: */ > @@ -209,7 +211,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > > cpu_reset(CPU(cpu)); > > - acc->parent_realize(dev, errp); > + dc_parent->realize(dev, errp); > } > > /* CPU models */ > @@ -803,14 +805,11 @@ static const ARMCPUInfo arm_cpus[] = { > > static void arm_cpu_class_init(ObjectClass *oc, void *data) > { > - ARMCPUClass *acc = ARM_CPU_CLASS(oc); > - CPUClass *cc = CPU_CLASS(acc); > + CPUClass *cc = CPU_CLASS(oc); > DeviceClass *dc = DEVICE_CLASS(oc); > > - acc->parent_realize = dc->realize; > dc->realize = arm_cpu_realizefn; > > - acc->parent_reset = cc->reset; > cc->reset = arm_cpu_reset; > > cc->class_by_name = arm_cpu_class_by_name; > @@ -839,7 +838,6 @@ static const TypeInfo arm_cpu_type_info = { > .instance_init = arm_cpu_initfn, > .instance_finalize = arm_cpu_finalizefn, > .abstract = true, > - .class_size = sizeof(ARMCPUClass), > .class_init = arm_cpu_class_init, > }; >