From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48789) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2T6O-00078B-NB for qemu-devel@nongnu.org; Thu, 25 Jul 2013 17:29:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V2Shm-00045U-Cv for qemu-devel@nongnu.org; Thu, 25 Jul 2013 17:04:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:1637) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2Shl-00045F-VI for qemu-devel@nongnu.org; Thu, 25 Jul 2013 17:04:10 -0400 Date: Fri, 26 Jul 2013 00:05:29 +0300 From: "Michael S. Tsirkin" Message-ID: <20130725210529.GB20471@redhat.com> References: <1374532568-28051-1-git-send-email-afaerber@suse.de> <1374532568-28051-5-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <1374532568-28051-5-git-send-email-afaerber@suse.de> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qom-next v2 4/4] pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?iso-8859-1?Q?F=E4rber?= Cc: qemu-devel@nongnu.org On Tue, Jul 23, 2013 at 12:36:08AM +0200, Andreas F=E4rber wrote: > Move PCIEPort's "port" property to the new type, same for "aer_log_max". > Move PCIESlot's "chassis" and "slot" properties to the new type. >=20 > Signed-off-by: Andreas F=E4rber > --- > hw/pci-bridge/ioh3420.c | 31 ++++++----------------- > hw/pci-bridge/xio3130_downstream.c | 31 ++++++----------------- > hw/pci-bridge/xio3130_upstream.c | 21 ++++----------- > hw/pci/pcie_port.c | 52 ++++++++++++++++++++++++++++++= ++++++++ > include/hw/pci/pcie_port.h | 14 ++++++++-- > 5 files changed, 85 insertions(+), 64 deletions(-) >=20 > diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c > index 728f658..e07c7e8 100644 > --- a/hw/pci-bridge/ioh3420.c > +++ b/hw/pci-bridge/ioh3420.c > @@ -92,9 +92,8 @@ static void ioh3420_reset(DeviceState *qdev) > =20 > static int ioh3420_initfn(PCIDevice *d) > { > - PCIBridge *br =3D PCI_BRIDGE(d); > - PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > - PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > + PCIEPort *p =3D PCIE_PORT(d); > + PCIESlot *s =3D PCIE_SLOT(d); > int rc; > =20 > rc =3D pci_bridge_initfn(d, TYPE_PCIE_BUS); > @@ -148,9 +147,7 @@ err_bridge: > =20 > static void ioh3420_exitfn(PCIDevice *d) > { > - PCIBridge *br =3D PCI_BRIDGE(d); > - PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > - PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > + PCIESlot *s =3D PCIE_SLOT(d); > =20 > pcie_aer_exit(d); > pcie_chassis_del_slot(s); > @@ -180,7 +177,7 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool= multifunction, > qdev_prop_set_uint16(qdev, "slot", slot); > qdev_init_nofail(qdev); > =20 > - return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br)); > + return PCIE_SLOT(d); > } > =20 > static const VMStateDescription vmstate_ioh3420 =3D { > @@ -190,23 +187,13 @@ static const VMStateDescription vmstate_ioh3420 =3D= { > .minimum_version_id_old =3D 1, > .post_load =3D pcie_cap_slot_post_load, > .fields =3D (VMStateField[]) { > - VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot), > - VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0, > - vmstate_pcie_aer_log, PCIEAERLog), > + VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot= ), > + VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, > + PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), > VMSTATE_END_OF_LIST() > } > }; > =20 > -static Property ioh3420_properties[] =3D { > - DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), > - DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), > - DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), > - DEFINE_PROP_UINT16("aer_log_max", PCIESlot, > - port.br.parent_obj.exp.aer_log.log_max, > - PCIE_AER_LOG_MAX_DEFAULT), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void ioh3420_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > @@ -223,13 +210,11 @@ static void ioh3420_class_init(ObjectClass *klass= , void *data) > dc->desc =3D "Intel IOH device id 3420 PCIE Root Port"; > dc->reset =3D ioh3420_reset; > dc->vmsd =3D &vmstate_ioh3420; > - dc->props =3D ioh3420_properties; > } > =20 > static const TypeInfo ioh3420_info =3D { > .name =3D "ioh3420", > - .parent =3D TYPE_PCI_BRIDGE, > - .instance_size =3D sizeof(PCIESlot), > + .parent =3D TYPE_PCIE_SLOT, > .class_init =3D ioh3420_class_init, > }; > =20 > diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130= _downstream.c > index 9acce3f..2c84b1a 100644 > --- a/hw/pci-bridge/xio3130_downstream.c > +++ b/hw/pci-bridge/xio3130_downstream.c > @@ -56,9 +56,8 @@ static void xio3130_downstream_reset(DeviceState *qde= v) > =20 > static int xio3130_downstream_initfn(PCIDevice *d) > { > - PCIBridge *br =3D PCI_BRIDGE(d); > - PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > - PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > + PCIEPort *p =3D PCIE_PORT(d); > + PCIESlot *s =3D PCIE_SLOT(d); > int rc; > =20 > rc =3D pci_bridge_initfn(d, TYPE_PCIE_BUS); > @@ -113,9 +112,7 @@ err_bridge: > =20 > static void xio3130_downstream_exitfn(PCIDevice *d) > { > - PCIBridge *br =3D PCI_BRIDGE(d); > - PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > - PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > + PCIESlot *s =3D PCIE_SLOT(d); > =20 > pcie_aer_exit(d); > pcie_chassis_del_slot(s); > @@ -147,7 +144,7 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int = devfn, bool multifunction, > qdev_prop_set_uint16(qdev, "slot", slot); > qdev_init_nofail(qdev); > =20 > - return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br)); > + return PCIE_SLOT(d); > } > =20 > static const VMStateDescription vmstate_xio3130_downstream =3D { > @@ -157,23 +154,13 @@ static const VMStateDescription vmstate_xio3130_d= ownstream =3D { > .minimum_version_id_old =3D 1, > .post_load =3D pcie_cap_slot_post_load, > .fields =3D (VMStateField[]) { > - VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot), > - VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0, > - vmstate_pcie_aer_log, PCIEAERLog), > + VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot= ), > + VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, > + PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), > VMSTATE_END_OF_LIST() > } > }; > =20 > -static Property xio3130_downstream_properties[] =3D { > - DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), > - DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), > - DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), > - DEFINE_PROP_UINT16("aer_log_max", PCIESlot, > - port.br.parent_obj.exp.aer_log.log_max, > - PCIE_AER_LOG_MAX_DEFAULT), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void xio3130_downstream_class_init(ObjectClass *klass, void *da= ta) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > @@ -190,13 +177,11 @@ static void xio3130_downstream_class_init(ObjectC= lass *klass, void *data) > dc->desc =3D "TI X3130 Downstream Port of PCI Express Switch"; > dc->reset =3D xio3130_downstream_reset; > dc->vmsd =3D &vmstate_xio3130_downstream; > - dc->props =3D xio3130_downstream_properties; > } > =20 > static const TypeInfo xio3130_downstream_info =3D { > .name =3D "xio3130-downstream", > - .parent =3D TYPE_PCI_BRIDGE, > - .instance_size =3D sizeof(PCIESlot), > + .parent =3D TYPE_PCIE_SLOT, > .class_init =3D xio3130_downstream_class_init, > }; > =20 > diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_u= pstream.c > index 0bc1d05..82add15 100644 > --- a/hw/pci-bridge/xio3130_upstream.c > +++ b/hw/pci-bridge/xio3130_upstream.c > @@ -53,8 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev) > =20 > static int xio3130_upstream_initfn(PCIDevice *d) > { > - PCIBridge *br =3D PCI_BRIDGE(d); > - PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > + PCIEPort *p =3D PCIE_PORT(d); > int rc; > =20 > rc =3D pci_bridge_initfn(d, TYPE_PCIE_BUS); > @@ -125,7 +124,7 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int de= vfn, bool multifunction, > qdev_prop_set_uint8(qdev, "port", port); > qdev_init_nofail(qdev); > =20 > - return DO_UPCAST(PCIEPort, br, br); > + return PCIE_PORT(d); > } > =20 > static const VMStateDescription vmstate_xio3130_upstream =3D { > @@ -134,21 +133,13 @@ static const VMStateDescription vmstate_xio3130_u= pstream =3D { > .minimum_version_id =3D 1, > .minimum_version_id_old =3D 1, > .fields =3D (VMStateField[]) { > - VMSTATE_PCIE_DEVICE(br.parent_obj, PCIEPort), > - VMSTATE_STRUCT(br.parent_obj.exp.aer_log, PCIEPort, 0, > + VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort), > + VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, > vmstate_pcie_aer_log, PCIEAERLog), So this horror is due to insistance of calling the first structure in each struct "parent_obj". I never understood why it's a good idea. > VMSTATE_END_OF_LIST() > } > }; > =20 > -static Property xio3130_upstream_properties[] =3D { > - DEFINE_PROP_UINT8("port", PCIEPort, port, 0), > - DEFINE_PROP_UINT16("aer_log_max", PCIEPort, > - br.parent_obj.exp.aer_log.log_max, > - PCIE_AER_LOG_MAX_DEFAULT), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void xio3130_upstream_class_init(ObjectClass *klass, void *data= ) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > @@ -165,13 +156,11 @@ static void xio3130_upstream_class_init(ObjectCla= ss *klass, void *data) > dc->desc =3D "TI X3130 Upstream Port of PCI Express Switch"; > dc->reset =3D xio3130_upstream_reset; > dc->vmsd =3D &vmstate_xio3130_upstream; > - dc->props =3D xio3130_upstream_properties; > } > =20 > static const TypeInfo xio3130_upstream_info =3D { > .name =3D "x3130-upstream", > - .parent =3D TYPE_PCI_BRIDGE, > - .instance_size =3D sizeof(PCIEPort), > + .parent =3D TYPE_PCIE_PORT, > .class_init =3D xio3130_upstream_class_init, > }; > =20 > diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c > index 91b53a0..2adb030 100644 > --- a/hw/pci/pcie_port.c > +++ b/hw/pci/pcie_port.c > @@ -116,3 +116,55 @@ void pcie_chassis_del_slot(PCIESlot *s) > { > QLIST_REMOVE(s, next); > } > + > +static Property pcie_port_props[] =3D { > + DEFINE_PROP_UINT8("port", PCIEPort, port, 0), > + DEFINE_PROP_UINT16("aer_log_max", PCIEPort, > + parent_obj.parent_obj.exp.aer_log.log_max, > + PCIE_AER_LOG_MAX_DEFAULT), > + DEFINE_PROP_END_OF_LIST() > +}; > + > +static void pcie_port_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(oc); > + > + dc->props =3D pcie_port_props; > +} > + > +static const TypeInfo pcie_port_type_info =3D { > + .name =3D TYPE_PCIE_PORT, > + .parent =3D TYPE_PCI_BRIDGE, > + .instance_size =3D sizeof(PCIEPort), > + .abstract =3D true, > + .class_init =3D pcie_port_class_init, > +}; > + > +static Property pcie_slot_props[] =3D { > + DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), > + DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), > + DEFINE_PROP_END_OF_LIST() > +}; > + > +static void pcie_slot_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(oc); > + > + dc->props =3D pcie_slot_props; > +} > + > +static const TypeInfo pcie_slot_type_info =3D { > + .name =3D TYPE_PCIE_SLOT, > + .parent =3D TYPE_PCIE_PORT, > + .instance_size =3D sizeof(PCIESlot), > + .abstract =3D true, > + .class_init =3D pcie_slot_class_init, > +}; > + > +static void pcie_port_register_types(void) > +{ > + type_register_static(&pcie_port_type_info); > + type_register_static(&pcie_slot_type_info); > +} > + > +type_init(pcie_port_register_types) > diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h > index d89aa61..e167bf7 100644 > --- a/include/hw/pci/pcie_port.h > +++ b/include/hw/pci/pcie_port.h > @@ -24,8 +24,13 @@ > #include "hw/pci/pci_bridge.h" > #include "hw/pci/pci_bus.h" > =20 > +#define TYPE_PCIE_PORT "pcie-port" > +#define PCIE_PORT(obj) OBJECT_CHECK(PCIEPort, (obj), TYPE_PCIE_PORT) > + > struct PCIEPort { > - PCIBridge br; > + /*< private >*/ > + PCIBridge parent_obj; > + /*< public >*/ > =20 > /* pci express switch port */ > uint8_t port; > @@ -33,8 +38,13 @@ struct PCIEPort { > =20 > void pcie_port_init_reg(PCIDevice *d); > =20 > +#define TYPE_PCIE_SLOT "pcie-slot" > +#define PCIE_SLOT(obj) OBJECT_CHECK(PCIESlot, (obj), TYPE_PCIE_SLOT) > + > struct PCIESlot { > - PCIEPort port; > + /*< private >*/ > + PCIEPort parent_obj; > + /*< public >*/ > =20 > /* pci express switch port with slot */ > uint8_t chassis; I don't like how everthing is called parent_obj instead of what it really is, but since this appears to be in vogue at the moment Acked-by: Michael S. Tsirkin > --=20 > 1.8.1.4