Re: [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE

[Aurelien Jarno <aurelien@aurel32.net>]

On Fri, Aug 02, 2013 at 10:33:43AM +0100, Yongbok Kim wrote:
> 34Kf core does support DSP ASE.
> CP0_Config3 configuration for 34Kf and description are wrong.
> 
> Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
> changes from v1:
> make status.MX writeable 
> 
>  target-mips/translate_init.c |    7 +++----
>  1 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 7cf238f..c45b1b2 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] =
>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>                         (1 << CP0C1_CA),
>          .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
> +                       (1 << CP0C3_DSPP),
>          .CP0_LLAddr_rw_bitmask = 0,
>          .CP0_LLAddr_shift = 0,
>          .SYNCI_Step = 32,
>          .CCRes = 2,
> -        /* No DSP implemented. */
> -        .CP0_Status_rw_bitmask = 0x3678FF1F,
> -        /* No DSP implemented. */
> +        .CP0_Status_rw_bitmask = 0x3778FF1F,
>          .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
>                      (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
>                      (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |

Thanks, applied.


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net