From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V5ju0-0006IU-CN for qemu-devel@nongnu.org; Sat, 03 Aug 2013 18:02:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V5jtz-0004gV-2h for qemu-devel@nongnu.org; Sat, 03 Aug 2013 18:02:20 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:56024) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V5jty-0004gN-SM for qemu-devel@nongnu.org; Sat, 03 Aug 2013 18:02:19 -0400 Date: Sun, 4 Aug 2013 00:02:16 +0200 From: Aurelien Jarno Message-ID: <20130803220216.GA4193@ohm.aurel32.net> References: <1375436023-38466-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1375436023-38466-1-git-send-email-yongbok.kim@imgtec.com> Subject: Re: [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: cristian.cuna@imgtec.com, leon.alrae@imgtec.com, qemu-devel@nongnu.org, Eric.Johnson@imgtec.com On Fri, Aug 02, 2013 at 10:33:43AM +0100, Yongbok Kim wrote: > 34Kf core does support DSP ASE. > CP0_Config3 configuration for 34Kf and description are wrong. > > Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet > > Signed-off-by: Yongbok Kim > --- > changes from v1: > make status.MX writeable > > target-mips/translate_init.c | 7 +++---- > 1 files changed, 3 insertions(+), 4 deletions(-) > > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c > index 7cf238f..c45b1b2 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] = > (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | > (1 << CP0C1_CA), > .CP0_Config2 = MIPS_CONFIG2, > - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT), > + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | > + (1 << CP0C3_DSPP), > .CP0_LLAddr_rw_bitmask = 0, > .CP0_LLAddr_shift = 0, > .SYNCI_Step = 32, > .CCRes = 2, > - /* No DSP implemented. */ > - .CP0_Status_rw_bitmask = 0x3678FF1F, > - /* No DSP implemented. */ > + .CP0_Status_rw_bitmask = 0x3778FF1F, > .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | > (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | > (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | Thanks, applied. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net