* [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE
@ 2013-08-02 9:33 Yongbok Kim
2013-08-03 22:02 ` Aurelien Jarno
0 siblings, 1 reply; 3+ messages in thread
From: Yongbok Kim @ 2013-08-02 9:33 UTC (permalink / raw)
To: qemu-devel; +Cc: yongbok.kim, cristian.cuna, leon.alrae, aurelien, Eric.Johnson
34Kf core does support DSP ASE.
CP0_Config3 configuration for 34Kf and description are wrong.
Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
changes from v1:
make status.MX writeable
target-mips/translate_init.c | 7 +++----
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 7cf238f..c45b1b2 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
+ (1 << CP0C3_DSPP),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
.CCRes = 2,
- /* No DSP implemented. */
- .CP0_Status_rw_bitmask = 0x3678FF1F,
- /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
--
1.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE
2013-08-02 9:33 [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE Yongbok Kim
@ 2013-08-03 22:02 ` Aurelien Jarno
2013-09-13 16:47 ` Maciej W. Rozycki
0 siblings, 1 reply; 3+ messages in thread
From: Aurelien Jarno @ 2013-08-03 22:02 UTC (permalink / raw)
To: Yongbok Kim; +Cc: cristian.cuna, leon.alrae, qemu-devel, Eric.Johnson
On Fri, Aug 02, 2013 at 10:33:43AM +0100, Yongbok Kim wrote:
> 34Kf core does support DSP ASE.
> CP0_Config3 configuration for 34Kf and description are wrong.
>
> Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
>
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
> changes from v1:
> make status.MX writeable
>
> target-mips/translate_init.c | 7 +++----
> 1 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 7cf238f..c45b1b2 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] =
> (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
> (1 << CP0C1_CA),
> .CP0_Config2 = MIPS_CONFIG2,
> - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
> + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
> + (1 << CP0C3_DSPP),
> .CP0_LLAddr_rw_bitmask = 0,
> .CP0_LLAddr_shift = 0,
> .SYNCI_Step = 32,
> .CCRes = 2,
> - /* No DSP implemented. */
> - .CP0_Status_rw_bitmask = 0x3678FF1F,
> - /* No DSP implemented. */
> + .CP0_Status_rw_bitmask = 0x3778FF1F,
> .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
> (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
> (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
Thanks, applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE
2013-08-03 22:02 ` Aurelien Jarno
@ 2013-09-13 16:47 ` Maciej W. Rozycki
0 siblings, 0 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2013-09-13 16:47 UTC (permalink / raw)
To: Aurelien Jarno
Cc: Yongbok Kim, cristian.cuna, leon.alrae, qemu-devel, Eric.Johnson
On Sat, 3 Aug 2013, Aurelien Jarno wrote:
> > 34Kf core does support DSP ASE.
> > CP0_Config3 configuration for 34Kf and description are wrong.
> >
> > Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
> >
> > Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> > ---
> > changes from v1:
> > make status.MX writeable
> >
> > target-mips/translate_init.c | 7 +++----
> > 1 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> > index 7cf238f..c45b1b2 100644
> > --- a/target-mips/translate_init.c
> > +++ b/target-mips/translate_init.c
> > @@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] =
> > (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
> > (1 << CP0C1_CA),
> > .CP0_Config2 = MIPS_CONFIG2,
> > - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
> > + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
> > + (1 << CP0C3_DSPP),
> > .CP0_LLAddr_rw_bitmask = 0,
> > .CP0_LLAddr_shift = 0,
> > .SYNCI_Step = 32,
> > .CCRes = 2,
> > - /* No DSP implemented. */
> > - .CP0_Status_rw_bitmask = 0x3678FF1F,
> > - /* No DSP implemented. */
> > + .CP0_Status_rw_bitmask = 0x3778FF1F,
> > .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
> > (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
> > (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
And likewise CP0.TCStatus.TMX has to be set (to match CP0.Status.MX):
(1 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
> Thanks, applied.
Maciej
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-08-02 9:33 [Qemu-devel] [PATCH v2] target-mips: fix 34Kf configuration for DSP ASE Yongbok Kim
2013-08-03 22:02 ` Aurelien Jarno
2013-09-13 16:47 ` Maciej W. Rozycki
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